The TRB3 features four FPGA-based TDCs with <20ps RMS time precision
between two channels and 256+4 channels in total. One central FPGA
provides flexible trigger functionality and GbE connectivity including
-powerful slow control. We present the recent users' applications of
-this platform following the COME&KISS principle: Successful test
-beamtimes at CERN (CBM), in Jülich and Mainz with an FPGA-based
-discriminator board (PaDiWa), a charge-to-width FEE board with high
-dynamic range, read-out of the n-XYTER ASIC and software for data
-unpacking and TDC calibration. We conclude with an outlook on future
-developments.
+powerful slow control. We present recent users' applications of this
+platform following the COME&KISS principle: Successful test beamtimes
+at CERN (CBM), in Juelich and Mainz with an FPGA-based discriminator
+board (PaDiWa), a charge-to-width FEE board with high dynamic range,
+read-out of the n-XYTER ASIC and software for data unpacking and TDC
+calibration. We conclude with an outlook on future developments.
[2] GSI Helmholtz Centre for Heavy Ion Research GmbH, Darmstadt - Germany
[3] Goethe-University, Frankfurt - Germany
[4] Jagiellonian University, Krakow – Poland
-[5] Technische Universität, Munich - Germany
+[5] Technische Universitaet, Munich - Germany
already enabling other groups to use the existing FEE boards without
major modifications. The overall reliability, flexibility and
performance of this platform was proven in three test beamtimes with
-different detectors and FEEs at CERN (CBM), in Jülich and Mainz with
+different detectors and FEEs at CERN (CBM), in Juelich and Mainz with
up to 2400 channels, of which results are shown.
Furthermore, the TRB3 can be used as an infrastructure to read-out