--- /dev/null
+\section{The prototype DAQ configuration file structure}
+In this section the MVD DAQ prototype configuration file structure is explained top to bottom.
+\subsection{Directories (draft)}
+[Which file is stored where?]
+\begin{description}
+\item[JTAG configuration XML files]
+are stored in mvdconfig/config/
+\item[System configuration XML files]
+are stored in mvdconfig/system/
+\item[Setup configuration XML files]
+are stored in mvdconfid/setup/
+\item[Sensor specification XML files]
+are stored in mvdsensorcontrol/spec
+\end{description}
+\subsection{The system configuration file}
+\label{sec:systemFile}
+The system configuration file is the top level configuration file for a MVD prototype DAQ system.
+It defines the FPGA addresses of the central control unit (ccu), the TRBnet hub (hub) and the
+gigabit ethernet link (gbe). All three entities may be located in the same FPGA and may consequently
+have the same address, which is usually the address of the central FPGA in a TRB3 set-up.
+A system may have multiple readout controllers (roc), which are usually implemented in the
+peripheral FPGAs of the TRB3.
+Apart from a description text for the system, also the daqopserver\footnote{
+[hostname]:[port] of the computer on which the TRBnet daemon is running
+} for the entire system is defined in this file.
+
+
+Example:
+% \begin{Verbatim}[frame=single,
+% framesep=2mm,
+% label=jtag\_cmd\_m26c Port,labelposition=all,commandchars=\\\{\}]
+\begin{Verbatim}[frame=single, framesep=2mm, fontsize=\small, label=mvdconfig/system/ELab.xml]
+<?xml version="1.0" encoding="utf-8" ?>
+<DaqSetup xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+ xsi:noNamespaceSchemaLocation="../schema/detectorsetup.xsd"
+ name="Elab"
+ >
+ <description>The Elab maps system setup file</description>
+
+ <daqopserver>jspc55:88</daqopserver>
+ <ccu address="8880" />
+ <hub address="8880" />
+ <roc address="d882" name="roc1" />
+ <gbe address="8880" port="50088" name="central link" />
+
+</DaqSetup>
+\end{Verbatim}
+
+
+\subsection{The setup configuration file}
+\label{sec:setupFile}
+The setup configuration file groups and defines all entities that make up a detector setup.
+The entire detector setup, which can consist of multiple sensors connected to multiple rocs,
+must be associated with one single readout system.
+In the current DAQ configuration a detector setup can have up to four controllers\footnote{rocs},
+one in each peripheral TRB3 FPGA.
+Each controller can have up to two (JTAG)chains, while each chain can contain up to two sensors.
+Overall, one TRB3 can accommodate $4\times2\times2=16$ sensors.
+Each sensor must be assigned a unique id, since this id will later be found inside the
+sensor data headers to make different data chunks attributable to their respective origin.
+(??)
+% [serial, enabled]
+The sensor also has the attribute "config", which assignes a (high level) JTAG configuration XML
+file to the sensor, from which it will acquire its JTAG register content.
+(The position information is not used yet.)
+Each chain node inside the setup file can have multiple config\footnote{
+for details about these parameters, see Bertram Neumann -
+Dokumentation: JTAG-Chain-Controller (fuer
+TRB V3) und JTAG-Monitor}
+child nodes. When the
+sensors are programmed, all text content of the config nodes will be interpreted as additional
+settings for the corresponding JTAG controller.
+Config nodes outside a chain node are settings for the JTAG controller as well, but not chain
+specific.
+
+Example:
+\begin{verbatim}
+<?xml version="1.0" encoding="utf-8" ?>
+<DetectorSetup xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+ xsi:noNamespaceSchemaLocation="../schema/detectorsetup.xsd"
+ name="Prototype"
+ >
+ <description>The main MVD prototype system setup file</description>
+
+ <readoutsystem name="ELab" />
+
+ <controller id="0" address="d882" name="board01">
+ <chain id="0" name="chain0">
+ <sensor id="0000"
+ serial="20"
+ name="sensorG03"
+ config="sensorG03.xml"
+ enabled="true">
+ <description>Sensor G03 on CB13 no 2</description>
+ <position
+ x="0"
+ y="0"
+ z="0"
+ flippedx="false"
+ flippedy="false"
+ phi="0"
+ />
+ </sensor>
+ <config>delay0</config>
+ <config>set_timing_10mhz</config>
+ <config>set_inout</config>
+ <config>maps_reset_before_off</config>
+ <config>maps_reset_after_on</config>
+ </chain>
+ <config>waitbeforestart_6us</config>
+ <config>trigger_init_sequence</config>
+ </controller>
+</DetectorSetup>
+\end{verbatim}
\ No newline at end of file
% \subsection{Overview}
+% \begin{figure}[H]
+% \centering
+% \includegraphics[width=.8\textwidth]{principlechain.pdf}
+% \caption{Simplified schema of the MVD DAQ}
+% \label{fig:principlechain}
+% \end{figure}
\begin{figure}[H]
\centering
-\includegraphics[width=.8\textwidth]{principlechain.pdf}
-\caption{Simplified schema of the MVD DAQ}
-\label{fig:principlechain}
+\includegraphics[width=.38\textwidth]{strang.pdf}
+\caption{Schema of the MVD DAQ}
+\label{fig:chain}
\end{figure}
-A strand of a MVD DAQ chain consists of the following items (see figure \ref{fig:principlechain}):
+A strand of the MVD DAQ chain consists of the following items (see figure \ref{fig:chain}):
\begin{description}
\item[The sensors:]
-MAPS of the model MIMOSA26
-\item[Front-end electronics]
+A group of sensors that are mounted in row on a mechanical support structure and are
+operated with the same set of front-end electronics is referred to as a ladder.
+In this hardware concept two\footnote{Number of sensors per ladder may change
+in future revisions of the hardware}
+MAPS of the model \hyperref[sec:The_sensors]{MIMOSA26} form one ladder.
+\item[Front-end electronics:]
Specialized electronics (PCBs and cables) that supply the sensors with power and external reference
-voltages and to some extend convert between different logic signal standards (for example
-TTL$\Leftrightarrow$LVDS).
-\item[FPGA boards]
-TRB3 boards, the latest general purpose FPGA platform used by the HADES experiment.
-\item[Computer]
+voltages.
+The sensors are bonded to a custom made FPC\footnote{Flex print cable} which connects to the
+\hyperref[sec:front-end_board]{front-end board}.
+The front-end board is connected to the
+\hyperref[sec:converter_board]{converter board} via two industry standard 50 pin FPCs.
+To some extend the front-end electronics convert between different logic signal
+standards (for example TTL$\Leftrightarrow$LVDS) and provide means to monitor the behaviour
+of the sensor.
+\item[FPGA board:]
+The \hyperref[sec:TRB3_FPGA_board]{TRB3} is
+the latest general purpose FPGA platform used by the HADES experiment.
+The FPGA is programmed with a custom logic design that containts the readout and control
+logic for the sensors.
+An adapter board (Ada-AddOn) is used to provide a connector that is compatible with the converter board.
+\item[Computer:]
Common PC running Linux and custom control, monitoring, and data acquisition software.
\end{description}
\subsection{The sensors}
+\label{sec:The_sensors}
The MIMOSA26 sensors are Monolithic Active Pixel Sensors (MAPS). In contrast to CCD sensors
MAPS can be produced in a standard CMOS process and have an amplifying transistor in each
pixel (thus "active"). This way even small amounts of charge separation can produce a measurable
The cathode is connected to analog ground.
\item
External outputs of the discriminator threshold voltage DACs. One differential voltage pair
-for each of the four DACs.
+for each of the four DACs. See \hyperref[sec:ADC]{section ADC} for details.
\item
The clamping voltage (VClp) input. The clamping voltage is a reference voltage that has to be
supplied to all pixels in the pixel matrix. It serves as a reset potential for parts of the
% \paragraph{Signal switches}
\subsubsection{Signal switches}
\label{sec:Signal_switches}
-The converter board provides semiconductor switches to enable/disable the sensor control signals
+The converter board provides solid state switches to enable/disable the sensor control signals
and to enable/bypass JTAG for each sensor.
There are four individual control signals that can be set by slow control:
\begin{description}
in order to perform the above tasks.
The firmware is written in C and compiled via a cross compiler. The resulting executable binary
file is written to the microcontroller's flash memory by using an
-SWD\footnote{Serial wire debug, a serial debug and programming interface developed by ST
-Microeletronics}
+SWD\footnote{Serial Wire Debug, a serial debug and programming interface comparable to the
+JTAG standard but using only one clock and one bidirectional data line}
programmer.
% - ?? why the microcontroller - to save lines - should I write that?
\subsection{TRB3 FPGA board}
+\label{sec:TRB3_FPGA_board}
\begin{figure}[H]
\centering
\includegraphics[width=.6\textwidth]{TRB3.png}
\end{figure}
+
+
The TRB3 board is the third iteration of the FPGA based multi purpose data acquisition
platform that was developed for the HADES experiment. It is also used in several other high energy
physics experiments due to its versatility.
+Meanwhile the TRB3 hardware platform and the associated software framework are developed and maintained
+by the TRB collaboration that includes contributors from several different countries.
It is equipped with five Lattice ECP3-150EA FPGAs, i.e. one central and four peripheral FPGAs.
The board possesses eight SFP ports that are able to accommodate optical or electrical ethernet adaptors.
-Next to each peripheral FPGA a high pin density extension connector is located, that can be equipped
+Next to each peripheral FPGA a compact 200 pin extension connector is located, that can be equipped
with specialized adaptor or interface boards. This way a wide range of data acquisition applications
-is possible. The FPGAs have an internal flash storage for its design configuration.
-When the FPGA is powered or reset, it retrieves and loads the configuration from this flash.
-The TRB3 hardware platform and the associated software framework are developed and maintained
-by the TRB collaboration.
-
-In this set-up, the TRB3 is used as a network controlled data readout board for the MIMOSA26 MAPS.
+is possible. Each FPGA has an internal flash storage for its design configuration.
+When the FPGA is powered or reset, it retrieves and loads the configuration from the flash.
+
+In the HADES detector set-up the different data acquisition and data processing FPGA boards
+communicate via TrbNet\cite{jan_diplom}, a network protocol taylored to the needs
+of a large triggered detector experiment. It is used for the configuration and monitoring of the
+components (slow control),
+the distribution of trigger signals and the transport of large amounts of acquired
+data. A TrbNet link transports triggers, data and slow control calls over a single serial
+transmission line (optical fiber or wire) by multiplexing.
+For realtime performance reasons, the trigger packets have priority over the data packets,
+which in turn have priority over the slow control packets. At each network node the packets
+are being demultiplexed into independent channels again while each channel
+has its proper receive buffer.
+In a TrbNet network, there are two different kinds of nodes: endpoints and hubs.
+Endpoints are nodes that insert and/or extract data packets to/from the network,
+while hubs route packets between other nodes (each hub is connected to one endpoint
+so it can be configured via slow control).
+
+(For a detailed description of the HADES DAQ see \cite{jan_dissertation}.)
+
+In the MVD set-up, the TRB3 is used as a network controlled data readout board for the MIMOSA26 MAPS.
The connection to the converter board is achieved by attaching an ADA-AddOn board to one
of the peripheral extension connectors. This board is a passive adaptor that provides two 80 pin
flat cable connectors, compatible with the connector on the converter board.
This way up to two\footnote{?? not implemented yet, only one converter board can be operated
due to the roc code ??} converter boards can be operated with one peripheral FPGA.
-\subsection{FPGA design entities (draft!)}
+\begin{figure}[H]
+\centering
+\includegraphics[width=.6\textwidth]{peripheral_FPGA.pdf}
+\caption{Simplified schema of the entities inside the peripheral FPGA design}
+\label{fig:peripheral_FPGA}
+\end{figure}
+
+% \subsection{FPGA design entities}
The FPGA design is internally divided into individual modules, the so called entities.
An entitity can be pictured as a (virtual) black box with a multitude of binary data inputs
and outputs. Entities can contain virtually every kind of digital circuitry, such as
combinatorial logic, memory, arithmetic processing elements, etc.
+
The design for the TRB3 peripheral FPGAs consists of
-three main entities: The readout controller (ROC), the JTAG controller and the converter board
-controller (CbController). Each of the three has its distinct functionality.
+three main entities: The \hyperref[sec:ReadoutController]{readout controller} (ROC)
+, the \hyperref[sec:JTAG_controller]{JTAG controller} and the
+\hyperref[sec:CbController]{converter board controller} (CbController)
+(see figure \ref{fig:peripheral_FPGA}).
+Apart from these front-end specific functional groups the design incorporates a TrbNet endpoint
+that connects the above entities to the DAQ network. The media interface entity serves as an
+adaptor between the abstract/generic endpoint and the physical data transmission medium,
+which can be an optical transceiver, or in this case, a differential line between two FPGAs.
+
+The central FPGA houses a TrbNet hub as well as a gigabit ethernet
+link entity (GbE) and the so called central control unit (CCU).
+The gigabit ethernet entity allows to use an attached SFP module to establish a gigabit ethernet
+link to the computer that runs the data acquisition, configuration and monitoring software.
+This way all endpoints connected to the central hub (i.e. all peripheral FPGAs) can be accessed
+by the user or automated DAQ software.
+
+The central control unit is an entity that generates trigger signals for the readout controllers.
+The CBM MVD is a detector that is designed to be free running, i.e. triggerless, while the
+hardware concepts are adapted from the HADES system, which is a triggered detector.
+In the MVD setup the central control unit resumes the task of the HADES
+CTS\footnote{central triggering system \cite{jan_dissertation}}
+but in a much simpler fashion. It sends trigger signals with a fixed frequency that corresponds
+to twice the sensor frame rate. This way such a readout request is guaranteed to occur within one
+frame and there is at least half a frame period to transmit the data before a new frame is acquired.
+
+
\subsubsection{Readout controller}
\label{sec:ReadoutController}
The readout controller\footnote{Implemented by Borislav Milanovic during his PhD. studies}
\subsubsection{JTAG controller}
\label{sec:JTAG_controller}
While the ROC is concerned with the data coming from the sensor, the JTAG
-controller\footnote{Developed by Bertram Neuman during his master's thesis} handles the
+controller\footnote{Developed by Bertram Neuman during his master's thesis\cite{bertram_master}}
+handles the
communication to the sensor. The MIMOSA26 sensor possesses a JTAG interface (a synchronous serial
data interface) that provides access to the settings registers of the chip.
Multiple sensors can have their JTAG interfaces connected in series (comparable to shift registers)
Furthermore the JTAG controller controls the START and the RESET signal of the sensor, so the sensor
can be initialized and reset via slow control commands.
+In the current set-up two sensors (= one ladder $\stackrel{\wedge}{=}$ one converter board)
+are operated as a JTAG chain that is controlled by one JTAG controller.
+
See section \ref{sec:JTAG_programming} for more details about JTAG registers and their manipulation.
\subsubsection{Converter board controller}
the entity allows for the switching of power and signal lines to and from the sensor via slow control.
Furthermore it is involved in the acquisition of sensor status information,
such as sensor temperature and power consumption.
-The ADC data acquisition and the converter board components are controlled by the on board
+The ADC data acquisition and the converter board components are controlled by the on-board
\hyperref[sec:Microcontroller]{microcontroller}.
To communicate with the microcontroller the entity incorporates an SPI slave interface and a
bidirectional UART.
The CbController entity forwards slow control commands to the converter board via the UART
-and receives status information in turn.
-The SPI slave constantly receives a joint data stream of all voltage and current measurements performed
-by the ADCs on the converter board.
-The readings get stored in dedicated registers and are refreshed continuously. The register contents
-can then be read out via slow control requests.
-\subsubsection{hub/ccu?(draft!)}
-[??placeholder]
-
+and receives status information in return.
+The SPI slave constantly receives a joint data stream from the microcontroller.
+It contains all voltage and current measurements performed by the ADCs on the converter board.
+The readings are stored in dedicated registers in the FPGA and are refreshed continuously.
+These registers can then be read out via slow control requests.
\usepackage[urlcolor=blue,linkcolor=blue,colorlinks=true]{hyperref}
\usepackage{siunitx}
\geometry{verbose,tmargin=3cm,bmargin=3cm,lmargin=3cm,rmargin=3cm}
-
-
+% \usepackage{framed}
+\usepackage{fancyvrb}
\begin{document}
% \bibliographystyle{plain}
\include{daqsetup}
-
-\section{The prototype DAQ configuration file structure}
-In this section the MVD DAQ prototype configuration file structure is explained top to bottom.
-\subsection{Directories (draft)}
-[Which file is stored where?]
-\begin{description}
-\item[JTAG configuration XML files]
-are stored in mvdconfig/config/
-\item[System configuration XML files]
-are stored in mvdconfig/system/
-\item[Setup configuration XML files]
-are stored in mvdconfid/setup/
-\item[Sensor specification XML files]
-are stored in mvdsensorcontrol/spec
-\end{description}
-\subsection{The system configuration file}
-\label{sec:systemFile}
-The system configuration file is the top level configuration file for a MVD prototype DAQ system.
-It defines the FPGA addresses of the central control unit (ccu), the TRBnet hub (hub) and the
-gigabit ethernet link (gbe). All three entities may be located in the same FPGA and may consequently
-have the same address, which is usually the address of the central FPGA in a TRB3 set-up.
-A system may have multiple readout controllers (roc), which are usually implemented in the
-peripheral FPGAs of the TRB3.
-Apart from a description text for the system, also the daqopserver\footnote{
-[hostname]:[port] of the computer on which the TRBnet daemon is running
-} for the entire system is defined in this file.
-
-
-Example:
-\begin{verbatim}
-<?xml version="1.0" encoding="utf-8" ?>
-<DaqSetup xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
- xsi:noNamespaceSchemaLocation="../schema/detectorsetup.xsd"
- name="Elab"
- >
- <description>The Elab maps system setup file</description>
-
- <daqopserver>jspc55:88</daqopserver>
- <ccu address="8880" />
- <hub address="8880" />
- <roc address="d882" name="roc1" />
- <gbe address="8880" port="50088" name="central link" />
-
-</DaqSetup>
-\end{verbatim}
-
-
-\subsection{The setup configuration file}
-\label{sec:setupFile}
-The setup configuration file groups and defines all entities that make up a detector setup.
-The entire detector setup, which can consist of multiple sensors connected to multiple rocs,
-must be associated with one single readout system.
-In the current DAQ configuration a detector setup can have up to four controllers\footnote{rocs},
-one in each peripheral TRB3 FPGA.
-Each controller can have up to two (JTAG)chains, while each chain can contain up to two sensors.
-Overall, one TRB3 can accommodate $4\times2\times2=16$ sensors.
-Each sensor must be assigned a unique id, since this id will later be found inside the
-sensor data headers to make different data chunks attributable to their respective origin.
-(??)
-% [serial, enabled]
-The sensor also has the attribute "config", which assignes a (high level) JTAG configuration XML
-file to the sensor, from which it will acquire its JTAG register content.
-(The position information is not used yet.)
-Each chain node inside the setup file can have multiple config\footnote{
-for details about these parameters, see Bertram Neumann -
-Dokumentation: JTAG-Chain-Controller (fuer
-TRB V3) und JTAG-Monitor}
-child nodes. When the
-sensors are programmed, all text content of the config nodes will be interpreted as additional
-settings for the corresponding JTAG controller.
-Config nodes outside a chain node are settings for the JTAG controller as well, but not chain
-specific.
-
-Example:
-\begin{verbatim}
-<?xml version="1.0" encoding="utf-8" ?>
-<DetectorSetup xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
- xsi:noNamespaceSchemaLocation="../schema/detectorsetup.xsd"
- name="Prototype"
- >
- <description>The main MVD prototype system setup file</description>
-
- <readoutsystem name="ELab" />
-
- <controller id="0" address="d882" name="board01">
- <chain id="0" name="chain0">
- <sensor id="0000"
- serial="20"
- name="sensorG03"
- config="sensorG03.xml"
- enabled="true">
- <description>Sensor G03 on CB13 no 2</description>
- <position
- x="0"
- y="0"
- z="0"
- flippedx="false"
- flippedy="false"
- phi="0"
- />
- </sensor>
- <config>delay0</config>
- <config>set_timing_10mhz</config>
- <config>set_inout</config>
- <config>maps_reset_before_off</config>
- <config>maps_reset_after_on</config>
- </chain>
- <config>waitbeforestart_6us</config>
- <config>trigger_init_sequence</config>
- </controller>
-</DetectorSetup>
-\end{verbatim}
-
+\include{config_structure}
\include{jtag}
\include{daqscripts}
\include{bib}
jspc29 / mvd_docu.git / commitdiff