Boris
CS: ----------------------------------------------------------------------
use work.trb_net_components.all;
entity trb_net16_med_16_IC is
+ generic(
+ DATA_CLK_OUT_PHASE : std_logic := '1'
+ );
port(
CLK : in std_logic;
CLK_EN : in std_logic;
THE_CLK_OUT : ddr_off
port map(
Clk => CLK,
- Data => "10",
+ Data(0) => DATA_CLK_OUT_PHASE,
+ Data(1) => not DATA_CLK_OUT_PHASE,
Q(0) => DATA_CLK_OUT
);