*** empty log message ***

diff --git a/design2/control_line_handle.vhd b/design2/control_line_handle.vhd
index 8938e9cf6cf3220d9193c1b0645b3c7ff9113428..ff5032c1e9cfab3877b785c99152ff20bda5e0a1 100644 (file)
--- a/design2/control_line_handle.vhd
+++ b/design2/control_line_handle.vhd
@@ -60,7 +60,8 @@ end entity;
 architecture behavioral of control_line_handle is
 
 --signal declarations
-  type state_type is (idle, trigger_begrun, send_token, trigger_calibration);
+  type state_type is (idle, trigger_begrun, send_token,
+                      trigger_calibration, wait_for_data_request);
 
   signal current_state           : state_type;
   signal next_state              : state_type;
@@ -152,7 +153,7 @@ begin
       end if;
     end process;
 
-  real_gde_i <= tmp_gde_i or A_GDE_ST_i;
+  real_gde_i <= tmp_gde_i or A_GDE_ST_i or A_GDE_TB_i;
 
   proc_real_gde : process (CLK)
     begin
@@ -161,14 +162,12 @@ begin
           tmp_gde_i <= '0';
         elsif finished_load_calib_i = '1' then
           tmp_gde_i <= '1';
+          else
+          tmp_gde_i <= tmp_gde_i; 
         end if;
       end if;
     end process;
 
--------------------------------------------------------------------------------
--- send_token_to_mb
--------------------------------------------------------------------------------
-
   the_send_token : send_token_to_mb
     port map (
       CLK                      => CLK,
@@ -194,8 +193,6 @@ begin
 -- send_token_to_mb
 -------------------------------------------------------------------------------
 
-
-
   proc_fsm_sync : process (CLK)
     begin
       --process
@@ -243,12 +240,13 @@ begin
 
       when trigger_calibration =>
         if finished_load_calib_i = '1' then
-          next_state             <= idle;
+          next_state     <= send_token;
         end if;
-
+        
       when send_token =>
+         next_line_select       <= '1';
         if token_back_i = '1' or no_token_back_i = '1' then
-          next_state             <= idle;
+          next_state            <= idle;
         end if;
 
       when others =>
@@ -257,7 +255,6 @@ begin
     end case;
   end process;
 
-
 -------------------------------------------------------------------------------
 -- I/O
 -------------------------------------------------------------------------------
@@ -296,8 +293,6 @@ begin
   DEBUG_REGISTER(11)             <= start_debug_readout_i;
   DEBUG_REGISTER(31 downto 12)   <= (others => '0');
 
-
-
 end behavioral;