signal write_ctrl_register : std_logic;
signal reset_mdc_addon_daq_bus_0, pulse_reset_internal_logic : std_logic;
-
+
begin
---------------------------------------------------------------------
-- PLL: 100 MHz
THE_RESET_COUNTER_PROC: process(CLK)
begin
if rising_edge(CLK) then
- if pll_locked = '0' then
+ if MED_STAT_OP(13) = '1' or pll_locked = '0' then
reset_counter <= x"000F00";
reset_internal <= '1';
reset_startup <= '1';
BUS_WRITE_ENABLE_OUT(2) => flash_mem_write,
BUS_DATA_OUT(2*32+31 downto 2*32) => flash_mem_data,
BUS_ADDR_OUT(2*16+8 downto 2*16) => flash_mem_addr,
- BUS_TIMEOUT_OUT(2) => open,
+ BUS_TIMEOUT_OUT(2) => open,
BUS_DATA_IN(2*32+31 downto 2*32) => flash_mem_data_out,
BUS_DATAREADY_IN(2) => very_last_reg_REGIO_READ,
BUS_WRITE_ACK_IN(2) => reg_REGIO_WRITE,
BUS_NO_MORE_DATA_IN(2) => '0',
- BUS_UNKNOWN_ADDR_IN(2) => '0',
+ BUS_UNKNOWN_ADDR_IN(2) => '0',
--Debugging
STAT_DEBUG => open
);
if (flash_mem_addr(3 downto 0) = x"0") then
write_cmd_register_in <= flash_mem_write;
flash_mem_data_out <= cmd_register_in;
-
+
elsif (flash_mem_addr(3 downto 0) = x"1") then
write_ctrl_register <= flash_mem_write;
flash_mem_data_out <= ctrl_register;
ctrl_register <= ctrl_register;
end if;
end if;
- end process;
+ end process;
---------------------------------------------------------------------
-- ADC
---------------------------------------------------------------------
-- 0xc0 0x1000 -> select compact mode data
-- 0xc0 0x2000 -> select test data
-- 0xc0 0xABCD2000 -> x"ABCD" test data number
-
+
PROC_GEN_TIMING : process(CLK_100)
begin
if rising_edge(CLK_100) then
PULSE_OUT => pulse_reset_internal_logic);
reset_mdc_addon_daq_bus_0 <= reset_internal or pulse_reset_internal_logic;
-
+
PULSE_BEGRUN_TRIGGER : edge_to_pulse
port map (
CLOCK => CLK_100,