package config is
-
------------------------------------------------------------------------------
--Begin of design configuration
------------------------------------------------------------------------------
+--We use an ECP3
+ constant FPGA_TYPE : integer := 3; --3: ECP3, 5: ECP5
+
+--Gbe included?
+ constant INCLUDE_GBE : integer := c_NO;
+
--Runs with 120 MHz instead of 100 MHz
constant USE_120_MHZ : integer := c_NO;
constant USE_200MHZOSCILLATOR : integer := c_YES;
constant USE_EXTERNAL_CLOCK : integer := c_YES; --'no' not implemented.
constant CLOCK_FAST_SELECT : integer := c_YES; --fast clock select (135us) or slow (280ms)?
- constant FPGA_TYPE : integer := 3; --3: ECP3, 5: ECP5
-
--Use sync mode, RX clock for all parts of the FPGA
constant USE_RXCLOCK : integer := c_NO;
constant INIT_ADDRESS : std_logic_vector := x"F3CE";
constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"61"; --61 with GbE, 60 without
-
- constant INCLUDE_UART : integer := c_YES;
- constant INCLUDE_SPI : integer := c_YES;
+ constant INCLUDE_UART : integer := c_NO; -- was c_YES
+ constant INCLUDE_SPI : integer := c_NO; -- was c_YES
constant INCLUDE_LCD : integer := c_NO;
- constant INCLUDE_DEBUG_INTERFACE: integer := c_YES;
+ constant INCLUDE_DEBUG_INTERFACE: integer := c_NO; -- was c_YES
--input monitor and trigger generation logic
- constant INCLUDE_TRIGGER_LOGIC : integer := c_YES;
- constant INCLUDE_STATISTICS : integer := c_YES;
+ constant INCLUDE_TRIGGER_LOGIC : integer := c_NO; -- was c_YES
+ constant INCLUDE_STATISTICS : integer := c_NO; -- was c_YES
constant TRIG_GEN_INPUT_NUM : integer := 22+32;
constant TRIG_GEN_OUTPUT_NUM : integer := 4;
constant MONITOR_INPUT_NUM : integer := 22+32;
-
- constant INCLUDE_GBE : integer := c_YES;
-
------------------------------------------------------------------------------
--End of design configuration
TOPNAME => "trb3sc_master",
-lm_license_file_for_synplify => "27000\@lxcad01.gsi.de",
+lm_license_file_for_synplify => "27000\@lxcad04.gsi.de",
lm_license_file_for_par => "1702\@hadeb05.gsi.de",
-lattice_path => '/opt/lattice/diamond/3.6_x64/',
-synplify_path => '/opt/synplicity/J-2014.09-SP2',
-#synplify_command => "/opt/lattice/diamond/3.4_x64/bin/lin64/synpwrap -fg -options",
-synplify_command => "/opt/synplicity/K-2015.09/bin/synplify_premier_dp",
+lattice_path => '/opt/lattice/diamond/3.12',
+synplify_path => '/opt/synplicity/R-2020.09-SP1',
+synplify_command => "/opt/synplicity/R-2020.09-SP1/bin/synplify_premier",
-nodelist_file => 'nodelist_gsi_template.txt',
+nodelist_file => 'nodelist.txt',
+pinout_file => 'trb3sc_master',
+par_options => '../par.p2t',
-firefox_open => 0,
-
-include_GBE => 1,
+include_TDC => 0,
+include_GBE => 0,
-#Report settings
firefox_open => 0,
-twr_number_of_errors => 20,
\ No newline at end of file
+twr_number_of_errors => 20,
+no_ltxt2ptxt => 0, #if there is no serdes being used
--- /dev/null
+// nodes file for parallel place&route
+
+[hades66]
+system = linux
+corenum = 24
+ENV = /home/compile/bin/diamond_env
+workdir = /home/compile/vhdl/dirich/dirich/workdir
+
-w
--i 15
-l 5
--y
-s 12
--t 32
+-t 32 # seed setting here!
-c 1
-e 2
-#-g guidefile.ncd
-#-m nodelist.txt
-# -w
-# -i 6
-# -l 5
-# -n 1
-# -t 1
-# -s 1
-# -c 0
-# -e 0
-#
-#-exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1
+-i 15
+-y
-exp parUseNBR=1:parCDP=auto:parCDR=1:parPathBased=OFF:parHold=ON:parHoldLimit=10000
+#General PAR Command Line Options
+# -w With this option, any files generated will overwrite existing files
+# (e.g., any .par, .pad files).
+# -y Adds the Delay Summary Report in the .par file and creates the delay
+# file (in .dly format) at the end of the par run.
+#
+#PAR Placement Command Line Options
+# -l Specifies the effort level of the design from 1 (simplest designs)
+# to 5 (most complex designs).
+# -m Multi-tasking option. Controlled by the compile.pl script.
+# -n Sets the number of iterations performed at the effort level
+# specified by the -l option. Controlled by the compile.pl script.
+# -s Save the number of best results for this run.
+# -t Start placement at the specified cost table. Default is 1.
+#
+#PAR Routing Command Line Options
+# -c Run number of cost-based cleanup passes of the router.
+# -e Run number of delay-based cleanup passes of the router on
+# completely-routed designs only.
+# -i Run a maximum number of passes, stopping earlier only if the routing
+# goes to 100 percent completion and all constraints are met.
+#
+#PAR Explorer Command Line Options
+# parCDP Enable the congestion-driven placement (CDP) algorithm. CDP is
+# compatible with all Lattice FPGA device families; however, most
+# benefit has been demonstrated with benchmarks targeted to ECP5,
+# LatticeECP2/M, LatticeECP3, and LatticeXP2 device families.
+# parCDR Enable the congestion-driven router (CDR) algorithm.
+# Congestion-driven options like parCDR and parCDP can improve
+# performance given a design with multiple congestion “hotspots.” The
+# Layer > Congestion option of the Design Planner Floorplan View can
+# help visualize routing congestion. Large congested areas may prevent
+# the options from finding a successful solution.
+# CDR is compatible with all Lattice FPGA device families however most
+# benefit has been demonstrated with benchmarks targeted to ECP5,
+# LatticeECP2/M,LatticeECP3, and LatticeXP2 device families.
+# paruseNBR NBR Router or Negotiation-based routing option. Supports all
+# FPGA device families except LatticeXP and MachXO.
+# When turned on, an alternate routing engine from the traditional
+# Rip-up-based routing selection (RBR) is used. This involves an
+# iterative routing algorithm that routes connections to achieve
+# minimum delay cost. It does so by computing the demand on each
+# routing resource and applying cost values per node. It will
+# complete when an optimal solution is arrived at or the number of
+# iterations is reached.
+# parPathBased Path-based placement option. Path-based timing driven
+# placement will yield better performance and more
+# predictable results in many cases.
+# parHold Additional hold time correction option. This option
+# forces the router to automatically insert extra wires to compensate for the
+# hold time violation.
+# parHoldLimit This option allows you to set a limit on the number of
+# hold time violations to be processed by the auto hold time correction option
+# parHold.
+# parPlcInLimit Cannot find in the online help
+# parPlcInNeighborSize Cannot find in the online help
+
CLK_SUPPL_PCLK : in std_logic; --125 MHz for GbE
CLK_CORE_PCLK : in std_logic; --Main Oscillator
CLK_EXT_PLL_LEFT : in std_logic; --External Clock
-
+ -- Trigger
TRIG_LEFT : in std_logic;
--Additional IO
HDR_IO : inout std_logic_vector(10 downto 1);
-- SPARE_IN : in std_logic_vector( 1 downto 0);
BACK_LVDS : inout std_logic_vector( 1 downto 0);
BACK_3V3 : inout std_logic_vector( 3 downto 0);
-
--KEL connector
INP : in std_logic_vector(95 downto 64);
DAC_OUT_SDO : out std_logic_vector(6 downto 5);
DAC_OUT_SCK : out std_logic_vector(6 downto 5);
DAC_OUT_CS : out std_logic_vector(6 downto 5);
DAC_IN_SDI : in std_logic_vector(6 downto 5);
-
-
--Lines to slaves
BACK_MASTER_READY : out std_logic_vector(8 downto 0);
BACK_SLAVE_READY : in std_logic_vector(8 downto 0);
BACK_TRIG1 : in std_logic_vector(8 downto 0);
BACK_TRIG2 : in std_logic_vector(8 downto 0);
-
--LED
LED_GREEN : out std_logic;
LED_YELLOW : out std_logic;
LED_WHITE : out std_logic_vector( 1 downto 0);
LED_SFP_GREEN : out std_logic_vector( 1 downto 0);
LED_SFP_RED : out std_logic_vector( 1 downto 0);
-
--SFP
SFP_LOS : in std_logic_vector( 1 downto 0);
SFP_MOD0 : in std_logic_vector( 1 downto 0);
SFP_MOD1 : inout std_logic_vector( 1 downto 0) := (others => 'Z');
SFP_MOD2 : inout std_logic_vector( 1 downto 0) := (others => 'Z');
SFP_TX_DIS : out std_logic_vector( 1 downto 0) := (others => '0');
-
--Serdes switch
PCSSW_ENSMB : out std_logic;
PCSSW_EQ : out std_logic_vector( 3 downto 0);
PCSSW_PE : out std_logic_vector( 3 downto 0);
PCSSW : out std_logic_vector( 7 downto 0);
-
--ADC
ADC_CLK : out std_logic;
ADC_CS : out std_logic;
ADC_DIN : out std_logic;
ADC_DOUT : in std_logic;
-
--Flash, 1-wire, Reload
FLASH_CLK : out std_logic;
FLASH_CS : out std_logic;
PROGRAMN : out std_logic;
ENPIRION_CLOCK : out std_logic;
TEMPSENS : inout std_logic;
-
--Test Connectors
TEST_LINE : out std_logic_vector(15 downto 0)
- );
-
+ );
attribute syn_useioff : boolean;
attribute syn_useioff of FLASH_CLK : signal is true;
--Backplane A2,A3,A0,A1 Slave 3,4,1,2, A0: TrbNet from backplane
--AddOn C2,C3,C0,C1,B0,B1,B2,D1(B3) Slave --,--,5,9,8,7,6,--
--SFP D0,B3(D1) D0: GbE, B3: TrbNet
-
-
+
end entity;
architecture trb3sc_arch of trb3sc_master is
LED_RED_OUT => LED_RJ_RED,
LED_GREEN_OUT => LED_RJ_GREEN,
DEBUG_OUT => debug_clock_reset
- );
-reset_from_net_i <= med2int(9).stat_op(13) or external_reset_delayed(4) ;
-send_reset_i <= med2int(9).stat_op(15); --int2med(0).ctrl_op(15) or;
+ );
+
+ reset_from_net_i <= med2int(9).stat_op(13) or external_reset_delayed(4) ;
+ send_reset_i <= med2int(9).stat_op(15); --int2med(0).ctrl_op(15) or;
---------------------------------------------------------------------------
-- TrbNet Uplink
THE_MEDIA_INT_MIXED : entity work.med_ecp3_sfp_sync_4_slave3 --PCSB
generic map(
IS_SYNC_SLAVE => (c_NO, c_NO, c_NO, c_YES),
- IS_USED => (c_YES, c_YES, c_YES ,c_YES)
- )
+ IS_USED => (c_YES, c_YES, c_YES, c_YES)
+ )
port map(
- CLK_REF_FULL => clk_full_osc, --med2int(INTERFACE_NUM-1).clk_full,
+ CLK_REF_FULL => clk_full_osc,
CLK_INTERNAL_FULL => clk_full_osc,
SYSCLK => clk_sys,
RESET => reset_i,
MEDIA_INT2MED(1) => int2med(6),
MEDIA_INT2MED(2) => int2med(5),
MEDIA_INT2MED(3) => int2med(9),
-
--Sync operation
RX_DLM => open,
RX_DLM_WORD => open,
TX_DLM => open,
TX_DLM_WORD => open,
-
--SFP Connection
SD_PRSNT_N_IN(0) => backplane_rx_present(7),
SD_LOS_IN(0) => backplane_rx_present(7),
generic map(
SERDES_NUM => 0,
IS_SYNC_SLAVE => c_NO
- )
+ )
port map(
- CLK_REF_FULL => clk_full_osc, --med2int(0).clk_full,
+ CLK_REF_FULL => clk_full_osc,
CLK_INTERNAL_FULL => clk_full_osc,
- SYSCLK => clk_sys,
- RESET => reset_i,
- CLEAR => clear_i,
+ SYSCLK => clk_sys,
+ RESET => reset_i,
+ CLEAR => clear_i,
--Internal Connection
- MEDIA_MED2INT => med2int(10), --10 or 8
- MEDIA_INT2MED => int2med(10),
-
+ MEDIA_MED2INT => med2int(10), --10 or 8
+ MEDIA_INT2MED => int2med(10),
--Sync operation
- RX_DLM => open,
- RX_DLM_WORD => open,
- TX_DLM => open,
- TX_DLM_WORD => open,
-
+ RX_DLM => open,
+ RX_DLM_WORD => open,
+ TX_DLM => open,
+ TX_DLM_WORD => open,
--SFP Connection
- SD_PRSNT_N_IN => SFP_MOD0(0),
- SD_LOS_IN => SFP_LOS(0),
- SD_TXDIS_OUT => SFP_TX_DIS(0),
+ SD_PRSNT_N_IN => SFP_MOD0(0),
+ SD_LOS_IN => SFP_LOS(0),
+ SD_TXDIS_OUT => SFP_TX_DIS(0),
--Control Interface
- BUS_RX => bussci4_rx,
- BUS_TX => bussci4_tx,
+ BUS_RX => bussci4_rx,
+ BUS_TX => bussci4_tx,
-- Status and control port
- STAT_DEBUG => open, --med_stat_debug(63 downto 0),
- CTRL_DEBUG => open
- );
+ STAT_DEBUG => open,
+ CTRL_DEBUG => open
+ );
end generate;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
THE_MEDIA_4_DOWN : entity work.med_ecp3_sfp_sync_4 --PCSA
generic map(
- IS_SYNC_SLAVE => (c_NO, c_NO, c_NO, c_NO),
- IS_USED => (c_YES,c_YES ,c_YES ,c_YES)
- )
+ IS_SYNC_SLAVE => (c_NO, c_NO, c_NO, c_NO),
+ IS_USED => (c_YES, c_YES, c_YES, c_YES)
+ )
port map(
- CLK_REF_FULL => clk_full_osc, --med2int(INTERFACE_NUM-1).clk_full,
- CLK_INTERNAL_FULL => clk_full_osc,
- SYSCLK => clk_sys,
- RESET => reset_i,
- CLEAR => clear_i,
-
+ CLK_REF_FULL => clk_full_osc,
+ CLK_INTERNAL_FULL => clk_full_osc,
+ SYSCLK => clk_sys,
+ RESET => reset_i,
+ CLEAR => clear_i,
--Internal Connection
MEDIA_MED2INT(0 to 3) => med2int(0 to 3),
MEDIA_INT2MED(0 to 3) => int2med(0 to 3),
-
--Sync operation
- RX_DLM => open,
- RX_DLM_WORD => open,
- TX_DLM => open,
- TX_DLM_WORD => open,
-
+ RX_DLM => open,
+ RX_DLM_WORD => open,
+ TX_DLM => open,
+ TX_DLM_WORD => open,
--SFP Connection
- SD_PRSNT_N_IN => backplane_rx_present(3 downto 0),
- SD_LOS_IN => backplane_rx_present(3 downto 0),
- SD_TXDIS_OUT => backplane_tx_present(3 downto 0),
-
+ SD_PRSNT_N_IN => backplane_rx_present(3 downto 0),
+ SD_LOS_IN => backplane_rx_present(3 downto 0),
+ SD_TXDIS_OUT => backplane_tx_present(3 downto 0),
--Control Interface
- BUS_RX => bussci1_rx,
- BUS_TX => bussci1_tx,
-
+ BUS_RX => bussci1_rx,
+ BUS_TX => bussci1_tx,
-- Status and control port
- STAT_DEBUG => med_stat_debug(63 downto 0),
- CTRL_DEBUG => open
- );
+ STAT_DEBUG => med_stat_debug(63 downto 0),
+ CTRL_DEBUG => open
+ );
THE_MEDIA_4_DOWN2 : entity work.med_ecp3_sfp_sync_4 --PCSC
generic map(
- IS_SYNC_SLAVE => (c_NO, c_NO, c_NO, c_NO),
- IS_USED => (c_YES,c_YES ,c_NO ,c_NO)
- )
+ IS_SYNC_SLAVE => (c_NO, c_NO, c_NO, c_NO),
+ IS_USED => (c_YES, c_YES, c_NO, c_NO)
+ )
port map(
- CLK_REF_FULL => clk_full_osc, --med2int(INTERFACE_NUM-1).clk_full,
+ CLK_REF_FULL => clk_full_osc,
CLK_INTERNAL_FULL => clk_full_osc,
SYSCLK => clk_sys,
RESET => reset_i,
CLEAR => clear_i,
-
--Internal Connection
- MEDIA_MED2INT(0) => med2int(4),
- MEDIA_MED2INT(1) => med2int(8),
- MEDIA_INT2MED(0) => int2med(4),
- MEDIA_INT2MED(1) => int2med(8),
-
+ MEDIA_MED2INT(0) => med2int(4),
+ MEDIA_MED2INT(1) => med2int(8),
+ MEDIA_INT2MED(0) => int2med(4),
+ MEDIA_INT2MED(1) => int2med(8),
--Sync operation
RX_DLM => open,
RX_DLM_WORD => open,
TX_DLM => open,
TX_DLM_WORD => open,
-
--SFP Connection
SD_PRSNT_N_IN(0) => backplane_rx_present(4),
SD_PRSNT_N_IN(1) => backplane_rx_present(8),
SD_PRSNT_N_IN(2) => '1',
SD_PRSNT_N_IN(3) => '1',
-
- SD_LOS_IN(0) => backplane_rx_present(4),
- SD_LOS_IN(1) => backplane_rx_present(8),
- SD_LOS_IN(2) => '1',
- SD_LOS_IN(3) => '1',
-
- SD_TXDIS_OUT(0) => backplane_tx_present(4),
- SD_TXDIS_OUT(1) => backplane_tx_present(8),
- SD_TXDIS_OUT(2) => open,
- SD_TXDIS_OUT(3) => open,
-
+ SD_LOS_IN(0) => backplane_rx_present(4),
+ SD_LOS_IN(1) => backplane_rx_present(8),
+ SD_LOS_IN(2) => '1',
+ SD_LOS_IN(3) => '1',
+ SD_TXDIS_OUT(0) => backplane_tx_present(4),
+ SD_TXDIS_OUT(1) => backplane_tx_present(8),
+ SD_TXDIS_OUT(2) => open,
+ SD_TXDIS_OUT(3) => open,
--Control Interface
BUS_RX => bussci3_rx,
BUS_TX => bussci3_tx,
-
-- Status and control port
- STAT_DEBUG => open, --med_stat_debug(63 downto 0),
+ STAT_DEBUG => open,
CTRL_DEBUG => open
- );
+ );
-gen_ready_signals : for i in 0 to 8 generate
- backplane_rx_present(i) <= BACK_SLAVE_READY(i);
- BACK_MASTER_READY(i) <= backplane_tx_present(i) or SFP_LOS(1);
+ gen_ready_signals : for i in 0 to 8 generate
+ backplane_rx_present(i) <= BACK_SLAVE_READY(i);
+ BACK_MASTER_READY(i) <= backplane_tx_present(i) or SFP_LOS(1);
- monitor_inputs_i(i*2+1 downto i*2) <= BACK_TRIG2(i) & BACK_TRIG1(i);
- trigger_inputs_i(i*2+1 downto i*2) <= BACK_TRIG2(i) & BACK_TRIG1(i);
-end generate;
+ monitor_inputs_i(i*2+1 downto i*2) <= BACK_TRIG2(i) & BACK_TRIG1(i);
+ trigger_inputs_i(i*2+1 downto i*2) <= BACK_TRIG2(i) & BACK_TRIG1(i);
+ end generate;
---------------------------------------------------------------------------
-- GbE
LINK_HAS_DHCP => "0001",
LINK_HAS_ARP => "0001",
LINK_HAS_PING => "0001"
- )
-
+ )
port map(
CLK_SYS_IN => clk_sys,
CLK_125_IN => CLK_SUPPL_PCLK,
RESET => reset_i,
GSR_N => GSR_N,
-
+ --
TRIGGER_IN => TRIG_LEFT,
-
+ --
SD_PRSNT_N_IN(0) => SFP_MOD0(0),
SD_LOS_IN(0) => SFP_LOS(0),
SD_TXDIS_OUT(0) => SFP_TX_DIS(0),
-
+ --
CTS_NUMBER_IN => cts_number,
CTS_CODE_IN => cts_code,
CTS_INFORMATION_IN => cts_information,
CTS_READ_IN => cts_read,
CTS_LENGTH_OUT => cts_length,
CTS_ERROR_PATTERN_OUT => cts_status_bits,
-
+ --
FEE_DATA_IN => fee_data,
FEE_DATAREADY_IN => fee_dataready,
FEE_READ_OUT => fee_read,
FEE_STATUS_BITS_IN => fee_status_bits,
FEE_BUSY_IN => fee_busy,
-
+ --
MC_UNIQUE_ID_IN => mc_unique_id,
MY_TRBNET_ADDRESS_IN => my_address,
ISSUE_REBOOT_OUT => reboot_from_gbe,
-
+ --
GSC_CLK_IN => clk_sys,
GSC_INIT_DATAREADY_OUT => gsc_init_dataready,
GSC_INIT_DATA_OUT => gsc_init_data,
GSC_REPLY_PACKET_NUM_IN => gsc_reply_packet_num,
GSC_REPLY_READ_OUT => gsc_reply_read,
GSC_BUSY_IN => gsc_busy,
-
- BUS_IP_RX => busgbeip_rx,
- BUS_IP_TX => busgbeip_tx,
- BUS_REG_RX => busgbereg_rx,
- BUS_REG_TX => busgbereg_tx,
-
+ --
+ BUS_IP_RX => busgbeip_rx,
+ BUS_IP_TX => busgbeip_tx,
+ BUS_REG_RX => busgbereg_rx,
+ BUS_REG_TX => busgbereg_tx,
+ --
MAKE_RESET_OUT => reset_via_gbe,
-
+ --
DEBUG_OUT => open
- );
-
+ );
---------------------------------------------------------------------------
-- Hub with GbE
---------------------------------------------------------------------------
-
THE_HUB: entity work.trb_net16_hub_streaming_port_sctrl_record
generic map(
- HUB_USED_CHANNELS => (1,1,0,1),
- INIT_ADDRESS => INIT_ADDRESS,
- MII_NUMBER => INTERFACE_NUM,
- MII_IS_UPLINK => MII_IS_UPLINK,
- MII_IS_DOWNLINK => MII_IS_DOWNLINK,
- MII_IS_UPLINK_ONLY => MII_IS_UPLINK_ONLY,
- USE_ONEWIRE => c_YES,
- HARDWARE_VERSION => HARDWARE_INFO,
- INCLUDED_FEATURES => INCLUDED_FEATURES,
- INIT_ENDPOINT_ID => x"0001",
- CLOCK_FREQUENCY => CLOCK_FREQUENCY,
+ HUB_USED_CHANNELS => (1,1,0,1),
+ INIT_ADDRESS => INIT_ADDRESS,
+ MII_NUMBER => INTERFACE_NUM,
+ MII_IS_UPLINK => MII_IS_UPLINK,
+ MII_IS_DOWNLINK => MII_IS_DOWNLINK,
+ MII_IS_UPLINK_ONLY => MII_IS_UPLINK_ONLY,
+ USE_ONEWIRE => c_YES,
+ HARDWARE_VERSION => HARDWARE_INFO,
+ INCLUDED_FEATURES => INCLUDED_FEATURES,
+ INIT_ENDPOINT_ID => x"0001",
+ CLOCK_FREQUENCY => CLOCK_FREQUENCY,
BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR
- )
+ )
port map(
- CLK => clk_sys,
- RESET => reset_i,
- CLK_EN => '1',
-
+ CLK => clk_sys,
+ RESET => reset_i,
+ CLK_EN => '1',
--Media interfacces
- MEDIA_MED2INT => med2int,
- MEDIA_INT2MED => int2med,
-
+ MEDIA_MED2INT => med2int,
+ MEDIA_INT2MED => int2med,
--Event information coming from CTS
- CTS_NUMBER_OUT => cts_number,
- CTS_CODE_OUT => cts_code,
- CTS_INFORMATION_OUT => cts_information,
- CTS_READOUT_TYPE_OUT => cts_readout_type,
- CTS_START_READOUT_OUT => cts_start_readout,
+ CTS_NUMBER_OUT => cts_number,
+ CTS_CODE_OUT => cts_code,
+ CTS_INFORMATION_OUT => cts_information,
+ CTS_READOUT_TYPE_OUT => cts_readout_type,
+ CTS_START_READOUT_OUT => cts_start_readout,
--Information sent to CTS
--status data, equipped with DHDR
- CTS_DATA_IN => cts_data,
- CTS_DATAREADY_IN => cts_dataready,
- CTS_READOUT_FINISHED_IN => cts_readout_finished,
- CTS_READ_OUT => cts_read,
- CTS_LENGTH_IN => cts_length,
- CTS_STATUS_BITS_IN => cts_status_bits,
+ CTS_DATA_IN => cts_data,
+ CTS_DATAREADY_IN => cts_dataready,
+ CTS_READOUT_FINISHED_IN => cts_readout_finished,
+ CTS_READ_OUT => cts_read,
+ CTS_LENGTH_IN => cts_length,
+ CTS_STATUS_BITS_IN => cts_status_bits,
-- Data from Frontends
- FEE_DATA_OUT => fee_data,
- FEE_DATAREADY_OUT => fee_dataready,
- FEE_READ_IN => fee_read,
- FEE_STATUS_BITS_OUT => fee_status_bits,
- FEE_BUSY_OUT => fee_busy,
- MY_ADDRESS_IN => my_address,
- COMMON_STAT_REGS => common_stat_reg, --open,
- COMMON_CTRL_REGS => common_ctrl_reg, --open,
- ONEWIRE => TEMPSENS,
- MY_ADDRESS_OUT => my_address,
- UNIQUE_ID_OUT => mc_unique_id,
- EXTERNAL_SEND_RESET => external_reset_i,
-
- BUS_RX => ctrlbus_rx,
- BUS_TX => ctrlbus_tx,
- TIMER => timer,
-
+ FEE_DATA_OUT => fee_data,
+ FEE_DATAREADY_OUT => fee_dataready,
+ FEE_READ_IN => fee_read,
+ FEE_STATUS_BITS_OUT => fee_status_bits,
+ FEE_BUSY_OUT => fee_busy,
+ MY_ADDRESS_IN => my_address,
+ COMMON_STAT_REGS => common_stat_reg,
+ COMMON_CTRL_REGS => common_ctrl_reg,
+ ONEWIRE => TEMPSENS,
+ MY_ADDRESS_OUT => my_address,
+ UNIQUE_ID_OUT => mc_unique_id,
+ EXTERNAL_SEND_RESET => external_reset_i,
+ --
+ BUS_RX => ctrlbus_rx,
+ BUS_TX => ctrlbus_tx,
+ TIMER => timer,
--Gbe Sctrl Input
- GSC_INIT_DATAREADY_IN => gsc_init_dataready,
- GSC_INIT_DATA_IN => gsc_init_data,
- GSC_INIT_PACKET_NUM_IN => gsc_init_packet_num,
- GSC_INIT_READ_OUT => gsc_init_read,
- GSC_REPLY_DATAREADY_OUT => gsc_reply_dataready,
- GSC_REPLY_DATA_OUT => gsc_reply_data,
- GSC_REPLY_PACKET_NUM_OUT => gsc_reply_packet_num,
- GSC_REPLY_READ_IN => gsc_reply_read,
- GSC_BUSY_OUT => gsc_busy,
-
- --status and control ports
- HUB_STAT_CHANNEL => open,
- HUB_STAT_GEN => open,
- MPLEX_CTRL => (others => '0'),
- MPLEX_STAT => open,
- STAT_REGS => open,
- STAT_CTRL_REGS => open,
-
+ GSC_INIT_DATAREADY_IN => gsc_init_dataready,
+ GSC_INIT_DATA_IN => gsc_init_data,
+ GSC_INIT_PACKET_NUM_IN => gsc_init_packet_num,
+ GSC_INIT_READ_OUT => gsc_init_read,
+ GSC_REPLY_DATAREADY_OUT => gsc_reply_dataready,
+ GSC_REPLY_DATA_OUT => gsc_reply_data,
+ GSC_REPLY_PACKET_NUM_OUT => gsc_reply_packet_num,
+ GSC_REPLY_READ_IN => gsc_reply_read,
+ GSC_BUSY_OUT => gsc_busy,
+ --status and control ports
+ HUB_STAT_CHANNEL => open,
+ HUB_STAT_GEN => open,
+ MPLEX_CTRL => (others => '0'),
+ MPLEX_STAT => open,
+ STAT_REGS => open,
+ STAT_CTRL_REGS => open,
--Fixed status and control ports
- STAT_DEBUG => open,
- CTRL_DEBUG => (others => '0')
+ STAT_DEBUG => open,
+ CTRL_DEBUG => (others => '0')
);
- external_reset_i <= reset_via_gbe; -- or med2int(9).stat_op(13);
+ external_reset_i <= reset_via_gbe;
process begin
wait until rising_edge(clk_sys);
end generate;
-
---------------------------------------------------------------------------
-- Hub without GbE
---------------------------------------------------------------------------
THE_HUB : trb_net16_hub_base
generic map(
- HUB_USED_CHANNELS => (1,1,0,1),
- INIT_ADDRESS => INIT_ADDRESS,
- MII_NUMBER => INTERFACE_NUM,
- MII_IS_UPLINK => MII_IS_UPLINK,
- MII_IS_DOWNLINK => MII_IS_DOWNLINK,
- MII_IS_UPLINK_ONLY => MII_IS_UPLINK_ONLY,
- USE_ONEWIRE => c_YES,
- HARDWARE_VERSION => HARDWARE_INFO,
- INCLUDED_FEATURES => INCLUDED_FEATURES,
- INIT_ENDPOINT_ID => x"0001",
- CLOCK_FREQUENCY => CLOCK_FREQUENCY,
+ HUB_USED_CHANNELS => (1,1,0,1),
+ INIT_ADDRESS => INIT_ADDRESS,
+ MII_NUMBER => INTERFACE_NUM,
+ MII_IS_UPLINK => MII_IS_UPLINK,
+ MII_IS_DOWNLINK => MII_IS_DOWNLINK,
+ MII_IS_UPLINK_ONLY => MII_IS_UPLINK_ONLY,
+ USE_ONEWIRE => c_YES,
+ HARDWARE_VERSION => HARDWARE_INFO,
+ INCLUDED_FEATURES => INCLUDED_FEATURES,
+ INIT_ENDPOINT_ID => x"0001",
+ CLOCK_FREQUENCY => CLOCK_FREQUENCY,
BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR,
- COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32))
- )
+ COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32))
+ )
port map (
CLK => clk_sys,
RESET => reset_i,
CLK_EN => '1',
-
- --Media interfacces
+ --Media interfacces
MED_DATAREADY_OUT(INTERFACE_NUM*1-1 downto 0) => med_dataready_out(INTERFACE_NUM*1-1 downto 0),
MED_DATA_OUT(INTERFACE_NUM*16-1 downto 0) => med_data_out(INTERFACE_NUM*16-1 downto 0),
MED_PACKET_NUM_OUT(INTERFACE_NUM*3-1 downto 0) => med_packet_num_out(INTERFACE_NUM*3-1 downto 0),
MED_READ_OUT(INTERFACE_NUM*1-1 downto 0) => med_read_out(INTERFACE_NUM*1-1 downto 0),
MED_STAT_OP(INTERFACE_NUM*16-1 downto 0) => med_stat_op(INTERFACE_NUM*16-1 downto 0),
MED_CTRL_OP(INTERFACE_NUM*16-1 downto 0) => med_ctrl_op(INTERFACE_NUM*16-1 downto 0),
-
- COMMON_STAT_REGS => common_stat_reg,
- COMMON_CTRL_REGS => common_ctrl_reg,
- MY_ADDRESS_OUT => my_address,
+ --
+ COMMON_STAT_REGS => common_stat_reg,
+ COMMON_CTRL_REGS => common_ctrl_reg,
+ MY_ADDRESS_OUT => my_address,
--REGIO INTERFACE
- REGIO_ADDR_OUT => ctrlbus_rx.addr,
- REGIO_READ_ENABLE_OUT => ctrlbus_rx.read,
- REGIO_WRITE_ENABLE_OUT => ctrlbus_rx.write,
- REGIO_DATA_OUT => ctrlbus_rx.data,
- REGIO_DATA_IN => ctrlbus_tx.data,
- REGIO_DATAREADY_IN => rdack,
- REGIO_NO_MORE_DATA_IN => ctrlbus_tx.nack,
- REGIO_WRITE_ACK_IN => wrack,
- REGIO_UNKNOWN_ADDR_IN => ctrlbus_tx.unknown,
- REGIO_TIMEOUT_OUT => ctrlbus_rx.timeout,
-
- ONEWIRE => TEMPSENS,
- ONEWIRE_MONITOR_OUT => open,
+ REGIO_ADDR_OUT => ctrlbus_rx.addr,
+ REGIO_READ_ENABLE_OUT => ctrlbus_rx.read,
+ REGIO_WRITE_ENABLE_OUT => ctrlbus_rx.write,
+ REGIO_DATA_OUT => ctrlbus_rx.data,
+ REGIO_DATA_IN => ctrlbus_tx.data,
+ REGIO_DATAREADY_IN => rdack,
+ REGIO_NO_MORE_DATA_IN => ctrlbus_tx.nack,
+ REGIO_WRITE_ACK_IN => wrack,
+ REGIO_UNKNOWN_ADDR_IN => ctrlbus_tx.unknown,
+ REGIO_TIMEOUT_OUT => ctrlbus_rx.timeout,
+ --
+ ONEWIRE => TEMPSENS,
+ ONEWIRE_MONITOR_OUT => open,
--Status ports (for debugging)
- MPLEX_CTRL => (others => '0'),
- CTRL_DEBUG => (others => '0'),
- STAT_DEBUG => open
- );
+ MPLEX_CTRL => (others => '0'),
+ CTRL_DEBUG => (others => '0'),
+ STAT_DEBUG => open
+ );
gen_media_record : for i in 0 to INTERFACE_NUM-1 generate
med_data_in(i*16+15 downto i*16) <= med2int(i).data;
int2med(i).ctrl_op <= med_ctrl_op(i*16+15 downto i*16);
end generate;
- rdack <= ctrlbus_tx.ack or ctrlbus_tx.rack;
- wrack <= ctrlbus_tx.ack or ctrlbus_tx.wack;
+ rdack <= ctrlbus_tx.ack or ctrlbus_tx.rack;
+ wrack <= ctrlbus_tx.ack or ctrlbus_tx.wack;
reboot_from_gbe <= '0';
reset_via_gbe <= '0';
external_reset_delayed <= (others => '0');
PORT_ADDRESSES => (0 => x"d000", 1 => x"d300", 2 => x"b000", 3 => x"b200", 4 => x"b400", 5 => x"8100", 6 => x"8300", 7 => x"b600", others => x"0000"),
PORT_ADDR_MASK => (0 => 12, 1 => 1, 2 => 9, 3 => 9, 4 => 9, 5 => 8, 6 => 8, 7 => 9, others => 0),
PORT_MASK_ENABLE => 1
- )
+ )
port map(
- CLK => clk_sys,
- RESET => reset_i,
-
- REGIO_RX => handlerbus_rx,
- REGIO_TX => ctrlbus_tx,
-
- BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED
- BUS_RX(1) => bustc_rx, --Clock switch
- BUS_RX(2) => bussci1_rx, --SCI Serdes
- BUS_RX(3) => bussci2_rx,
- BUS_RX(4) => bussci3_rx,
- BUS_RX(5) => busgbeip_rx,
- BUS_RX(6) => busgbereg_rx,
- BUS_RX(7) => bussci4_rx,
- BUS_TX(0) => bustools_tx,
- BUS_TX(1) => bustc_tx,
- BUS_TX(2) => bussci1_tx,
- BUS_TX(3) => bussci2_tx,
- BUS_TX(4) => bussci3_tx,
- BUS_TX(5) => busgbeip_tx,
- BUS_TX(6) => busgbereg_tx,
- BUS_TX(7) => bussci4_tx,
+ CLK => clk_sys,
+ RESET => reset_i,
+ --
+ REGIO_RX => handlerbus_rx,
+ REGIO_TX => ctrlbus_tx,
+ --
+ BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED
+ BUS_RX(1) => bustc_rx, --Clock switch
+ BUS_RX(2) => bussci1_rx, --SCI Serdes
+ BUS_RX(3) => bussci2_rx,
+ BUS_RX(4) => bussci3_rx,
+ BUS_RX(5) => busgbeip_rx,
+ BUS_RX(6) => busgbereg_rx,
+ BUS_RX(7) => bussci4_rx,
+ BUS_TX(0) => bustools_tx,
+ BUS_TX(1) => bustc_tx,
+ BUS_TX(2) => bussci1_tx,
+ BUS_TX(3) => bussci2_tx,
+ BUS_TX(4) => bussci3_tx,
+ BUS_TX(5) => busgbeip_tx,
+ BUS_TX(6) => busgbereg_tx,
+ BUS_TX(7) => bussci4_tx,
STAT_DEBUG => open
- );
+ );
handlerbus_rx <= ctrlbus_rx when bus_master_active = '0' else bus_master_out;
---------------------------------------------------------------------------
THE_TOOLS: entity work.trb3sc_tools
port map(
- CLK => clk_sys,
- RESET => reset_i,
-
+ CLK => clk_sys,
+ RESET => reset_i,
--Flash & Reload
- FLASH_CS => FLASH_CS,
- FLASH_CLK => FLASH_CLK,
- FLASH_IN => FLASH_OUT,
- FLASH_OUT => FLASH_IN,
- PROGRAMN => PROGRAMN,
- REBOOT_IN => do_reboot_i,
+ FLASH_CS => FLASH_CS,
+ FLASH_CLK => FLASH_CLK,
+ FLASH_IN => FLASH_OUT,
+ FLASH_OUT => FLASH_IN,
+ PROGRAMN => PROGRAMN,
+ REBOOT_IN => do_reboot_i,
--SPI
- SPI_CS_OUT => spi_cs,
- SPI_MOSI_OUT=> spi_mosi,
- SPI_MISO_IN => spi_miso,
- SPI_CLK_OUT => spi_clk,
+ SPI_CS_OUT => spi_cs,
+ SPI_MOSI_OUT => spi_mosi,
+ SPI_MISO_IN => spi_miso,
+ SPI_CLK_OUT => spi_clk,
--Header
- HEADER_IO => HDR_IO,
+ HEADER_IO => HDR_IO,
--LCD
- LCD_DATA_IN => lcd_data,
+ LCD_DATA_IN => lcd_data,
--ADC
- ADC_CS => ADC_CS,
- ADC_MOSI => ADC_DIN,
- ADC_MISO => ADC_DOUT,
- ADC_CLK => ADC_CLK,
+ ADC_CS => ADC_CS,
+ ADC_MOSI => ADC_DIN,
+ ADC_MISO => ADC_DOUT,
+ ADC_CLK => ADC_CLK,
--Trigger & Monitor
- MONITOR_INPUTS => monitor_inputs_i,
--- MONITOR_INPUTS(21 downto 18) => trig_gen_out_i,
- TRIG_GEN_INPUTS => trigger_inputs_i,
- TRIG_GEN_OUTPUTS => trig_gen_out_i,
+ MONITOR_INPUTS => monitor_inputs_i,
+ TRIG_GEN_INPUTS => trigger_inputs_i,
+ TRIG_GEN_OUTPUTS => trig_gen_out_i,
--SED
- SED_ERROR_OUT => sed_error_i,
+ SED_ERROR_OUT => sed_error_i,
--Slowcontrol
- BUS_RX => bustools_rx,
- BUS_TX => bustools_tx,
+ BUS_RX => bustools_rx,
+ BUS_TX => bustools_tx,
--Control master for default settings
- BUS_MASTER_IN => ctrlbus_tx,
- BUS_MASTER_OUT => bus_master_out,
+ BUS_MASTER_IN => ctrlbus_tx,
+ BUS_MASTER_OUT => bus_master_out,
BUS_MASTER_ACTIVE => bus_master_active,
- DEBUG_OUT => open
- );
+ DEBUG_OUT => open
+ );
-monitor_inputs_i(21 downto 18) <= trig_gen_out_i;
-monitor_inputs_i(53 downto 22) <= INP(95 downto 64);
+ monitor_inputs_i(21 downto 18) <= trig_gen_out_i;
+ monitor_inputs_i(53 downto 22) <= INP(95 downto 64);
-trigger_inputs_i(21 downto 18) <= (others => '0');
-trigger_inputs_i(53 downto 22) <= INP(95 downto 64);
+ trigger_inputs_i(21 downto 18) <= (others => '0');
+ trigger_inputs_i(53 downto 22) <= INP(95 downto 64);
spi_miso(5 downto 4) <= DAC_IN_SDI(6 downto 5);
DAC_OUT_SCK(6 downto 5) <= spi_clk(5 downto 4);
DAC_OUT_CS(6 downto 5) <= spi_cs(5 downto 4);
DAC_OUT_SDO(6 downto 5) <= spi_mosi(5 downto 4);
-
-do_reboot_i <= common_ctrl_reg(15) or reboot_from_gbe;
+ do_reboot_i <= common_ctrl_reg(15) or reboot_from_gbe;
---------------------------------------------------------------------------
-- Switches
PCSSW_PE <= x"F";
PCSSW <= "01001110"; --SFP2 on B3, AddOn on D1
-
---------------------------------------------------------------------------
-- LED
---------------------------------------------------------------------------
LED_WHITE <= led;
LED_SFP_GREEN(1) <= not med2int(9).stat_op(9); --SFP Link Status
LED_SFP_RED(1) <= not (med2int(9).stat_op(10) or med2int(9).stat_op(11)); --SFP RX/TX
-gen_led_nogbe : if INCLUDE_GBE = c_NO generate
- LED_SFP_GREEN(0) <= not med2int(10).stat_op(9); --SFP Link Status
- LED_SFP_RED(0) <= not (med2int(10).stat_op(10) or med2int(10).stat_op(11)); --SFP RX/TX
-end generate;
-gen_led_gbe : if INCLUDE_GBE = c_YES generate
- LED_SFP_GREEN(0) <= '1';
- LED_SFP_RED(0) <= '1';
-end generate;
+ gen_led_nogbe : if INCLUDE_GBE = c_NO generate
+ LED_SFP_GREEN(0) <= not med2int(10).stat_op(9); --SFP Link Status
+ LED_SFP_RED(0) <= not (med2int(10).stat_op(10) or med2int(10).stat_op(11)); --SFP RX/TX
+ end generate;
+ gen_led_gbe : if INCLUDE_GBE = c_YES generate
+ LED_SFP_GREEN(0) <= '1';
+ LED_SFP_RED(0) <= '1';
+ end generate;
---------------------------------------------------------------------------
-- LCD Data to display
---------------------------------------------------------------------------
led(0) <= time_counter(26) and time_counter(16);
led(1) <= not (clear_i or reset_i);
-
--- TEST_LINE <= med_stat_debug(15 downto 0);
TEST_LINE(0) <= med2int(9).stat_op(13);
TEST_LINE(1) <= med2int(9).stat_op(15);
TEST_LINE(2) <= clear_i;
TEST_LINE(5) <= int2med(9).dataready;
TEST_LINE(6) <= med2int(7).dataready;
TEST_LINE(7) <= int2med(7).dataready;
--- TEST_LINE(7) <= med2int(9).stat_op(9);
end architecture;
--- /dev/null
+config_simple.vhd
\ No newline at end of file
--- /dev/null
+TOPNAME => "trb3sc_cts",
+lm_license_file_for_synplify => "27000\@lxcad04.gsi.de",
+lm_license_file_for_par => "1702\@hadeb05.gsi.de",
+lattice_path => '/opt/lattice/diamond/3.12',
+synplify_path => '/opt/synplicity/R-2020.09-SP1',
+synplify_command => "/opt/synplicity/R-2020.09-SP1/bin/synplify_premier",
+
+nodelist_file => 'nodelist.txt',
+pinout_file => 'trb3sc_hub_kelpadiwa',
+par_options => '../par.p2t',
+
+include_TDC => 0,
+include_GBE => 1,
+
+firefox_open => 0,
+twr_number_of_errors => 20,
+no_ltxt2ptxt => 0, #if there is no serdes being used
+
package config is
-
------------------------------------------------------------------------------
--Begin of design configuration
------------------------------------------------------------------------------
+-- FPGA type
+ constant FPGA_TYPE : integer := 3; --3: ECP3, 5: ECP5
+
--design options: backplane or front SFP, with or without GBE
- constant USE_BACKPLANE : integer := c_NO; --c_YES doesn't work
- constant USE_ADDON : integer := c_NO;
- constant USE_RJADAPT : integer := c_NO; --!!! Change pin-out file!
- constant INCLUDE_GBE : integer := c_YES; --c_NO doesn't work
+ constant USE_BACKPLANE : integer := c_NO; --c_YES doesn't work
+ constant USE_ADDON : integer := c_NO;
+ constant USE_RJADAPT : integer := c_NO; --!!! Change pin-out file!
+ constant INCLUDE_GBE : integer := c_YES; --c_NO doesn't work
--Runs with 120 MHz instead of 100 MHz
- constant USE_120_MHZ : integer := c_NO;
- constant USE_200MHZOSCILLATOR : integer := c_YES;
- constant USE_EXTERNAL_CLOCK : integer := c_YES; --'no' not implemented.
- constant CLOCK_FAST_SELECT : integer := c_YES; --fast clock select (135us) or slow (280ms)?
+ constant USE_120_MHZ : integer := c_NO;
+ constant USE_200MHZOSCILLATOR : integer := c_YES;
+ constant USE_EXTERNAL_CLOCK : integer := c_YES; --'no' not implemented.
+ constant CLOCK_FAST_SELECT : integer := c_YES; --fast clock select (135us) or slow (280ms)?
--Use sync mode, RX clock for all parts of the FPGA
- constant USE_RXCLOCK : integer := c_NO;
+ constant USE_RXCLOCK : integer := c_NO;
--Address settings
- constant INIT_ADDRESS : std_logic_vector := x"F3C0";
- constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"62"; --62 for SFP, 63 for backplane
-
+ constant INIT_ADDRESS : std_logic_vector := x"F3C0";
+ constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"62"; --62 for SFP, 63 for backplane
- constant INCLUDE_UART : integer := c_YES;
- constant INCLUDE_SPI : integer := c_YES;
- constant INCLUDE_LCD : integer := c_NO;
- constant INCLUDE_DEBUG_INTERFACE : integer := c_YES;
+--Peripherials
+ constant INCLUDE_UART : integer := c_YES;
+ constant INCLUDE_SPI : integer := c_YES;
+ constant INCLUDE_LCD : integer := c_NO;
+ constant INCLUDE_DEBUG_INTERFACE : integer := c_YES;
--input monitor and trigger generation logic
- constant INCLUDE_TDC : integer := c_NO; -- was c_YES
- constant INCLUDE_TRIGGER_LOGIC : integer := c_YES;
- constant INCLUDE_STATISTICS : integer := c_YES;
- constant TRIG_GEN_INPUT_NUM : integer := 36 - USE_RJADAPT*12;
- constant TRIG_GEN_OUTPUT_NUM : integer := 2;
- constant MONITOR_INPUT_NUM : integer := 36 - USE_RJADAPT*12;
-
--- FPGA type
- constant FPGA_TYPE : integer := 3; --3: ECP3, 5: ECP5
-
--- retransmission
- constant USE_RETRANSMISSION : integer := c_YES;
-
- constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement
- constant NUM_TDC_CHANNELS : integer range 1 to 65 := 33; -- number of tdc channels per module
- constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 4; --the nearest power of two, for convenience reasons
- constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 3; --double edge type: 0, 1, 2, 3
- -- 0: single edge only,
- -- 1: same channel,
- -- 2: alternating channels,
- -- 3: same channel with stretcher
- constant RING_BUFFER_SIZE : integer range 0 to 7 := 7; --ring buffer size: 0, 1, 2, 3, 7 --> change names in constraints file
+ constant INCLUDE_TDC : integer := c_NO;
+ constant INCLUDE_TRIGGER_LOGIC : integer := c_YES;
+ constant INCLUDE_STATISTICS : integer := c_YES;
+ constant TRIG_GEN_INPUT_NUM : integer := 36 - USE_RJADAPT*12;
+ constant TRIG_GEN_OUTPUT_NUM : integer := 2;
+ constant MONITOR_INPUT_NUM : integer := 36 - USE_RJADAPT*12;
+
+-- TDC stuff
+ constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement
+ constant NUM_TDC_CHANNELS : integer range 1 to 65 := 33; -- number of tdc channels per module
+ constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 4; --the nearest power of two, for convenience reasons
+ constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 3; --double edge type: 0, 1, 2, 3
+ -- 0: single edge only,
+ -- 1: same channel,
+ -- 2: alternating channels,
+ -- 3: same channel with stretcher
+ constant RING_BUFFER_SIZE : integer range 0 to 7 := 7; --ring buffer size: 0, 1, 2, 3, 7 --> change names in constraints file
--ring buffer size: 32,64,96,128,dyn
- constant TDC_DATA_FORMAT : integer := 0;
+ constant TDC_DATA_FORMAT : integer := 0;
- constant EVENT_BUFFER_SIZE : integer range 9 to 13 := 13; -- size of the event buffer, 2**N
- constant EVENT_MAX_SIZE : integer := 1023; --maximum event size. Should not exceed
+ constant EVENT_BUFFER_SIZE : integer range 9 to 13 := 13; -- size of the event buffer, 2**N
+ constant EVENT_MAX_SIZE : integer := 1023; --maximum event size. Should not exceed
- constant GEN_BUSY_OUTPUT : integer := c_NO;
+ constant GEN_BUSY_OUTPUT : integer := c_NO;
- constant TRIGGER_COIN_COUNT : integer := 1;
- constant TRIGGER_PULSER_COUNT : integer := 3;
- constant TRIGGER_RAND_PULSER : integer := 1;
- constant TRIGGER_ADDON_COUNT : integer := 4;
- constant PERIPH_TRIGGER_COUNT : integer := 0;
- constant ADDON_LINE_COUNT : integer := 36 - USE_RJADAPT*12; --36 with Padiwa, 22 with RJ-adapter
- constant CTS_OUTPUT_MULTIPLEXERS : integer := 1;
+ constant TRIGGER_COIN_COUNT : integer := 1;
+ constant TRIGGER_PULSER_COUNT : integer := 3;
+ constant TRIGGER_RAND_PULSER : integer := 1;
+ constant TRIGGER_ADDON_COUNT : integer := 4;
+ constant PERIPH_TRIGGER_COUNT : integer := 0;
+ constant ADDON_LINE_COUNT : integer := 36 - USE_RJADAPT*12; --36 with Padiwa, 22 with RJ-adapter
+ constant CTS_OUTPUT_MULTIPLEXERS : integer := 1;
--TODO:
-- constant INCLUDE_MBS_MASTER : integer range c_NO to c_YES := c_NO;
--Which external trigger module (ETM) to use?
constant INCLUDE_TIMESTAMP_GENERATOR : integer := c_NO;
-
-
------------------------------------------------------------------------------
--End of design configuration
------------------------------------------------------------------------------
--- /dev/null
+// nodes file for parallel place&route
+
+[hades66]
+system = linux
+corenum = 24
+ENV = /home/compile/bin/diamond_env
+workdir = /home/compile/vhdl/dirich/dirich/workdir
+
-# -w
-# -i 15
-# -l 5
-# -y
-# -s 12
-# -t 26
-# -c 1
-# -e 2
-# #-g guidefile.ncd
-# #-m nodelist.txt
-# # -w
-# # -i 6
-# # -l 5
-# # -n 1
-# # -t 1
-# # -s 1
-# # -c 0
-# # -e 0
-# #
-#
-w
-#-y
-l 5
-#-m nodelist.txt # Controlled by the compile.pl script.
-#-n 1 # Controlled by the compile.pl script.
-s 10
--t 3
+-t 3 # seed setting here!
-c 0
-e 0
-i 6
--exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1:parHold=ON:parHoldLimit=10000:parCDP=auto:parCDR=1:parPathBased=OFF:paruseNBR=1:parHold=2
+-exp parCDP=auto:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1
+#General PAR Command Line Options
+# -w With this option, any files generated will overwrite existing files
+# (e.g., any .par, .pad files).
+# -y Adds the Delay Summary Report in the .par file and creates the delay
+# file (in .dly format) at the end of the par run.
+#
+#PAR Placement Command Line Options
+# -l Specifies the effort level of the design from 1 (simplest designs)
+# to 5 (most complex designs).
+# -m Multi-tasking option. Controlled by the compile.pl script.
+# -n Sets the number of iterations performed at the effort level
+# specified by the -l option. Controlled by the compile.pl script.
+# -s Save the number of best results for this run.
+# -t Start placement at the specified cost table. Default is 1.
+#
+#PAR Routing Command Line Options
+# -c Run number of cost-based cleanup passes of the router.
+# -e Run number of delay-based cleanup passes of the router on
+# completely-routed designs only.
+# -i Run a maximum number of passes, stopping earlier only if the routing
+# goes to 100 percent completion and all constraints are met.
+#
+#PAR Explorer Command Line Options
+# parCDP Enable the congestion-driven placement (CDP) algorithm. CDP is
+# compatible with all Lattice FPGA device families; however, most
+# benefit has been demonstrated with benchmarks targeted to ECP5,
+# LatticeECP2/M, LatticeECP3, and LatticeXP2 device families.
+# parCDR Enable the congestion-driven router (CDR) algorithm.
+# Congestion-driven options like parCDR and parCDP can improve
+# performance given a design with multiple congestion “hotspots.” The
+# Layer > Congestion option of the Design Planner Floorplan View can
+# help visualize routing congestion. Large congested areas may prevent
+# the options from finding a successful solution.
+# CDR is compatible with all Lattice FPGA device families however most
+# benefit has been demonstrated with benchmarks targeted to ECP5,
+# LatticeECP2/M,LatticeECP3, and LatticeXP2 device families.
+# paruseNBR NBR Router or Negotiation-based routing option. Supports all
+# FPGA device families except LatticeXP and MachXO.
+# When turned on, an alternate routing engine from the traditional
+# Rip-up-based routing selection (RBR) is used. This involves an
+# iterative routing algorithm that routes connections to achieve
+# minimum delay cost. It does so by computing the demand on each
+# routing resource and applying cost values per node. It will
+# complete when an optimal solution is arrived at or the number of
+# iterations is reached.
+# parPathBased Path-based placement option. Path-based timing driven
+# placement will yield better performance and more
+# predictable results in many cases.
+# parHold Additional hold time correction option. This option
+# forces the router to automatically insert extra wires to compensate for the
+# hold time violation.
+# parHoldLimit This option allows you to set a limit on the number of
+# hold time violations to be processed by the auto hold time correction option
+# parHold.
+# parPlcInLimit Cannot find in the online help
+# parPlcInNeighborSize Cannot find in the online help
+
ADC_DOUT : in std_logic;
--SPI
- DAC_OUT_SDO : out std_logic_vector(6 downto 5+2*USE_RJADAPT); --
- DAC_OUT_SCK : out std_logic_vector(6 downto 5+2*USE_RJADAPT); --
- DAC_OUT_CS : out std_logic_vector(6 downto 5+2*USE_RJADAPT); --
- DAC_IN_SDI : in std_logic_vector(6 downto 5+2*USE_RJADAPT); --
+ DAC_OUT_SDO : out std_logic_vector(6 downto 5+2*USE_RJADAPT);
+ DAC_OUT_SCK : out std_logic_vector(6 downto 5+2*USE_RJADAPT);
+ DAC_OUT_CS : out std_logic_vector(6 downto 5+2*USE_RJADAPT);
+ DAC_IN_SDI : in std_logic_vector(6 downto 5+2*USE_RJADAPT);
-
--Flash, 1-wire, Reload
FLASH_CLK : out std_logic;
FLASH_CS : out std_logic;
--Test Connectors
TEST_LINE : out std_logic_vector(15 downto 0)
- );
+ );
-
- attribute syn_useioff : boolean;
+ attribute syn_useioff : boolean;
attribute syn_useioff of FLASH_CLK : signal is true;
attribute syn_useioff of FLASH_CS : signal is true;
attribute syn_useioff of FLASH_IN : signal is true;
attribute syn_useioff of FLASH_OUT : signal is true;
- attribute syn_useioff of SPARE_IN : signal is false;
- attribute syn_useioff of INP : signal is false;
+ attribute syn_useioff of SPARE_IN : signal is false;
+ attribute syn_useioff of INP : signal is false;
end entity;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
--- constant CTS_ADDON_LINE_COUNT : integer := 18;
--- constant CTS_OUTPUT_MULTIPLEXERS : integer := 1;
--- constant CTS_OUTPUT_INPUTS : integer := 16;
-
-
-
signal clk_sys, clk_full, clk_full_osc, clk_cal : std_logic;
signal GSR_N : std_logic;
signal reset_i : std_logic;
signal cts_rdo_rx : READOUT_RX;
signal cts_addon_triggers_in : std_logic_vector(ADDON_LINE_COUNT-1 downto 0);
--- signal cts_addon_activity_i,
--- cts_addon_selected_i : std_logic_vector(6 downto 0);
-
--- signal cts_periph_trigger_i : std_logic_vector(19 downto 0);
--- signal cts_output_multiplexers_i : std_logic_vector(CTS_OUTPUT_MULTIPLEXERS - 1 downto 0);
-
--- signal cts_periph_lines_i : std_logic_vector(CTS_OUTPUT_INPUTS - 1 downto 0);
signal cts_trg_send : std_logic;
signal cts_trg_type : std_logic_vector(3 downto 0);
begin
-
---------------------------------------------------------------------------
-- Clock & Reset Handling
---------------------------------------------------------------------------
EXT_CLK_IN => CLK_EXT_PLL_LEFT,
NET_CLK_FULL_IN => '0',
NET_CLK_HALF_IN => '0',
- RESET_FROM_NET => make_reset,
-
+ RESET_FROM_NET => make_reset,
BUS_RX => bustc_rx,
BUS_TX => bustc_tx,
-
RESET_OUT => reset_i,
CLEAR_OUT => clear_i,
GSR_OUT => GSR_N,
-
FULL_CLK_OUT => clk_full,
SYS_CLK_OUT => clk_sys,
- REF_CLK_OUT => clk_full_osc,
-
+ REF_CLK_OUT => clk_full_osc,
ENPIRION_CLOCK => ENPIRION_CLOCK,
LED_RED_OUT => LED_RJ_RED,
LED_GREEN_OUT => LED_RJ_GREEN,
DEBUG_OUT => debug_clock_reset
- );
+ );
proc_make_reset : process begin
port map (
CLK => CLK_SUPPL_PCLK,
CLKOP => clk_cal,
- LOCK => open);
+ LOCK => open
+ );
---------------------------------------------------------------------------
-- PCSA
---------------------------------------------------------------------------
-bussci1_tx.data <= (others => '0');
-bussci1_tx.ack <= '0';
-bussci1_tx.nack <= '0';
+bussci1_tx.data <= (others => '0');
+bussci1_tx.ack <= '0';
+bussci1_tx.nack <= '0';
bussci1_tx.unknown <= '1';
-
---------------------------------------------------------------------------
-- PCSB Downlink without backplane is SFP
---------------------------------------------------------------------------
generic map(
SERDES_NUM => 3,
IS_SYNC_SLAVE => c_NO
- )
+ )
port map(
CLK_REF_FULL => clk_full_osc,
CLK_INTERNAL_FULL => clk_full_osc,
- SYSCLK => clk_sys,
- RESET => reset_i,
- CLEAR => clear_i,
+ SYSCLK => clk_sys,
+ RESET => reset_i,
+ CLEAR => clear_i,
--Internal Connection
- MEDIA_MED2INT => med2int(0),
- MEDIA_INT2MED => int2med(0),
-
- --Sync operation
- RX_DLM => open,
- RX_DLM_WORD => open,
- TX_DLM => open,
- TX_DLM_WORD => open,
-
+ MEDIA_MED2INT => med2int(0),
+ MEDIA_INT2MED => int2med(0),
+ --Sync operation
+ RX_DLM => open,
+ RX_DLM_WORD => open,
+ TX_DLM => open,
+ TX_DLM_WORD => open,
--SFP Connection
- SD_PRSNT_N_IN => SFP_MOD0(1),
- SD_LOS_IN => SFP_LOS(1),
- SD_TXDIS_OUT => SFP_TX_DIS(1),
+ SD_PRSNT_N_IN => SFP_MOD0(1),
+ SD_LOS_IN => SFP_LOS(1),
+ SD_TXDIS_OUT => SFP_TX_DIS(1),
--Control Interface
- BUS_RX => bussci2_rx,
- BUS_TX => bussci2_tx,
+ BUS_RX => bussci2_rx,
+ BUS_TX => bussci2_tx,
-- Status and control port
- STAT_DEBUG => open,
- CTRL_DEBUG => open
- );
+ STAT_DEBUG => open,
+ CTRL_DEBUG => open
+ );
PCSSW <= "01001110"; --SFP2 on B3, AddOn on D1
end generate;
generic map(
IS_SYNC_SLAVE => (c_NO, c_NO, c_NO, c_NO),
IS_USED => (c_YES,c_YES ,c_YES ,c_YES)
- )
+ )
port map(
CLK_REF_FULL => clk_full_osc,
CLK_INTERNAL_FULL => clk_full_osc,
SYSCLK => clk_sys,
RESET => reset_i,
CLEAR => clear_i,
-
--Internal Connection
- MEDIA_MED2INT(0) => med2int(2),
- MEDIA_MED2INT(1) => med2int(3),
- MEDIA_MED2INT(2) => med2int(0),
- MEDIA_MED2INT(3) => med2int(1),
- MEDIA_INT2MED(0) => int2med(2),
- MEDIA_INT2MED(1) => int2med(3),
- MEDIA_INT2MED(2) => int2med(0),
- MEDIA_INT2MED(3) => int2med(1),
-
+ MEDIA_MED2INT(0) => med2int(2),
+ MEDIA_MED2INT(1) => med2int(3),
+ MEDIA_MED2INT(2) => med2int(0),
+ MEDIA_MED2INT(3) => med2int(1),
+ MEDIA_INT2MED(0) => int2med(2),
+ MEDIA_INT2MED(1) => int2med(3),
+ MEDIA_INT2MED(2) => int2med(0),
+ MEDIA_INT2MED(3) => int2med(1),
--Sync operation
RX_DLM => open,
RX_DLM_WORD => open,
TX_DLM => open,
TX_DLM_WORD => open,
-
--SFP Connection
SD_PRSNT_N_IN(0) => HUB_MOD0(3),
SD_PRSNT_N_IN(1) => HUB_MOD0(4),
SD_PRSNT_N_IN(2) => HUB_MOD0(1),
SD_PRSNT_N_IN(3) => HUB_MOD0(2),
-
- SD_LOS_IN(0) => HUB_LOS(3),
- SD_LOS_IN(1) => HUB_LOS(4),
- SD_LOS_IN(2) => HUB_LOS(1),
- SD_LOS_IN(3) => HUB_LOS(2),
-
- SD_TXDIS_OUT(0) => HUB_TXDIS(3),
- SD_TXDIS_OUT(1) => HUB_TXDIS(4),
- SD_TXDIS_OUT(2) => HUB_TXDIS(1),
- SD_TXDIS_OUT(3) => HUB_TXDIS(2),
-
+ SD_LOS_IN(0) => HUB_LOS(3),
+ SD_LOS_IN(1) => HUB_LOS(4),
+ SD_LOS_IN(2) => HUB_LOS(1),
+ SD_LOS_IN(3) => HUB_LOS(2),
+ SD_TXDIS_OUT(0) => HUB_TXDIS(3),
+ SD_TXDIS_OUT(1) => HUB_TXDIS(4),
+ SD_TXDIS_OUT(2) => HUB_TXDIS(1),
+ SD_TXDIS_OUT(3) => HUB_TXDIS(2),
--Control Interface
BUS_RX => bussci3_rx,
BUS_TX => bussci3_tx,
-
-- Status and control port
- STAT_DEBUG => open, --med_stat_debug(63 downto 0),
+ STAT_DEBUG => open,
CTRL_DEBUG => open
);
end generate;
generic map(
IS_SYNC_SLAVE => (c_NO, c_NO, c_NO, c_NO),
IS_USED => (c_YES,c_YES ,c_YES ,c_YES)
- )
+ )
port map(
CLK_REF_FULL => clk_full_osc,
CLK_INTERNAL_FULL => clk_full_osc,
SYSCLK => clk_sys,
RESET => reset_i,
CLEAR => clear_i,
-
--Internal Connection
- MEDIA_MED2INT(0) => med2int(4),
- MEDIA_MED2INT(1) => med2int(5),
- MEDIA_MED2INT(2) => med2int(6),
- MEDIA_MED2INT(3) => med2int(7),
- MEDIA_INT2MED(0) => int2med(4),
- MEDIA_INT2MED(1) => int2med(5),
- MEDIA_INT2MED(2) => int2med(6),
- MEDIA_INT2MED(3) => int2med(7),
-
+ MEDIA_MED2INT(0) => med2int(4),
+ MEDIA_MED2INT(1) => med2int(5),
+ MEDIA_MED2INT(2) => med2int(6),
+ MEDIA_MED2INT(3) => med2int(7),
+ MEDIA_INT2MED(0) => int2med(4),
+ MEDIA_INT2MED(1) => int2med(5),
+ MEDIA_INT2MED(2) => int2med(6),
+ MEDIA_INT2MED(3) => int2med(7),
--Sync operation
RX_DLM => open,
RX_DLM_WORD => open,
SD_PRSNT_N_IN(1) => HUB_MOD0(6),
SD_PRSNT_N_IN(2) => HUB_MOD0(7),
SD_PRSNT_N_IN(3) => HUB_MOD0(8),
-
- SD_LOS_IN(0) => HUB_LOS(5),
- SD_LOS_IN(1) => HUB_LOS(6),
- SD_LOS_IN(2) => HUB_LOS(7),
- SD_LOS_IN(3) => HUB_LOS(8),
-
- SD_TXDIS_OUT(0) => HUB_TXDIS(5),
- SD_TXDIS_OUT(1) => HUB_TXDIS(6),
- SD_TXDIS_OUT(2) => HUB_TXDIS(7),
- SD_TXDIS_OUT(3) => HUB_TXDIS(8),
-
+ SD_LOS_IN(0) => HUB_LOS(5),
+ SD_LOS_IN(1) => HUB_LOS(6),
+ SD_LOS_IN(2) => HUB_LOS(7),
+ SD_LOS_IN(3) => HUB_LOS(8),
+ SD_TXDIS_OUT(0) => HUB_TXDIS(5),
+ SD_TXDIS_OUT(1) => HUB_TXDIS(6),
+ SD_TXDIS_OUT(2) => HUB_TXDIS(7),
+ SD_TXDIS_OUT(3) => HUB_TXDIS(8),
--Control Interface
BUS_RX => bussci2_rx,
BUS_TX => bussci2_tx,
-
-- Status and control port
- STAT_DEBUG => open, --med_stat_debug(63 downto 0),
+ STAT_DEBUG => open,
CTRL_DEBUG => open
);
- PCSSW <= "11100100"; --01001110"; --default 1:1
+ PCSSW <= "11100100"; --default 1:1
end generate;
---------------------------------------------------------------------------
LINK_HAS_ARP => "0001",
LINK_HAS_PING => "0001",
LINK_HAS_FWD => "0000"
- )
-
+ )
port map(
CLK_SYS_IN => clk_sys,
CLK_125_IN => CLK_SUPPL_PCLK,
RESET => reset_i,
GSR_N => GSR_N,
-
+ -- Trigger
TRIGGER_IN => cts_rdo_rx.data_valid,
-
+ -- SFP
SD_PRSNT_N_IN(0) => SFP_MOD0(0),
SD_LOS_IN(0) => SFP_LOS(0),
SD_TXDIS_OUT(0) => SFP_TX_DIS(0),
+ -- trigger channel
CTS_NUMBER_IN => gbe_cts_number,
CTS_CODE_IN => gbe_cts_code,
CTS_INFORMATION_IN => gbe_cts_information,
CTS_READ_IN => '1',
CTS_LENGTH_OUT => open,
CTS_ERROR_PATTERN_OUT => gbe_cts_status_bits,
-
+ -- data channel
FEE_DATA_IN => gbe_fee_data,
FEE_DATAREADY_IN => gbe_fee_dataready,
FEE_READ_OUT => gbe_fee_read,
FEE_STATUS_BITS_IN => gbe_fee_status_bits,
FEE_BUSY_IN => gbe_fee_busy,
-
+ -- unique adresses
MC_UNIQUE_ID_IN => timer.uid,
MY_TRBNET_ADDRESS_IN => timer.network_address,
- ISSUE_REBOOT_OUT => reboot_from_gbe,
-
+ ISSUE_REBOOT_OUT => reboot_from_gbe,
+ -- slow control by GbE
GSC_CLK_IN => clk_sys,
GSC_INIT_DATAREADY_OUT => gsc_init_dataready,
GSC_INIT_DATA_OUT => gsc_init_data,
GSC_REPLY_PACKET_NUM_IN => gsc_reply_packet_num,
GSC_REPLY_READ_OUT => gsc_reply_read,
GSC_BUSY_IN => gsc_busy,
-
- BUS_IP_RX => busgbeip_rx,
- BUS_IP_TX => busgbeip_tx,
- BUS_REG_RX => busgbereg_rx,
- BUS_REG_TX => busgbereg_tx,
-
+ -- readout
+ BUS_IP_RX => busgbeip_rx,
+ BUS_IP_TX => busgbeip_tx,
+ BUS_REG_RX => busgbereg_rx,
+ BUS_REG_TX => busgbereg_tx,
+ -- reset
MAKE_RESET_OUT => reset_via_gbe,
-
+ -- debug
DEBUG_OUT => open
- );
-
+ );
---------------------------------------------------------------------------
-- Hub
RDO_DATA_BUFFER_FULL_THRESH => 2**EVENT_BUFFER_SIZE-EVENT_MAX_SIZE,
RDO_HEADER_BUFFER_DEPTH => 9,
RDO_HEADER_BUFFER_FULL_THRESH => 2**9-16
- )
+ )
port map (
- CLK => clk_sys,
- RESET => reset_i,
- CLK_EN => '1',
-
+ CLK => clk_sys,
+ RESET => reset_i,
+ CLK_EN => '1',
-- Media interfacces ---------------------------------------------------------------
MED_DATAREADY_OUT(INTERFACE_NUM*1-1 downto 0) => med_dataready_out(INTERFACE_NUM*1-1 downto 0),
MED_DATA_OUT(INTERFACE_NUM*16-1 downto 0) => med_data_out(INTERFACE_NUM*16-1 downto 0),
MED_READ_OUT(INTERFACE_NUM*1-1 downto 0) => med_read_out(INTERFACE_NUM*1-1 downto 0),
MED_STAT_OP(INTERFACE_NUM*16-1 downto 0) => med_stat_op(INTERFACE_NUM*16-1 downto 0),
MED_CTRL_OP(INTERFACE_NUM*16-1 downto 0) => med_ctrl_op(INTERFACE_NUM*16-1 downto 0),
-
-- Gbe Read-out Path ---------------------------------------------------------------
--Event information coming from CTS for GbE
- GBE_CTS_NUMBER_OUT => gbe_cts_number,
- GBE_CTS_CODE_OUT => gbe_cts_code,
- GBE_CTS_INFORMATION_OUT => gbe_cts_information,
- GBE_CTS_READOUT_TYPE_OUT => gbe_cts_readout_type,
- GBE_CTS_START_READOUT_OUT => gbe_cts_start_readout,
+ GBE_CTS_NUMBER_OUT => gbe_cts_number,
+ GBE_CTS_CODE_OUT => gbe_cts_code,
+ GBE_CTS_INFORMATION_OUT => gbe_cts_information,
+ GBE_CTS_READOUT_TYPE_OUT => gbe_cts_readout_type,
+ GBE_CTS_START_READOUT_OUT => gbe_cts_start_readout,
--Information sent to CTS
- GBE_CTS_READOUT_FINISHED_IN => gbe_cts_readout_finished,
- GBE_CTS_STATUS_BITS_IN => gbe_cts_status_bits,
+ GBE_CTS_READOUT_FINISHED_IN => gbe_cts_readout_finished,
+ GBE_CTS_STATUS_BITS_IN => gbe_cts_status_bits,
-- Data from Frontends
- GBE_FEE_DATA_OUT => gbe_fee_data,
- GBE_FEE_DATAREADY_OUT => gbe_fee_dataready,
- GBE_FEE_READ_IN => gbe_fee_read,
- GBE_FEE_STATUS_BITS_OUT => gbe_fee_status_bits,
- GBE_FEE_BUSY_OUT => gbe_fee_busy,
-
+ GBE_FEE_DATA_OUT => gbe_fee_data,
+ GBE_FEE_DATAREADY_OUT => gbe_fee_dataready,
+ GBE_FEE_READ_IN => gbe_fee_read,
+ GBE_FEE_STATUS_BITS_OUT => gbe_fee_status_bits,
+ GBE_FEE_BUSY_OUT => gbe_fee_busy,
-- CTS Request Sending -------------------------------------------------------------
--LVL1 trigger
- CTS_TRG_SEND_IN => cts_trg_send,
- CTS_TRG_TYPE_IN => cts_trg_type,
- CTS_TRG_NUMBER_IN => cts_trg_number,
- CTS_TRG_INFORMATION_IN => cts_trg_information,
- CTS_TRG_RND_CODE_IN => cts_trg_code,
- CTS_TRG_STATUS_BITS_OUT => cts_trg_status_bits,
- CTS_TRG_BUSY_OUT => cts_trg_busy,
+ CTS_TRG_SEND_IN => cts_trg_send,
+ CTS_TRG_TYPE_IN => cts_trg_type,
+ CTS_TRG_NUMBER_IN => cts_trg_number,
+ CTS_TRG_INFORMATION_IN => cts_trg_information,
+ CTS_TRG_RND_CODE_IN => cts_trg_code,
+ CTS_TRG_STATUS_BITS_OUT => cts_trg_status_bits,
+ CTS_TRG_BUSY_OUT => cts_trg_busy,
--IPU Channel
- CTS_IPU_SEND_IN => cts_ipu_send,
- CTS_IPU_TYPE_IN => cts_ipu_type,
- CTS_IPU_NUMBER_IN => cts_ipu_number,
- CTS_IPU_INFORMATION_IN => cts_ipu_information,
- CTS_IPU_RND_CODE_IN => cts_ipu_code,
+ CTS_IPU_SEND_IN => cts_ipu_send,
+ CTS_IPU_TYPE_IN => cts_ipu_type,
+ CTS_IPU_NUMBER_IN => cts_ipu_number,
+ CTS_IPU_INFORMATION_IN => cts_ipu_information,
+ CTS_IPU_RND_CODE_IN => cts_ipu_code,
-- Receiver port
- CTS_IPU_STATUS_BITS_OUT => cts_ipu_status_bits,
- CTS_IPU_BUSY_OUT => cts_ipu_busy,
-
+ CTS_IPU_STATUS_BITS_OUT => cts_ipu_status_bits,
+ CTS_IPU_BUSY_OUT => cts_ipu_busy,
-- CTS Data Readout ----------------------------------------------------------------
--Trigger to CTS out
- RDO_TRIGGER_IN => cts_trigger_out,
- RDO_TRG_DATA_VALID_OUT => cts_rdo_rx.data_valid,
- RDO_VALID_TIMING_TRG_OUT => cts_rdo_rx.valid_timing_trg,
- RDO_VALID_NOTIMING_TRG_OUT => cts_rdo_rx.valid_notiming_trg,
- RDO_INVALID_TRG_OUT => cts_rdo_rx.invalid_trg,
- RDO_TRG_TYPE_OUT => cts_rdo_rx.trg_type,
- RDO_TRG_CODE_OUT => cts_rdo_rx.trg_code,
- RDO_TRG_INFORMATION_OUT => cts_rdo_rx.trg_information,
- RDO_TRG_NUMBER_OUT => cts_rdo_rx.trg_number,
-
+ RDO_TRIGGER_IN => cts_trigger_out,
+ RDO_TRG_DATA_VALID_OUT => cts_rdo_rx.data_valid,
+ RDO_VALID_TIMING_TRG_OUT => cts_rdo_rx.valid_timing_trg,
+ RDO_VALID_NOTIMING_TRG_OUT => cts_rdo_rx.valid_notiming_trg,
+ RDO_INVALID_TRG_OUT => cts_rdo_rx.invalid_trg,
+ RDO_TRG_TYPE_OUT => cts_rdo_rx.trg_type,
+ RDO_TRG_CODE_OUT => cts_rdo_rx.trg_code,
+ RDO_TRG_INFORMATION_OUT => cts_rdo_rx.trg_information,
+ RDO_TRG_NUMBER_OUT => cts_rdo_rx.trg_number,
--Data from CTS in
RDO_TRG_STATUSBITS_IN => cts_rdo_trg_status_bits_cts,
RDO_DATA_IN => cts_rdo_data,
RDO_ADDITIONAL_DATA => cts_rdo_additional_data,
RDO_ADDITIONAL_WRITE => cts_rdo_additional_write,
RDO_ADDITIONAL_FINISHED => cts_rdo_additional_finished,
-
-- Slow Control --------------------------------------------------------------------
- COMMON_STAT_REGS => open,
- COMMON_CTRL_REGS => common_ctrl_reg,
- ONEWIRE => TEMPSENS,
- ONEWIRE_MONITOR_IN => open,
- MY_ADDRESS_OUT => timer.network_address,
- UNIQUE_ID_OUT => timer.uid,
- TIMER_TICKS_OUT(0) => timer.tick_us,
- TIMER_TICKS_OUT(1) => timer.tick_ms,
- TEMPERATURE_OUT => timer.temperature,
- EXTERNAL_SEND_RESET => reset_via_gbe,
-
- REGIO_ADDR_OUT => ctrlbus_rx.addr,
- REGIO_READ_ENABLE_OUT => ctrlbus_rx.read,
- REGIO_WRITE_ENABLE_OUT => ctrlbus_rx.write,
- REGIO_DATA_OUT => ctrlbus_rx.data,
- REGIO_DATA_IN => ctrlbus_tx.data,
- REGIO_DATAREADY_IN => rdack,
- REGIO_NO_MORE_DATA_IN => ctrlbus_tx.nack,
- REGIO_WRITE_ACK_IN => wrack,
- REGIO_UNKNOWN_ADDR_IN => ctrlbus_tx.unknown,
- REGIO_TIMEOUT_OUT => ctrlbus_rx.timeout,
-
+ COMMON_STAT_REGS => open,
+ COMMON_CTRL_REGS => common_ctrl_reg,
+ ONEWIRE => TEMPSENS,
+ ONEWIRE_MONITOR_IN => open,
+ MY_ADDRESS_OUT => timer.network_address,
+ UNIQUE_ID_OUT => timer.uid,
+ TIMER_TICKS_OUT(0) => timer.tick_us,
+ TIMER_TICKS_OUT(1) => timer.tick_ms,
+ TEMPERATURE_OUT => timer.temperature,
+ EXTERNAL_SEND_RESET => reset_via_gbe,
+ --
+ REGIO_ADDR_OUT => ctrlbus_rx.addr,
+ REGIO_READ_ENABLE_OUT => ctrlbus_rx.read,
+ REGIO_WRITE_ENABLE_OUT => ctrlbus_rx.write,
+ REGIO_DATA_OUT => ctrlbus_rx.data,
+ REGIO_DATA_IN => ctrlbus_tx.data,
+ REGIO_DATAREADY_IN => rdack,
+ REGIO_NO_MORE_DATA_IN => ctrlbus_tx.nack,
+ REGIO_WRITE_ACK_IN => wrack,
+ REGIO_UNKNOWN_ADDR_IN => ctrlbus_tx.unknown,
+ REGIO_TIMEOUT_OUT => ctrlbus_rx.timeout,
--Gbe Sctrl Input
- GSC_INIT_DATAREADY_IN => gsc_init_dataready,
- GSC_INIT_DATA_IN => gsc_init_data,
- GSC_INIT_PACKET_NUM_IN => gsc_init_packet_num,
- GSC_INIT_READ_OUT => gsc_init_read,
- GSC_REPLY_DATAREADY_OUT => gsc_reply_dataready,
- GSC_REPLY_DATA_OUT => gsc_reply_data,
- GSC_REPLY_PACKET_NUM_OUT => gsc_reply_packet_num,
- GSC_REPLY_READ_IN => gsc_reply_read,
- GSC_BUSY_OUT => gsc_busy,
-
+ GSC_INIT_DATAREADY_IN => gsc_init_dataready,
+ GSC_INIT_DATA_IN => gsc_init_data,
+ GSC_INIT_PACKET_NUM_IN => gsc_init_packet_num,
+ GSC_INIT_READ_OUT => gsc_init_read,
+ GSC_REPLY_DATAREADY_OUT => gsc_reply_dataready,
+ GSC_REPLY_DATA_OUT => gsc_reply_data,
+ GSC_REPLY_PACKET_NUM_OUT => gsc_reply_packet_num,
+ GSC_REPLY_READ_IN => gsc_reply_read,
+ GSC_BUSY_OUT => gsc_busy,
--status and control ports
- HUB_STAT_CHANNEL => open,
- HUB_STAT_GEN => open,
- MPLEX_CTRL => (others => '0'),
- MPLEX_STAT => open,
- STAT_REGS => open,
- STAT_CTRL_REGS => open,
-
+ HUB_STAT_CHANNEL => open,
+ HUB_STAT_GEN => open,
+ MPLEX_CTRL => (others => '0'),
+ MPLEX_STAT => open,
+ STAT_REGS => open,
+ STAT_CTRL_REGS => open,
--Fixed status and control ports
- STAT_DEBUG => open,
- CTRL_DEBUG => (others => '0')
- );
+ STAT_DEBUG => open,
+ CTRL_DEBUG => (others => '0')
+ );
gen_addition_ports : for i in 0 to cts_rdo_additional_ports-1 generate
cts_rdo_additional_data(31 + i*32 downto 32*i) <= cts_rdo_additional(i).data;
cts_rdo_additional_write(i) <= cts_rdo_additional(i).data_write;
cts_rdo_additional_finished(i) <= cts_rdo_additional(i).data_finished;
-
end generate;
gen_media_record : for i in 0 to INTERFACE_NUM-1 generate
---------------------------------------------------------------------------
-- CTS
---------------------------------------------------------------------------
- THE_CTS : CTS
- generic map (
- EXTERNAL_TRIGGER_ID => ETM_ID, -- fill in trigger logic enumeration id of external trigger logic
- PLATTFORM => 1+USE_RJADAPT, --TRB3sc+KEL+RJ45
- OUTPUT_MULTIPLEXERS => CTS_OUTPUT_MULTIPLEXERS,
- ADDON_GROUPS => 1,
- ADDON_GROUP_UPPER => (32-USE_RJADAPT*12+3, others => 0)
- )
- port map (
- CLK => clk_sys,
- RESET => reset_i,
-
- TRIGGER_BUSY_OUT => trigger_busy_i,
- TIME_REFERENCE_OUT => cts_trigger_out,
-
- ADDON_TRIGGERS_IN => cts_addon_triggers_in,
- ADDON_GROUP_ACTIVITY_OUT => open,
- ADDON_GROUP_SELECTED_OUT => open,
-
- EXT_TRIGGER_IN => cts_ext_trigger,
- EXT_STATUS_IN => cts_ext_status,
- EXT_CONTROL_OUT => cts_ext_control,
- EXT_HEADER_BITS_IN => cts_ext_header,
- EXT_FORCE_TRIGGER_INFO_IN => (others => '0'),
-
- PERIPH_TRIGGER_IN => (others => '0'),
-
- OUTPUT_MULTIPLEXERS_OUT => open,
-
- CTS_TRG_SEND_OUT => cts_trg_send,
- CTS_TRG_TYPE_OUT => cts_trg_type,
- CTS_TRG_NUMBER_OUT => cts_trg_number,
- CTS_TRG_INFORMATION_OUT => cts_trg_information,
- CTS_TRG_RND_CODE_OUT => cts_trg_code,
- CTS_TRG_STATUS_BITS_IN => cts_trg_status_bits,
- CTS_TRG_BUSY_IN => cts_trg_busy,
-
- CTS_IPU_SEND_OUT => cts_ipu_send,
- CTS_IPU_TYPE_OUT => cts_ipu_type,
- CTS_IPU_NUMBER_OUT => cts_ipu_number,
- CTS_IPU_INFORMATION_OUT => cts_ipu_information,
- CTS_IPU_RND_CODE_OUT => cts_ipu_code,
- CTS_IPU_STATUS_BITS_IN => cts_ipu_status_bits,
- CTS_IPU_BUSY_IN => cts_ipu_busy,
-
- CTS_REGIO_ADDR_IN => buscts_rx.addr,
- CTS_REGIO_DATA_IN => buscts_rx.data,
- CTS_REGIO_READ_ENABLE_IN => buscts_rx.read,
- CTS_REGIO_WRITE_ENABLE_IN => buscts_rx.write,
- CTS_REGIO_DATA_OUT => buscts_tx.data,
- CTS_REGIO_DATAREADY_OUT => buscts_tx.rack,
- CTS_REGIO_WRITE_ACK_OUT => buscts_tx.wack,
- CTS_REGIO_UNKNOWN_ADDR_OUT => buscts_tx.unknown,
-
- LVL1_TRG_DATA_VALID_IN => cts_rdo_rx.data_valid,
- LVL1_VALID_TIMING_TRG_IN => cts_rdo_rx.valid_timing_trg,
- LVL1_VALID_NOTIMING_TRG_IN => cts_rdo_rx.valid_notiming_trg,
- LVL1_INVALID_TRG_IN => cts_rdo_rx.invalid_trg,
-
- FEE_TRG_STATUSBITS_OUT => cts_rdo_trg_status_bits_cts,
- FEE_DATA_OUT => cts_rdo_data,
- FEE_DATA_WRITE_OUT => cts_rdo_write,
- FEE_DATA_FINISHED_OUT => cts_rdo_finished
- );
-
-gen_inputs_kel : if USE_RJADAPT = 0 generate
- cts_addon_triggers_in(1 downto 0) <= SPARE_IN(1 downto 0);
- cts_addon_triggers_in(33 downto 2) <= INP(31 downto 0);
- cts_addon_triggers_in(35 downto 34) <= trigger_gen_outputs_i when rising_edge(clk_sys);
-end generate;
-gen_inputs_rj : if USE_RJADAPT = 1 generate
- cts_addon_triggers_in(1 downto 0) <= SPARE_IN(1 downto 0);
- cts_addon_triggers_in(21 downto 2) <= INP(19 downto 0);
- cts_addon_triggers_in(23 downto 22) <= trigger_gen_outputs_i when rising_edge(clk_sys);
-end generate;
+ THE_CTS : CTS
+ generic map (
+ EXTERNAL_TRIGGER_ID => ETM_ID, -- fill in trigger logic enumeration id of external trigger logic
+ PLATTFORM => 1+USE_RJADAPT, --TRB3sc+KEL+RJ45
+ OUTPUT_MULTIPLEXERS => CTS_OUTPUT_MULTIPLEXERS,
+ ADDON_GROUPS => 1,
+ ADDON_GROUP_UPPER => (32-USE_RJADAPT*12+3, others => 0)
+ )
+ port map (
+ CLK => clk_sys,
+ RESET => reset_i,
+ --
+ TRIGGER_BUSY_OUT => trigger_busy_i,
+ TIME_REFERENCE_OUT => cts_trigger_out,
+ --
+ ADDON_TRIGGERS_IN => cts_addon_triggers_in,
+ ADDON_GROUP_ACTIVITY_OUT => open,
+ ADDON_GROUP_SELECTED_OUT => open,
+ --
+ EXT_TRIGGER_IN => cts_ext_trigger,
+ EXT_STATUS_IN => cts_ext_status,
+ EXT_CONTROL_OUT => cts_ext_control,
+ EXT_HEADER_BITS_IN => cts_ext_header,
+ EXT_FORCE_TRIGGER_INFO_IN => (others => '0'),
+ --
+ PERIPH_TRIGGER_IN => (others => '0'),
+ --
+ OUTPUT_MULTIPLEXERS_OUT => open,
+ --
+ CTS_TRG_SEND_OUT => cts_trg_send,
+ CTS_TRG_TYPE_OUT => cts_trg_type,
+ CTS_TRG_NUMBER_OUT => cts_trg_number,
+ CTS_TRG_INFORMATION_OUT => cts_trg_information,
+ CTS_TRG_RND_CODE_OUT => cts_trg_code,
+ CTS_TRG_STATUS_BITS_IN => cts_trg_status_bits,
+ CTS_TRG_BUSY_IN => cts_trg_busy,
+ --
+ CTS_IPU_SEND_OUT => cts_ipu_send,
+ CTS_IPU_TYPE_OUT => cts_ipu_type,
+ CTS_IPU_NUMBER_OUT => cts_ipu_number,
+ CTS_IPU_INFORMATION_OUT => cts_ipu_information,
+ CTS_IPU_RND_CODE_OUT => cts_ipu_code,
+ CTS_IPU_STATUS_BITS_IN => cts_ipu_status_bits,
+ CTS_IPU_BUSY_IN => cts_ipu_busy,
+ --
+ CTS_REGIO_ADDR_IN => buscts_rx.addr,
+ CTS_REGIO_DATA_IN => buscts_rx.data,
+ CTS_REGIO_READ_ENABLE_IN => buscts_rx.read,
+ CTS_REGIO_WRITE_ENABLE_IN => buscts_rx.write,
+ CTS_REGIO_DATA_OUT => buscts_tx.data,
+ CTS_REGIO_DATAREADY_OUT => buscts_tx.rack,
+ CTS_REGIO_WRITE_ACK_OUT => buscts_tx.wack,
+ CTS_REGIO_UNKNOWN_ADDR_OUT => buscts_tx.unknown,
+ --
+ LVL1_TRG_DATA_VALID_IN => cts_rdo_rx.data_valid,
+ LVL1_VALID_TIMING_TRG_IN => cts_rdo_rx.valid_timing_trg,
+ LVL1_VALID_NOTIMING_TRG_IN => cts_rdo_rx.valid_notiming_trg,
+ LVL1_INVALID_TRG_IN => cts_rdo_rx.invalid_trg,
+ --
+ FEE_TRG_STATUSBITS_OUT => cts_rdo_trg_status_bits_cts,
+ FEE_DATA_OUT => cts_rdo_data,
+ FEE_DATA_WRITE_OUT => cts_rdo_write,
+ FEE_DATA_FINISHED_OUT => cts_rdo_finished
+ );
+
+ gen_inputs_kel : if USE_RJADAPT = 0 generate
+ cts_addon_triggers_in(1 downto 0) <= SPARE_IN(1 downto 0);
+ cts_addon_triggers_in(33 downto 2) <= INP(31 downto 0);
+ cts_addon_triggers_in(35 downto 34) <= trigger_gen_outputs_i when rising_edge(clk_sys);
+ end generate;
+ gen_inputs_rj : if USE_RJADAPT = 1 generate
+ cts_addon_triggers_in(1 downto 0) <= SPARE_IN(1 downto 0);
+ cts_addon_triggers_in(21 downto 2) <= INP(19 downto 0);
+ cts_addon_triggers_in(23 downto 22) <= trigger_gen_outputs_i when rising_edge(clk_sys);
+ end generate;
buscts_tx.nack <= '0';
buscts_tx.ack <= '0';
----------------------------------------------------------------------------
--- Add timestamp generator
----------------------------------------------------------------------------
--- GEN_TIMESTAMP : if INCLUDE_TIMESTAMP_GENERATOR = c_YES generate
--- THE_TIMESTAMP : entity work.timestamp_generator
--- port map(
--- CLK => clk_sys,
--- RESET_IN => reset_i,
---
--- TIMER_CLOCK_IN => KEL(20),
--- TIMER_RESET_IN => KEL(21),
---
--- TRIGGER_IN => cts_trigger_out,
--- BUSRDO_RX => cts_rdo_rx,
--- BUSRDO_TX => cts_rdo_additional(0)
--- );
--- end generate;
---
--- assert not(INCLUDE_ETM = c_YES and INCLUDE_TIMESTAMP_GENERATOR = c_YES) report "Timestamp generator and ETM can not be implemented at the same time (TODO: fix this)" severity failure;
---
---------------------------------------------------------------------------
-- MBS receiver
---------------------------------------------------------------------------
-
-- MBS Module
gen_mbs_vulom_as_etm : if ETM_CHOICE = ETM_CHOICE_MBS_VULOM and INCLUDE_ETM = c_YES generate
THE_MBS : entity work.mbs_vulom_recv
port map (
- CLK => clk_sys,
- RESET_IN => reset_i,
-
- MBS_IN => INP(0),
- CLK_200 => clk_full,
-
- TRG_ASYNC_OUT => mbs_async_out, --TODO MBS async connect to TDC
- TRG_SYNC_OUT => cts_ext_trigger,
-
- TRIGGER_IN => cts_rdo_rx.data_valid,
- TRG_NUMBER_IN => cts_trg_number,
- TRG_CODE_IN => cts_trg_code,
- TIMING_TRG_IN => cts_trigger_out,
-
- DATA_OUT => cts_rdo_additional(0).data,
- WRITE_OUT => cts_rdo_additional(0).data_write,
- FINISHED_OUT => cts_rdo_additional(0).data_finished,
- STATUSBIT_OUT => cts_rdo_additional(0).statusbits,
-
+ CLK => clk_sys,
+ RESET_IN => reset_i,
+ --
+ MBS_IN => INP(0),
+ CLK_200 => clk_full,
+ --
+ TRG_ASYNC_OUT => mbs_async_out, --TODO MBS async connect to TDC
+ TRG_SYNC_OUT => cts_ext_trigger,
+ --
+ TRIGGER_IN => cts_rdo_rx.data_valid,
+ TRG_NUMBER_IN => cts_trg_number,
+ TRG_CODE_IN => cts_trg_code,
+ TIMING_TRG_IN => cts_trigger_out,
+ --
+ DATA_OUT => cts_rdo_additional(0).data,
+ WRITE_OUT => cts_rdo_additional(0).data_write,
+ FINISHED_OUT => cts_rdo_additional(0).data_finished,
+ STATUSBIT_OUT => cts_rdo_additional(0).statusbits,
+ --
CONTROL_REG_IN => cts_ext_control,
STATUS_REG_OUT => cts_ext_status,
HEADER_REG_OUT => cts_ext_header,
-
- DEBUG => cts_ext_debug
- );
+ --
+ DEBUG => cts_ext_debug
+ );
end generate;
PORT_ADDRESSES => (0 => x"d000", 1 => x"d300", 2 => x"b000", 3 => x"b200", 4 => x"b400", 5 => x"8100", 6 => x"8300", 7 => x"a000", 8 => x"c000", others => x"0000"),
PORT_ADDR_MASK => (0 => 12, 1 => 1, 2 => 9, 3 => 9, 4 => 9, 5 => 8, 6 => 8, 7 => 11, 8 => 12, others => 0),
PORT_MASK_ENABLE => 1
- )
+ )
port map(
- CLK => clk_sys,
- RESET => reset_i,
-
- REGIO_RX => handlerbus_rx,
- REGIO_TX => ctrlbus_tx,
-
- BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED
- BUS_RX(1) => bustc_rx, --Clock switch
- BUS_RX(2) => bussci1_rx, --SCI Serdes
- BUS_RX(3) => bussci2_rx,
- BUS_RX(4) => bussci3_rx,
- BUS_RX(5) => busgbeip_rx,
- BUS_RX(6) => busgbereg_rx,
- BUS_RX(7) => buscts_rx,
- BUS_RX(8) => bustdc_rx,
- BUS_TX(0) => bustools_tx,
- BUS_TX(1) => bustc_tx,
- BUS_TX(2) => bussci1_tx,
- BUS_TX(3) => bussci2_tx,
- BUS_TX(4) => bussci3_tx,
- BUS_TX(5) => busgbeip_tx,
- BUS_TX(6) => busgbereg_tx,
- BUS_TX(7) => buscts_tx,
- BUS_TX(8) => bustdc_tx,
+ CLK => clk_sys,
+ RESET => reset_i,
+ --
+ REGIO_RX => handlerbus_rx,
+ REGIO_TX => ctrlbus_tx,
+ --
+ BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED
+ BUS_RX(1) => bustc_rx, --Clock switch
+ BUS_RX(2) => bussci1_rx, --SCI Serdes
+ BUS_RX(3) => bussci2_rx,
+ BUS_RX(4) => bussci3_rx,
+ BUS_RX(5) => busgbeip_rx,
+ BUS_RX(6) => busgbereg_rx,
+ BUS_RX(7) => buscts_rx,
+ BUS_RX(8) => bustdc_rx,
+ BUS_TX(0) => bustools_tx,
+ BUS_TX(1) => bustc_tx,
+ BUS_TX(2) => bussci1_tx,
+ BUS_TX(3) => bussci2_tx,
+ BUS_TX(4) => bussci3_tx,
+ BUS_TX(5) => busgbeip_tx,
+ BUS_TX(6) => busgbereg_tx,
+ BUS_TX(7) => buscts_tx,
+ BUS_TX(8) => bustdc_tx,
STAT_DEBUG => open
- );
+ );
handlerbus_rx <= ctrlbus_rx when bus_master_active = '0' else bus_master_out;
---------------------------------------------------------------------------
THE_TOOLS: entity work.trb3sc_tools
port map(
- CLK => clk_sys,
- RESET => reset_i,
-
+ CLK => clk_sys,
+ RESET => reset_i,
--Flash & Reload
- FLASH_CS => FLASH_CS,
- FLASH_CLK => FLASH_CLK,
- FLASH_IN => FLASH_OUT,
- FLASH_OUT => FLASH_IN,
- PROGRAMN => PROGRAMN,
- REBOOT_IN => do_reboot_i,
+ FLASH_CS => FLASH_CS,
+ FLASH_CLK => FLASH_CLK,
+ FLASH_IN => FLASH_OUT,
+ FLASH_OUT => FLASH_IN,
+ PROGRAMN => PROGRAMN,
+ REBOOT_IN => do_reboot_i,
--SPI
- SPI_CS_OUT => spi_cs,
- SPI_MOSI_OUT=> spi_mosi,
- SPI_MISO_IN => spi_miso,
- SPI_CLK_OUT => spi_clk,
+ SPI_CS_OUT => spi_cs,
+ SPI_MOSI_OUT => spi_mosi,
+ SPI_MISO_IN => spi_miso,
+ SPI_CLK_OUT => spi_clk,
--Header
- HEADER_IO => HDR_IO,
+ HEADER_IO => HDR_IO,
--LCD
- LCD_DATA_IN => open,
+ LCD_DATA_IN => open,
--ADC
- ADC_CS => ADC_CS,
- ADC_MOSI => ADC_DIN,
- ADC_MISO => ADC_DOUT,
- ADC_CLK => ADC_CLK,
+ ADC_CS => ADC_CS,
+ ADC_MOSI => ADC_DIN,
+ ADC_MISO => ADC_DOUT,
+ ADC_CLK => ADC_CLK,
--Trigger & Monitor
- MONITOR_INPUTS => monitor_inputs_i,
- TRIG_GEN_INPUTS => monitor_inputs_i,
- TRIG_GEN_OUTPUTS => trigger_gen_outputs_i,
+ MONITOR_INPUTS => monitor_inputs_i,
+ TRIG_GEN_INPUTS => monitor_inputs_i,
+ TRIG_GEN_OUTPUTS => trigger_gen_outputs_i,
--SED
- SED_ERROR_OUT => sed_error_i,
+ SED_ERROR_OUT => sed_error_i,
--Slowcontrol
- BUS_RX => bustools_rx,
- BUS_TX => bustools_tx,
+ BUS_RX => bustools_rx,
+ BUS_TX => bustools_tx,
--Control master for default settings
- BUS_MASTER_IN => ctrlbus_tx,
- BUS_MASTER_OUT => bus_master_out,
+ BUS_MASTER_IN => ctrlbus_tx,
+ BUS_MASTER_OUT => bus_master_out,
BUS_MASTER_ACTIVE => bus_master_active,
- DEBUG_OUT => open
- );
+ DEBUG_OUT => open
+ );
-monitor_inputs_i <= cts_addon_triggers_in; --INP;
+ monitor_inputs_i <= cts_addon_triggers_in; --INP;
-gen_reboot_no_gbe : if INCLUDE_GBE = c_NO generate
- do_reboot_i <= common_ctrl_reg(15);
-end generate;
-gen_reboot_with_gbe : if INCLUDE_GBE = c_YES generate
- do_reboot_i <= common_ctrl_reg(15) or reboot_from_gbe;
-end generate;
+ gen_reboot_no_gbe : if INCLUDE_GBE = c_NO generate
+ do_reboot_i <= common_ctrl_reg(15);
+ end generate;
+ gen_reboot_with_gbe : if INCLUDE_GBE = c_YES generate
+ do_reboot_i <= common_ctrl_reg(15) or reboot_from_gbe;
+ end generate;
---------------------------------------------------------------------------
-- Switches
PCSSW_EQ <= x"0";
PCSSW_PE <= x"F";
-
---------------------------------------------------------------------------
-- I/O
---------------------------------------------------------------------------
-gen_SPI : if USE_RJADAPT = 0 generate
- spi_miso(5 downto 4) <= DAC_IN_SDI(6 downto 5);
- DAC_OUT_SCK(6 downto 5) <= spi_clk(5 downto 4);
- DAC_OUT_CS(6 downto 5) <= spi_cs(5 downto 4);
- DAC_OUT_SDO(6 downto 5) <= spi_mosi(5 downto 4);
- spi_miso(3 downto 0) <= (others => '0');
- spi_miso(15 downto 7) <= (others => '0');
-end generate;
+ gen_SPI : if USE_RJADAPT = 0 generate
+ spi_miso(5 downto 4) <= DAC_IN_SDI(6 downto 5);
+ DAC_OUT_SCK(6 downto 5) <= spi_clk(5 downto 4);
+ DAC_OUT_CS(6 downto 5) <= spi_cs(5 downto 4);
+ DAC_OUT_SDO(6 downto 5) <= spi_mosi(5 downto 4);
+ spi_miso(3 downto 0) <= (others => '0');
+ spi_miso(15 downto 7) <= (others => '0');
+ end generate;
-gen_reftime_out : if USE_RJADAPT = 1 generate
- REFOUT <= (others => cts_trigger_out);
-end generate;
+ gen_reftime_out : if USE_RJADAPT = 1 generate
+ REFOUT <= (others => cts_trigger_out);
+ end generate;
RJ_IO(0) <= cts_trigger_out;
LED_YELLOW <= debug_clock_reset(2);
-gen_leds_addon : if USE_ADDON = c_YES generate
- gen_hub_leds : for i in 1 to 8 generate
- LED_HUB_LINKOK(i) <= not med2int(i-1).stat_op(9);
- LED_HUB_TX(i) <= not (med2int(i-1).stat_op(10) or not med2int(i-1).stat_op(9));
- LED_HUB_RX(i) <= not (med2int(i-1).stat_op(11));
+ gen_leds_addon : if USE_ADDON = c_YES generate
+ gen_hub_leds : for i in 1 to 8 generate
+ LED_HUB_LINKOK(i) <= not med2int(i-1).stat_op(9);
+ LED_HUB_TX(i) <= not (med2int(i-1).stat_op(10) or not med2int(i-1).stat_op(9));
+ LED_HUB_RX(i) <= not (med2int(i-1).stat_op(11));
+ end generate;
+ LED_SFP_GREEN(1) <= '1';
+ LED_SFP_RED(1) <= '1';
end generate;
- LED_SFP_GREEN(1) <= '1';
- LED_SFP_RED(1) <= '1';
-end generate;
--- LED_HUB_LINKOK(8) <= not med2int(7).stat_op(9) when INCLUDE_GBE = 0 else
--- '1';
--- LED_HUB_TX(8) <= not (med2int(7).stat_op(10) or not med2int(7).stat_op(9)) when INCLUDE_GBE = 0 else
--- '1';
--- LED_HUB_RX(8) <= not (med2int(7).stat_op(11)) when INCLUDE_GBE = 0 else
---
LED_SFP_GREEN(0) <= --not med2int(8).stat_op(9) when INCLUDE_GBE = 0 else
'1';
LED_SFP_RED(0) <= --not (med2int(8).stat_op(10) or med2int(8).stat_op(11) or not med2int(8).stat_op(9)) when INCLUDE_GBE = 0 else
'1';
-gen_leds_addon : if USE_ADDON = c_NO generate
- LED_SFP_GREEN(1) <= not med2int(0).stat_op(9) when USE_BACKPLANE = 0 else
+ gen_leds_addon : if USE_ADDON = c_NO generate
+ LED_SFP_GREEN(1) <= not med2int(0).stat_op(9) when USE_BACKPLANE = 0 else
'1';
- LED_SFP_RED(1) <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11) or not med2int(0).stat_op(9)) when USE_BACKPLANE = 0 else
+ LED_SFP_RED(1) <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11) or not med2int(0).stat_op(9)) when USE_BACKPLANE = 0 else
'1';
-end generate;
--- LED_WHITE(0) <= not med2int(10).stat_op(9) when INCLUDE_GBE = 0 and USE_BACKPLANE = 1 else
--- not med2int(8).stat_op(9) when INCLUDE_GBE = 1 and USE_BACKPLANE = 1 else
--- '1';
--- LED_WHITE(1) <= not (med2int(10).stat_op(10) or med2int(10).stat_op(11) or not med2int(10).stat_op(9)) when INCLUDE_GBE = 0 and USE_BACKPLANE = 1 else
--- not (med2int(8).stat_op(10) or med2int(8).stat_op(11) or not med2int(8).stat_op(9)) when INCLUDE_GBE = 1 and USE_BACKPLANE = 1 else
--- '1';
+ end generate;
-------------------------------------------------------------------------------
-- TDC
-------------------------------------------------------------------------------
- THE_TDC : entity work.TDC_record
- generic map (
- CHANNEL_NUMBER => NUM_TDC_CHANNELS, -- Number of TDC channels per module
- STATUS_REG_NR => 21, -- Number of status regs
- DEBUG => c_YES,
- SIMULATION => c_NO)
- port map (
- RESET => reset_i,
- CLK_TDC => clk_full_osc,
- CLK_READOUT => clk_sys, -- Clock for the readout
- REFERENCE_TIME => cts_trigger_out, -- Reference time input
- HIT_IN => hit_in_i(NUM_TDC_CHANNELS-1 downto 1), -- Channel start signals
- HIT_CAL_IN => clk_cal, -- Hits for calibrating the TDC
- -- Trigger signals from handler
- BUSRDO_RX => cts_rdo_rx,
- BUSRDO_TX => cts_rdo_additional(INCLUDE_TIMESTAMP_GENERATOR + INCLUDE_ETM),
- -- Slow control bus
- BUS_RX => bustdc_rx,
- BUS_TX => bustdc_tx,
- -- Dubug signals
- INFO_IN => timer,
- LOGIC_ANALYSER_OUT => open
- );
-
- -- For single edge measurements
- gen_single : if DOUBLE_EDGE_TYPE = 0 or DOUBLE_EDGE_TYPE = 1 or DOUBLE_EDGE_TYPE = 3 generate
- hit_in_i(NUM_TDC_CHANNELS-1 downto 1) <= INP(NUM_TDC_CHANNELS-2 downto 0);
- end generate;
+-- THE_TDC : entity work.TDC_record
+-- generic map (
+-- CHANNEL_NUMBER => NUM_TDC_CHANNELS, -- Number of TDC channels per module
+-- STATUS_REG_NR => 21, -- Number of status regs
+-- DEBUG => c_YES,
+-- SIMULATION => c_NO
+-- )
+-- port map (
+-- RESET => reset_i,
+-- CLK_TDC => clk_full_osc,
+-- CLK_READOUT => clk_sys, -- Clock for the readout
+-- REFERENCE_TIME => cts_trigger_out, -- Reference time input
+-- HIT_IN => hit_in_i(NUM_TDC_CHANNELS-1 downto 1), -- Channel start signals
+-- HIT_CAL_IN => clk_cal, -- Hits for calibrating the TDC
+-- -- Trigger signals from handler
+-- BUSRDO_RX => cts_rdo_rx,
+-- BUSRDO_TX => cts_rdo_additional(INCLUDE_TIMESTAMP_GENERATOR + INCLUDE_ETM),
+-- -- Slow control bus
+-- BUS_RX => bustdc_rx,
+-- BUS_TX => bustdc_tx,
+-- -- Dubug signals
+-- INFO_IN => timer,
+-- LOGIC_ANALYSER_OUT => open
+-- );
+--
+-- -- For single edge measurements
+-- gen_single : if DOUBLE_EDGE_TYPE = 0 or DOUBLE_EDGE_TYPE = 1 or DOUBLE_EDGE_TYPE = 3 generate
+-- hit_in_i(NUM_TDC_CHANNELS-1 downto 1) <= INP(NUM_TDC_CHANNELS-2 downto 0);
+-- end generate;
end architecture;
-
-
-
------------------------------------------------------------------------------
--design options: backplane or front SFP, with or without GBE
- constant USE_BACKPLANE : integer := c_NO;
- constant INCLUDE_GBE : integer := c_YES;
+ constant USE_BACKPLANE : integer := c_YES;
+ constant INCLUDE_GBE : integer := c_NO;
- constant FPGA_TYPE : integer := 5; --3: ECP3, 5: ECP5
+--We want an ECP3
+ constant FPGA_TYPE : integer := 3; --3: ECP3, 5: ECP5
--Runs with 120 MHz instead of 100 MHz
constant USE_120_MHZ : integer := c_NO;
--Address settings
constant INIT_ADDRESS : std_logic_vector := x"F3CD";
-
-
constant INCLUDE_UART : integer := c_YES;
constant INCLUDE_SPI : integer := c_YES;
constant INCLUDE_LCD : integer := c_NO;
--- /dev/null
+TOPNAME => "trb3sc_hub",
+lm_license_file_for_synplify => "27000\@lxcad04.gsi.de",
+lm_license_file_for_par => "1702\@hadeb05.gsi.de",
+lattice_path => '/opt/lattice/diamond/3.12',
+synplify_path => '/opt/synplicity/R-2020.09-SP1',
+synplify_command => "/opt/synplicity/R-2020.09-SP1/bin/synplify_premier",
+
+nodelist_file => 'nodelist.txt',
+#pinout_file => '',
+par_options => '../par.p2t',
+
+include_TDC => 0,
+include_GBE => 0,
+
+firefox_open => 0,
+twr_number_of_errors => 20,
+no_ltxt2ptxt => 0, #if there is no serdes being used
+
--- /dev/null
+// nodes file for parallel place&route
+
+[hades66]
+system = linux
+corenum = 24
+ENV = /home/compile/bin/diamond_env
+workdir = /home/compile/vhdl/dirich/dirich/workdir
+
-w
--i 15
-l 5
--n 1
--y
-s 12
--t 32
+-t 32 # seed setting here!
-c 1
-e 2
-#-g guidefile.ncd
-#-m nodelist.txt
-# -w
-# -i 6
-# -l 5
-# -n 1
-# -t 1
-# -s 1
-# -c 0
-# -e 0
+-i 15
+-y
+-exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=
+#General PAR Command Line Options
+# -w With this option, any files generated will overwrite existing files
+# (e.g., any .par, .pad files).
+# -y Adds the Delay Summary Report in the .par file and creates the delay
+# file (in .dly format) at the end of the par run.
+#
+#PAR Placement Command Line Options
+# -l Specifies the effort level of the design from 1 (simplest designs)
+# to 5 (most complex designs).
+# -m Multi-tasking option. Controlled by the compile.pl script.
+# -n Sets the number of iterations performed at the effort level
+# specified by the -l option. Controlled by the compile.pl script.
+# -s Save the number of best results for this run.
+# -t Start placement at the specified cost table. Default is 1.
+#
+#PAR Routing Command Line Options
+# -c Run number of cost-based cleanup passes of the router.
+# -e Run number of delay-based cleanup passes of the router on
+# completely-routed designs only.
+# -i Run a maximum number of passes, stopping earlier only if the routing
+# goes to 100 percent completion and all constraints are met.
#
--exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1
+#PAR Explorer Command Line Options
+# parCDP Enable the congestion-driven placement (CDP) algorithm. CDP is
+# compatible with all Lattice FPGA device families; however, most
+# benefit has been demonstrated with benchmarks targeted to ECP5,
+# LatticeECP2/M, LatticeECP3, and LatticeXP2 device families.
+# parCDR Enable the congestion-driven router (CDR) algorithm.
+# Congestion-driven options like parCDR and parCDP can improve
+# performance given a design with multiple congestion “hotspots.” The
+# Layer > Congestion option of the Design Planner Floorplan View can
+# help visualize routing congestion. Large congested areas may prevent
+# the options from finding a successful solution.
+# CDR is compatible with all Lattice FPGA device families however most
+# benefit has been demonstrated with benchmarks targeted to ECP5,
+# LatticeECP2/M,LatticeECP3, and LatticeXP2 device families.
+# paruseNBR NBR Router or Negotiation-based routing option. Supports all
+# FPGA device families except LatticeXP and MachXO.
+# When turned on, an alternate routing engine from the traditional
+# Rip-up-based routing selection (RBR) is used. This involves an
+# iterative routing algorithm that routes connections to achieve
+# minimum delay cost. It does so by computing the demand on each
+# routing resource and applying cost values per node. It will
+# complete when an optimal solution is arrived at or the number of
+# iterations is reached.
+# parPathBased Path-based placement option. Path-based timing driven
+# placement will yield better performance and more
+# predictable results in many cases.
+# parHold Additional hold time correction option. This option
+# forces the router to automatically insert extra wires to compensate for the
+# hold time violation.
+# parHoldLimit This option allows you to set a limit on the number of
+# hold time violations to be processed by the auto hold time correction option
+# parHold.
+# parPlcInLimit Cannot find in the online help
+# parPlcInNeighborSize Cannot find in the online help
+
jspc29 / trb3sc.git / commitdiff