library work;
use work.trb_net_std.all;
use work.trb_net_components.all;
-
use work.trb_net_gbe_components.all;
+use work.med_sync_define_RS.all;
entity gbe_med_interface_5G is
generic (
signal sd_rx_cv_error, sd_rx_cv_error_q : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
signal tx_power, rx_power : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
signal los, signal_detected : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- signal rx_cdr_lol : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- signal tx_pll_lol, quad_rst : std_logic;
- signal tx_pcs_rst, rx_pcs_rst, rx_serdes_rst : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
signal rx_clk_en : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
signal tx_clk_en : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
signal operational_rate : std_logic_vector(NUMBER_OF_GBE_LINKS * 2 - 1 downto 0);
signal synced_rst, ff : std_logic;
signal fifo_eof_q, fifo_eof_qq, fifo_eof_qqq, fifo_eof_qqqq : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+
+ signal link_rx_ready : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal rx_los_low : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal rx_cdr_lol : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal rst_dual : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal rx_pcs_rst : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal rx_pcs_rst_q : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal rx_serdes_rst : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal rx_serdes_rst_q : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal tx_pcs_rst : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal link_tx_ready : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal pll_lol : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal init_dual : std_logic;
+
+ signal debug : std_logic_vector(255 downto 0);
begin
+ --------------------------------------------------------------------
+ --------------------------------------------------------------------
+-- debug(255 downto 0) <= (others => '0');
+ DEBUG_OUT <= debug;
+ --------------------------------------------------------------------
+ --------------------------------------------------------------------
+
+ init_dual <= not GSR_N;
rx_power <= "1111";
tx_power <= "1111";
gbe_serdes: entity serdes_gbe
port map(
- hdinp => SD_RXD_P_IN(i),
+ -- external I/Os
+ hdinp => SD_RXD_P_IN(i),
hdinn => SD_RXD_N_IN(i),
hdoutp => SD_TXD_P_OUT(i),
hdoutn => SD_TXD_N_OUT(i),
+ -- clocks
pll_refclki => CLK_125_IN,
rxrefclk => CLK_125_IN,
- txi_clk => CLK_125_IN, -- REALLY?
+ txi_clk => sd_tx_clk(i), -- REALLY?
tx_pclk => sd_tx_clk(i), -- TO BE IMPLEMENTED
rx_pclk => sd_rx_clk(i), -- recovered RX clock
+ -- TX channel
txdata => sd_tx_data_q( (i + 1) * 8 - 1 downto i * 8),
tx_k => sd_tx_kcntl_q(i downto i),
tx_disp_correct => sd_tx_correct_disp_q(i downto i),
xmit => xmit(i downto i),
+ -- RX channel
rxdata => sd_rx_data( (i + 1) * 8 - 1 downto i * 8),
rx_k => sd_rx_kcntl(i downto i),
rx_disp_err => sd_rx_disp_error(i downto i),
rx_cv_err => sd_rx_cv_error(i downto i),
lsm_status_s => signal_detected(i),
signal_detect_c => '1', -- enable internal LSM
- rsl_disable => '0', -- enable internal reset state machine
- rsl_rst => '0', -- should do
- pll_lol => open, -- BUG --out std_logic;
- rx_cdr_lol_s => open, -- BUG --out std_logic;
- rst_dual_c => '0', -- BUG --in std_logic;
- rx_pcs_rst_c => '0', -- BUG --in std_logic;
- rx_serdes_rst_c => '0', -- BUG --in std_logic;
- tx_pcs_rst_c => '0', -- BUG --in std_logic;
+ -- Status signals
+ pll_lol => pll_lol(i),
+ rx_cdr_lol_s => rx_cdr_lol(i),
+ rx_los_low_s => rx_los_low(i),
+ -- Power control
rx_pwrup_c => rx_power(i),
tx_pwrup_c => tx_power(i),
- serdes_pdb => '1', -- DUAL is powered up
+ serdes_pdb => '1', -- DUAL is powered up
+ -- Resets
+ sli_rst => '0', -- soft logic reset (?)
+ rst_dual_c => rst_dual(i),
+ rx_pcs_rst_c => rx_pcs_rst_q(i),
+ rx_serdes_rst_c => rx_serdes_rst_q(i),
+ tx_pcs_rst_c => tx_pcs_rst(i),
serdes_rst_dual_c => '0',
- tx_serdes_rst_c => '0',
- sli_rst => '0', --
- sci_wrdata => (others => '0'), --
- sci_addr => (others => '0'), --
- sci_rddata => open, --
- sci_en_dual => '0', --
- sci_sel_dual => '0', --
- sci_en => '0', --
- sci_sel => '0', --
- sci_rd => '0', --
- sci_wrn => '1', --
- sci_int => open, --
- cyawstn => '1' --
+ tx_serdes_rst_c => '0'
+ );
+
+ rst_dual(i) <= init_dual;
+
+ THE_MAIN_TX_RST: main_tx_reset_RS
+ port map (
+ CLEAR => init_dual,
+ CLK_REF => CLK_125_IN,
+ TX_PLL_LOL_IN => pll_lol(i),
+ TX_CLOCK_AVAIL_IN => '1', -- not needed here
+ TX_PCS_RST_CH_C_OUT => tx_pcs_rst(i),
+ SYNC_TX_QUAD_OUT => open,
+ LINK_TX_READY_OUT => link_tx_ready(i),
+ STATE_OUT => open
+ );
+
+ THE_MAIN_RX_RST: main_rx_reset_RS
+ port map(
+ CLEAR => init_dual,
+ CLK_REF => CLK_125_IN,
+ CDR_LOL_IN => rx_cdr_lol(i),
+ CV_IN => sd_rx_cv_error(i),
+ LSM_IN => signal_detected(i),
+ LOS_IN => rx_los_low(i),
+ WAP_ZERO_IN => '1', -- not used here
+ -- outputs
+ WAP_REQ_OUT => open, -- not used here
+ RX_SERDES_RST_OUT => rx_serdes_rst(i), -- CLK_REF based
+ RX_PCS_RST_OUT => rx_pcs_rst(i), -- CLK_REF based
+ LINK_RX_READY_OUT => link_rx_ready(i), -- CLK_REF based
+ STATE_OUT => open
);
-
+
+ -- reset signals for RX SerDes need to be sync'ed to real RX clock for ECP5
+ SYNC_RST_SIGS: entity work.signal_sync
+ generic map( WIDTH => 2 )
+ port map(
+ RESET => '0',
+ CLK0 => sd_rx_clk(i),
+ CLK1 => sd_rx_clk(i),
+ D_IN(0) => rx_pcs_rst(i),
+ D_IN(1) => rx_serdes_rst(i),
+ D_OUT(0) => rx_pcs_rst_q(i),
+ D_OUT(1) => rx_serdes_rst_q(i)
+ );
+
+ debug(0) <= init_dual;
+ debug(1) <= pll_lol(i);
+ debug(2) <= rx_cdr_lol(i);
+ debug(3) <= rx_los_low(i);
+ debug(4) <= sd_rx_cv_error(i);
+ debug(5) <= signal_detected(i);
+ debug(6) <= tx_pcs_rst(i);
+ debug(7) <= rx_serdes_rst(i);
+ debug(8) <= rx_pcs_rst(i);
+ debug(9) <= link_rx_ready(i);
+ debug(10) <= link_tx_ready(i);
+
-- one register between SGMII and SerDes
SYNC_TX_PROC : process(CLK_125_IN)
begin
SGMII_GBE_PCS : sgmii_gbe_core
port map(
rst_n => synced_rst,
- signal_detect => signal_detected(i),
+ signal_detect => link_rx_ready(i), --signal_detected(i),
gbe_mode => '1',
sgmii_mode => '0',
operational_rate => operational_rate( (i + 1) * 2 - 1 downto (i * 2)),
mr_restart_an => mr_restart_an(i),
mr_adv_ability => mr_adv_ability( (i + 1) * 16 - 1 downto i * 16)
);
-
- MAC_AN_READY_OUT(i) <= an_complete(i);
+ MAC_AN_READY_OUT(i) <= an_complete(i);
+
+ debug(11) <= sd_rx_kcntl_q(i);
+ debug(19 downto 12) <= sd_rx_data_q( (i + 1) * 8 - 1 downto i * 8);
+
+ debug(20) <= sd_tx_kcntl_q(i);
+ debug(28 downto 21) <= sd_tx_data_q( (i + 1) * 8 - 1 downto i * 8);
+
+ debug(29) <= xmit(i);
+ debug(30) <= mr_main_reset(i);
+ debug(31) <= mr_restart_an(i);
+ debug(32) <= mr_page_rx(i);
+ debug(33) <= an_complete(i);
+
u0_rate_resolution : rate_resolution port map(
gbe_mode => '1',
sgmii_mode => '0',
signal cfg_throttle_pause : std_logic_vector(15 downto 0);
signal issue_reboot : std_logic_vector(3 downto 0);
- signal my_ip : std_logic_vector(127 downto 0);
+ signal my_ip : std_logic_vector(127 downto 0);
+ signal debug : std_logic_vector(255 downto 0);
+
begin
+
+ DEBUG_OUT <= debug(127 downto 0);
+
mac_impl_gen : if DO_SIMULATION = 0 generate
mac_0 <= MC_UNIQUE_ID_IN(15 downto 8) & MC_UNIQUE_ID_IN(23 downto 16) & MC_UNIQUE_ID_IN(31 downto 24) & x"0" & MC_UNIQUE_ID_IN(35 downto 32) & x"7ada";
mac_1 <= MC_UNIQUE_ID_IN(15 downto 8) & MC_UNIQUE_ID_IN(23 downto 16) & MC_UNIQUE_ID_IN(31 downto 24) & x"1" & MC_UNIQUE_ID_IN(35 downto 32) & x"7ada";
SD_PRSNT_N_IN => SD_PRSNT_N_IN,
SD_LOS_IN => SD_LOS_IN,
SD_TXDIS_OUT => SD_TXDIS_OUT,
- DEBUG_OUT => open
+ DEBUG_OUT => debug --open
);
end generate physical_impl_gen;
--
GEN_LINK_2 : if (LINKS_ACTIVE(2) = '1') generate
gbe_inst2 : entity work.gbe_logic_wrapper
- generic map(DO_SIMULATION => DO_SIMULATION,
+ generic map(DO_SIMULATION => DO_SIMULATION,
INCLUDE_DEBUG => INCLUDE_DEBUG,
USE_INTERNAL_TRBNET_DUMMY => USE_INTERNAL_TRBNET_DUMMY,
RX_PATH_ENABLE => 1,
MY_MAC_IN => mac_2,
DHCP_DONE_OUT => dhcp_done(2),
MY_IP_OUT => my_ip(95 downto 64),
- MY_TRBNET_ADDRESS_IN => MY_TRBNET_ADDRESS_IN,
- ISSUE_REBOOT_OUT => issue_reboot(2),
+ MY_TRBNET_ADDRESS_IN => MY_TRBNET_ADDRESS_IN,
+ ISSUE_REBOOT_OUT => issue_reboot(2),
MAC_READY_CONF_IN => mac_ready_conf(2),
MAC_RECONF_OUT => mac_reconf(2),
MAC_AN_READY_IN => mac_an_ready(2),
GSR_N => GSR_N,
MY_MAC_IN => mac_0,
DHCP_DONE_OUT => dhcp_done(0),
- MY_IP_OUT => my_ip(31 downto 0),
- MY_TRBNET_ADDRESS_IN => MY_TRBNET_ADDRESS_IN,
- ISSUE_REBOOT_OUT => issue_reboot(0),
+ MY_IP_OUT => my_ip(31 downto 0),
+ MY_TRBNET_ADDRESS_IN => MY_TRBNET_ADDRESS_IN,
+ ISSUE_REBOOT_OUT => issue_reboot(0),
MAC_READY_CONF_IN => mac_ready_conf(0),
MAC_RECONF_OUT => mac_reconf(0),
MAC_AN_READY_IN => mac_an_ready(0),
sum_dropped <= monitor_dropped(4 * 32 - 1 downto 3 * 32) + monitor_dropped(3 * 32 - 1 downto 2 * 32) + monitor_dropped(2 * 32 - 1 downto 1 * 32) + monitor_dropped(1 * 32 - 1 downto 0 * 32);
include_debug_gen : if (INCLUDE_DEBUG = 1) generate
- DEBUG_OUT(63 downto 0) <= monitor_gen_dbg(4 * 64 - 1 downto 3 * 64);
- DEBUG_OUT(127 downto 65) <= (others => '0');
+-- DEBUG_OUT(63 downto 0) <= monitor_gen_dbg(4 * 64 - 1 downto 3 * 64);
+-- DEBUG_OUT(127 downto 65) <= (others => '0');
end generate;
testbench_sim : if DO_SIMULATION = 1 generate
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