*** empty log message ***

diff --git a/rich.tex b/rich.tex
index fb0128e1811b6e361a0b3eb699e49cc40e44ed32..68152693279bbdbb7da85faccef18a907ebba532 100755 (executable)
--- a/rich.tex
+++ b/rich.tex
@@ -23,7 +23,7 @@ preprocessing inside the FPGA (see table \ref{richnormaldataformat}).
 \begin{figure}
        \centering
                \includegraphics[height=0.9\textheight]{sector.png}
-       \caption[RICH Sector Nomenclature]{BlaBlubb}
+       \caption[RICH Sector Layout]{RICH sector frontend numbering}
        \label{fig:richsector}
 \end{figure}
 
@@ -76,7 +76,8 @@ information sent on TRBnet (see table~\ref{richpreprocessingoptions}).
 111 & NC64THR   & $\leq 64$  & normal mode \\
 \hline
 \end{tabularx}
-\caption{RICH preprocessing options}
+\caption{RICH preprocessing options for LVL trigger information. With each 
+trigger a different preprocessing option can be used.}
 \label{richpreprocessingoptions}
 \end{center}
 \end{table}
@@ -242,7 +243,7 @@ register.
 \hline
 \end{tabularx}
 \caption{APV control and status register}
-\label{richadcspi}
+\label{richapvctrl}
 \end{center}
 \end{table}