removed some bugs when data is not read immediately in lvds chain, Jan

diff --git a/trb_net_18_to_16_converter.vhd b/trb_net_18_to_16_converter.vhd
index b43f6a21cf557a59132865560c671068e787c44f..85447e3619800f208e051dd6d5066eabca665f54 100644 (file)
--- a/trb_net_18_to_16_converter.vhd
+++ b/trb_net_18_to_16_converter.vhd
@@ -102,7 +102,7 @@ signal buffer_dbuf16_comb_data_in      : std_logic_vector(7 downto 0);
 signal next_buffer_dbuf16_comb_data_in : std_logic_vector(7 downto 0);
 signal next_buf_D16_READ_OUT, buf_D16_READ_OUT   : std_logic;
 signal D16_packet, next_D16_packet     : std_logic_vector(1 downto 0);
-
+signal last_dbuf18_next_read_out : std_logic;
 
 
 begin
@@ -112,23 +112,32 @@ begin
 -----------------------------------------------------------
 
 
-next_buf_D18_READ_OUT <= dbuf18_next_read_out ;--and not D18_PACKET4;
+
+next_buf_D18_READ_OUT <= dbuf18_next_read_out;--and not D18_PACKET4;
 D18_READ_OUT <= buf_D18_READ_OUT;
   
   D18to16 : process(buffer_dbuf18_comb_data_in, dbuf18_comb_data_in, last_D18_PACKET4,
-                   buf_D18_READ_OUT, D18_DATAREADY_IN, D18_PACKET_NUM_IN, D18_DATA_IN)
+                   buf_D18_READ_OUT, D18_DATAREADY_IN, D18_PACKET_NUM_IN, D18_DATA_IN,
+                   last_dbuf18_next_read_out)
     variable newdata : std_logic;
     begin
+      dbuf18_comb_dataready_in <= '0';
+      next_buffer_dbuf18_comb_data_in <= buffer_dbuf18_comb_data_in;
+      dbuf18_comb_data_in <= dbuf18_comb_data_in;
+      D18_PACKET4 <= '0';
+
+
       if buf_D18_READ_OUT = '1' and D18_DATAREADY_IN = '1' then
         newdata := '1';
       else
         newdata := '0';
       end if;
-      
-      dbuf18_comb_dataready_in <= '0';
-      next_buffer_dbuf18_comb_data_in <= buffer_dbuf18_comb_data_in;
-      dbuf18_comb_data_in <= dbuf18_comb_data_in;
-      D18_PACKET4 <= '0';      
+
+
+      if ((D18_PACKET_NUM_IN /= "00" and newdata = '1') or last_D18_PACKET4 = '1') then
+        dbuf18_comb_dataready_in <= '1';
+      end if;
+
 
       if newdata = '1' and D18_PACKET_NUM_IN /= "00" then
         dbuf18_comb_data_in(7 downto 0) <= D18_DATA_IN(15 downto 8);
@@ -148,11 +157,8 @@ D18_READ_OUT <= buf_D18_READ_OUT;
         dbuf18_comb_data_in(17 downto 16) <= "00";
       end if;
 
-      if (D18_PACKET_NUM_IN /= "00" and newdata = '1') or last_D18_PACKET4 = '1' then
-        dbuf18_comb_dataready_in <= '1';
-      end if;
 
-      if D18_PACKET_NUM_IN = "11" and newdata = '1' then
+      if (D18_PACKET_NUM_IN = "11" and newdata = '1') or (last_D18_PACKET4 = '1' and last_dbuf18_next_read_out = '0') then
         D18_PACKET4 <= '1';
       end if;      
 
@@ -160,22 +166,23 @@ D18_READ_OUT <= buf_D18_READ_OUT;
         next_buffer_dbuf18_comb_data_in <= D18_DATA_IN(7 downto 0);
       end if;
 
+
     end process;
   
-  process(CLK, RESET)
+  process(CLK)
     begin
-      if RESET = '1' then
-        buffer_dbuf18_comb_data_in <= (others => '0');
-        last_D18_PACKET4 <= '0';
-        buf_D18_READ_OUT <= '0';
-      elsif rising_edge(CLK) then
-        buffer_dbuf18_comb_data_in <= next_buffer_dbuf18_comb_data_in;
-        last_D18_PACKET4 <= D18_PACKET4;
-        buf_D18_READ_OUT <= next_buf_D18_READ_OUT;
-      else
-        buffer_dbuf18_comb_data_in <= buffer_dbuf18_comb_data_in;
-        last_D18_PACKET4 <= last_D18_PACKET4;
-        buf_D18_READ_OUT <= buf_D18_READ_OUT;
+      if rising_edge(CLK) then
+        if RESET = '1' then
+          buffer_dbuf18_comb_data_in <= (others => '0');
+          last_D18_PACKET4 <= '0';
+          buf_D18_READ_OUT <= '0';
+          last_dbuf18_next_read_out <= '0';
+        else
+          buffer_dbuf18_comb_data_in <= next_buffer_dbuf18_comb_data_in;
+          last_D18_PACKET4 <= D18_PACKET4;
+          buf_D18_READ_OUT <= next_buf_D18_READ_OUT;
+          last_dbuf18_next_read_out <= dbuf18_next_read_out;
+        end if;
       end if;
     end process; 
 
@@ -188,7 +195,7 @@ D18_READ_OUT <= buf_D18_READ_OUT;
         CLK_EN => CLK_EN,
         COMB_DATAREADY_IN  => dbuf18_comb_dataready_in,
         COMB_next_READ_OUT => dbuf18_next_read_out,
-        COMB_READ_IN       => '1',
+        COMB_READ_IN       => last_dbuf18_next_read_out,
         COMB_DATA_IN       => dbuf18_comb_data_in,
         -- Port to synchronous output.
         SYN_DATAREADY_OUT  => D16_DATAREADY_OUT,

diff --git a/trb_net_55_to_18_converter.vhd b/trb_net_55_to_18_converter.vhd
index 4a745c6eccecf0f0ecb5579a3c46063f57d5f735..6e8490f2eb090ee5d42393509ce8e26a066b0c7d 100644 (file)
--- a/trb_net_55_to_18_converter.vhd
+++ b/trb_net_55_to_18_converter.vhd
@@ -167,6 +167,7 @@ D18_READ_OUT <= buf_D18_READ_OUT;
       next_D55_READ_OUT <= '0';
       next_buf_D55_DATA_IN <= buf_D55_DATA_IN;
       next_dataread55 <= dataread55;
+      
       if(D18_READ_IN = '1' AND buf_D18_DATAREADY_OUT = '1') then
         dataisread := '1';
       else
@@ -201,13 +202,13 @@ D18_READ_OUT <= buf_D18_READ_OUT;
                                   --data available before, now ready to write
           elsif dataisread = '1' and dataread55 = '1' then
             next_dataread55 <= '0';
-            next_D18_DATA_OUT(7 downto 0) <= D55_DATA_IN(55 downto 48);
+            next_D18_DATA_OUT(7 downto 0) <= buf_D55_DATA_IN(55 downto 48);
             next_D18_DATA_OUT(15 downto 8) <= (others => '0');
             next_D18_PACKET_NUM_OUT <= "00";
             next_D18_DATAREADY_OUT <= '1';
             next_D55to18_state <= FIRST;
                                   --no data available
-          else
+          elsif dataread55 = '0' then
             next_buf_D55_DATA_IN(55 downto 0) <= (others => '0');
             next_D55_READ_OUT <= '1';
           end if;
@@ -240,7 +241,7 @@ D18_READ_OUT <= buf_D18_READ_OUT;
 --             next_D18_DATAREADY_OUT <= '0';
             next_D55to18_state <= IDLE;
 --             next_D18_PACKET_NUM_OUT <= "00";
---             next_D55_READ_OUT <= '1';
+--            next_D55_READ_OUT <= '1';
 --           end if;
       end case;
     end process;

diff --git a/trb_net_med_8bit_fast.vhd b/trb_net_med_8bit_fast.vhd
index d618acccbe4e4a13f57f7f11f3642de678351ce8..88a38f4694c698643ba9bdb82637469239cce362 100644 (file)
--- a/trb_net_med_8bit_fast.vhd
+++ b/trb_net_med_8bit_fast.vhd
@@ -550,8 +550,8 @@ RESET_RECV <= RESET or not DCM_LOCKED;
       elsif rising_edge(CLK) then
         send_data_byte1 <= next_send_data_byte1 after 1 ns;
         send_data_byte2 <= next_send_data_byte2 after 1 ns;
-        send_data_byte1_parity <= next_send_data_byte1_parity after 1 ns;        
-        send_data_byte2_parity <= next_send_data_byte2_parity after 1 ns;        
+        send_data_byte1_parity <= next_send_data_byte1_parity after 1 ns;
+        send_data_byte2_parity <= next_send_data_byte2_parity after 1 ns;
         send_dataready <= next_send_dataready after 1 ns;
         send_packet1 <= next_send_packet1 after 1 ns;
       else