--- /dev/null
+--------------------------------------------------------------------------------
+-- This file is owned and controlled by Xilinx and must be used --
+-- solely for design, simulation, implementation and creation of --
+-- design files limited to Xilinx devices or technologies. Use --
+-- with non-Xilinx devices or technologies is expressly prohibited --
+-- and immediately terminates your license. --
+-- --
+-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
+-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
+-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
+-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
+-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
+-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
+-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
+-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
+-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
+-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
+-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
+-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
+-- FOR A PARTICULAR PURPOSE. --
+-- --
+-- Xilinx products are not intended for use in life support --
+-- appliances, devices, or systems. Use in such applications are --
+-- expressly prohibited. --
+-- --
+-- (c) Copyright 1995-2007 Xilinx, Inc. --
+-- All rights reserved. --
+--------------------------------------------------------------------------------
+-- You must compile the wrapper file fifo_18x512_oreg.vhd when simulating
+-- the core, fifo_18x512_oreg. When compiling the wrapper file, be sure to
+-- reference the XilinxCoreLib VHDL simulation library. For detailed
+-- instructions, please refer to the "CORE Generator Help".
+
+-- The synthesis directives "translate_off/translate_on" specified
+-- below are supported by Xilinx, Mentor Graphics and Synplicity
+-- synthesis tools. Ensure they are correct for your synthesis tool(s).
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+-- synthesis translate_off
+Library XilinxCoreLib;
+-- synthesis translate_on
+ENTITY fifo_18x512_oreg IS
+ port (
+ clk: IN std_logic;
+ din: IN std_logic_VECTOR(17 downto 0);
+ prog_full_thresh: IN std_logic_VECTOR(8 downto 0);
+ rd_en: IN std_logic;
+ rst: IN std_logic;
+ wr_en: IN std_logic;
+ data_count: OUT std_logic_VECTOR(8 downto 0);
+ dout: OUT std_logic_VECTOR(17 downto 0);
+ empty: OUT std_logic;
+ full: OUT std_logic;
+ prog_full: OUT std_logic);
+END fifo_18x512_oreg;
+
+ARCHITECTURE fifo_18x512_oreg_a OF fifo_18x512_oreg IS
+-- synthesis translate_off
+component wrapped_fifo_18x512_oreg
+ port (
+ clk: IN std_logic;
+ din: IN std_logic_VECTOR(17 downto 0);
+ prog_full_thresh: IN std_logic_VECTOR(8 downto 0);
+ rd_en: IN std_logic;
+ rst: IN std_logic;
+ wr_en: IN std_logic;
+ data_count: OUT std_logic_VECTOR(8 downto 0);
+ dout: OUT std_logic_VECTOR(17 downto 0);
+ empty: OUT std_logic;
+ full: OUT std_logic;
+ prog_full: OUT std_logic);
+end component;
+
+-- Configuration specification
+ for all : wrapped_fifo_18x512_oreg use entity XilinxCoreLib.fifo_generator_v4_2(behavioral)
+ generic map(
+ c_has_int_clk => 0,
+ c_rd_freq => 1,
+ c_wr_response_latency => 1,
+ c_has_srst => 0,
+ c_has_rd_data_count => 0,
+ c_din_width => 18,
+ c_has_wr_data_count => 0,
+ c_full_flags_rst_val => 1,
+ c_implementation_type => 0,
+ c_family => "virtex4",
+ c_use_embedded_reg => 1,
+ c_has_wr_rst => 0,
+ c_wr_freq => 1,
+ c_use_dout_rst => 0,
+ c_underflow_low => 0,
+ c_has_meminit_file => 0,
+ c_has_overflow => 0,
+ c_preload_latency => 2,
+ c_dout_width => 18,
+ c_rd_depth => 512,
+ c_default_value => "BlankString",
+ c_mif_file_name => "BlankString",
+ c_has_underflow => 0,
+ c_has_rd_rst => 0,
+ c_has_almost_full => 0,
+ c_has_rst => 1,
+ c_data_count_width => 9,
+ c_has_wr_ack => 0,
+ c_use_ecc => 0,
+ c_wr_ack_low => 0,
+ c_common_clock => 1,
+ c_rd_pntr_width => 9,
+ c_use_fwft_data_count => 0,
+ c_has_almost_empty => 0,
+ c_rd_data_count_width => 9,
+ c_enable_rlocs => 0,
+ c_wr_pntr_width => 9,
+ c_overflow_low => 0,
+ c_prog_empty_type => 0,
+ c_optimization_mode => 0,
+ c_wr_data_count_width => 9,
+ c_preload_regs => 1,
+ c_dout_rst_val => "0",
+ c_has_data_count => 1,
+ c_prog_full_thresh_negate_val => 509,
+ c_wr_depth => 512,
+ c_prog_empty_thresh_negate_val => 3,
+ c_prog_empty_thresh_assert_val => 2,
+ c_has_valid => 0,
+ c_init_wr_pntr_val => 0,
+ c_prog_full_thresh_assert_val => 510,
+ c_use_fifo16_flags => 0,
+ c_has_backup => 0,
+ c_valid_low => 0,
+ c_prim_fifo_type => "512x36",
+ c_count_type => 0,
+ c_prog_full_type => 3,
+ c_memory_type => 1);
+-- synthesis translate_on
+BEGIN
+-- synthesis translate_off
+U0 : wrapped_fifo_18x512_oreg
+ port map (
+ clk => clk,
+ din => din,
+ prog_full_thresh => prog_full_thresh,
+ rd_en => rd_en,
+ rst => rst,
+ wr_en => wr_en,
+ data_count => data_count,
+ dout => dout,
+ empty => empty,
+ full => full,
+ prog_full => prog_full);
+-- synthesis translate_on
+
+END fifo_18x512_oreg_a;
+
--- /dev/null
+##############################################################
+#
+# Xilinx Core Generator version J.40
+# Date: Sun Apr 18 18:45:39 2010
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = False
+SET asysymbol = False
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = False
+SET designentry = VHDL
+SET device = xc4vlx40
+SET devicefamily = virtex4
+SET flowvendor = Other
+SET formalverification = False
+SET foundationsym = False
+SET implementationfiletype = Ngc
+SET package = ff668
+SET removerpms = False
+SET simulationfiles = Behavioral
+SET speedgrade = -11
+SET verilogsim = False
+SET vhdlsim = True
+# END Project Options
+# BEGIN Select
+SELECT Fifo_Generator family Xilinx,_Inc. 4.2
+# END Select
+# BEGIN Parameters
+CSET almost_empty_flag=false
+CSET almost_full_flag=false
+CSET component_name=fifo_18x512_oreg
+CSET data_count=true
+CSET data_count_width=9
+CSET dout_reset_value=0
+CSET empty_threshold_assert_value=2
+CSET empty_threshold_negate_value=3
+CSET enable_ecc=false
+CSET enable_int_clk=false
+CSET fifo_implementation=Common_Clock_Block_RAM
+CSET full_flags_reset_value=1
+CSET full_threshold_assert_value=510
+CSET full_threshold_negate_value=509
+CSET input_data_width=18
+CSET input_depth=512
+CSET output_data_width=18
+CSET output_depth=512
+CSET overflow_flag=false
+CSET overflow_sense=Active_High
+CSET performance_options=Standard_FIFO
+CSET programmable_empty_type=No_Programmable_Empty_Threshold
+CSET programmable_full_type=Single_Programmable_Full_Threshold_Input_Port
+CSET read_clock_frequency=1
+CSET read_data_count=false
+CSET read_data_count_width=9
+CSET reset_pin=true
+CSET reset_type=Asynchronous_Reset
+CSET underflow_flag=false
+CSET underflow_sense=Active_High
+CSET use_dout_reset=false
+CSET use_embedded_registers=true
+CSET use_extra_logic=false
+CSET valid_flag=false
+CSET valid_sense=Active_High
+CSET write_acknowledge_flag=false
+CSET write_acknowledge_sense=Active_High
+CSET write_clock_frequency=1
+CSET write_data_count=false
+CSET write_data_count_width=9
+# END Parameters
+GENERATE
+# CRC: 5d90b917
+
--- /dev/null
+--------------------------------------------------------------------------------
+-- This file is owned and controlled by Xilinx and must be used --
+-- solely for design, simulation, implementation and creation of --
+-- design files limited to Xilinx devices or technologies. Use --
+-- with non-Xilinx devices or technologies is expressly prohibited --
+-- and immediately terminates your license. --
+-- --
+-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
+-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
+-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
+-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
+-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
+-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
+-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
+-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
+-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
+-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
+-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
+-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
+-- FOR A PARTICULAR PURPOSE. --
+-- --
+-- Xilinx products are not intended for use in life support --
+-- appliances, devices, or systems. Use in such applications are --
+-- expressly prohibited. --
+-- --
+-- (c) Copyright 1995-2007 Xilinx, Inc. --
+-- All rights reserved. --
+--------------------------------------------------------------------------------
+-- You must compile the wrapper file fifo_36x16k_oreg.vhd when simulating
+-- the core, fifo_36x16k_oreg. When compiling the wrapper file, be sure to
+-- reference the XilinxCoreLib VHDL simulation library. For detailed
+-- instructions, please refer to the "CORE Generator Help".
+
+-- The synthesis directives "translate_off/translate_on" specified
+-- below are supported by Xilinx, Mentor Graphics and Synplicity
+-- synthesis tools. Ensure they are correct for your synthesis tool(s).
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+-- synthesis translate_off
+Library XilinxCoreLib;
+-- synthesis translate_on
+ENTITY fifo_36x16k_oreg IS
+ port (
+ clk: IN std_logic;
+ din: IN std_logic_VECTOR(35 downto 0);
+ prog_full_thresh: IN std_logic_VECTOR(13 downto 0);
+ rd_en: IN std_logic;
+ rst: IN std_logic;
+ wr_en: IN std_logic;
+ almost_full: OUT std_logic;
+ data_count: OUT std_logic_VECTOR(13 downto 0);
+ dout: OUT std_logic_VECTOR(35 downto 0);
+ empty: OUT std_logic;
+ full: OUT std_logic;
+ prog_full: OUT std_logic);
+END fifo_36x16k_oreg;
+
+ARCHITECTURE fifo_36x16k_oreg_a OF fifo_36x16k_oreg IS
+-- synthesis translate_off
+component wrapped_fifo_36x16k_oreg
+ port (
+ clk: IN std_logic;
+ din: IN std_logic_VECTOR(35 downto 0);
+ prog_full_thresh: IN std_logic_VECTOR(13 downto 0);
+ rd_en: IN std_logic;
+ rst: IN std_logic;
+ wr_en: IN std_logic;
+ almost_full: OUT std_logic;
+ data_count: OUT std_logic_VECTOR(13 downto 0);
+ dout: OUT std_logic_VECTOR(35 downto 0);
+ empty: OUT std_logic;
+ full: OUT std_logic;
+ prog_full: OUT std_logic);
+end component;
+
+-- Configuration specification
+ for all : wrapped_fifo_36x16k_oreg use entity XilinxCoreLib.fifo_generator_v4_2(behavioral)
+ generic map(
+ c_has_int_clk => 0,
+ c_rd_freq => 1,
+ c_wr_response_latency => 1,
+ c_has_srst => 0,
+ c_has_rd_data_count => 0,
+ c_din_width => 36,
+ c_has_wr_data_count => 0,
+ c_full_flags_rst_val => 1,
+ c_implementation_type => 0,
+ c_family => "virtex4",
+ c_use_embedded_reg => 1,
+ c_has_wr_rst => 0,
+ c_wr_freq => 1,
+ c_use_dout_rst => 0,
+ c_underflow_low => 0,
+ c_has_meminit_file => 0,
+ c_has_overflow => 0,
+ c_preload_latency => 2,
+ c_dout_width => 36,
+ c_rd_depth => 16384,
+ c_default_value => "BlankString",
+ c_mif_file_name => "BlankString",
+ c_has_underflow => 0,
+ c_has_rd_rst => 0,
+ c_has_almost_full => 1,
+ c_has_rst => 1,
+ c_data_count_width => 14,
+ c_has_wr_ack => 0,
+ c_use_ecc => 0,
+ c_wr_ack_low => 0,
+ c_common_clock => 1,
+ c_rd_pntr_width => 14,
+ c_use_fwft_data_count => 0,
+ c_has_almost_empty => 0,
+ c_rd_data_count_width => 14,
+ c_enable_rlocs => 0,
+ c_wr_pntr_width => 14,
+ c_overflow_low => 0,
+ c_prog_empty_type => 0,
+ c_optimization_mode => 0,
+ c_wr_data_count_width => 14,
+ c_preload_regs => 1,
+ c_dout_rst_val => "0",
+ c_has_data_count => 1,
+ c_prog_full_thresh_negate_val => 16381,
+ c_wr_depth => 16384,
+ c_prog_empty_thresh_negate_val => 3,
+ c_prog_empty_thresh_assert_val => 2,
+ c_has_valid => 0,
+ c_init_wr_pntr_val => 0,
+ c_prog_full_thresh_assert_val => 16382,
+ c_use_fifo16_flags => 0,
+ c_has_backup => 0,
+ c_valid_low => 0,
+ c_prim_fifo_type => "4kx9",
+ c_count_type => 0,
+ c_prog_full_type => 3,
+ c_memory_type => 1);
+-- synthesis translate_on
+BEGIN
+-- synthesis translate_off
+U0 : wrapped_fifo_36x16k_oreg
+ port map (
+ clk => clk,
+ din => din,
+ prog_full_thresh => prog_full_thresh,
+ rd_en => rd_en,
+ rst => rst,
+ wr_en => wr_en,
+ almost_full => almost_full,
+ data_count => data_count,
+ dout => dout,
+ empty => empty,
+ full => full,
+ prog_full => prog_full);
+-- synthesis translate_on
+
+END fifo_36x16k_oreg_a;
+
--- /dev/null
+##############################################################
+#
+# Xilinx Core Generator version J.40
+# Date: Fri Apr 16 21:01:46 2010
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = False
+SET asysymbol = False
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = False
+SET designentry = VHDL
+SET device = xc4vlx40
+SET devicefamily = virtex4
+SET flowvendor = Other
+SET formalverification = False
+SET foundationsym = False
+SET implementationfiletype = Ngc
+SET package = ff668
+SET removerpms = False
+SET simulationfiles = Behavioral
+SET speedgrade = -11
+SET verilogsim = False
+SET vhdlsim = True
+# END Project Options
+# BEGIN Select
+SELECT Fifo_Generator family Xilinx,_Inc. 4.2
+# END Select
+# BEGIN Parameters
+CSET almost_empty_flag=false
+CSET almost_full_flag=true
+CSET component_name=fifo_36x16k_oreg
+CSET data_count=true
+CSET data_count_width=14
+CSET dout_reset_value=0
+CSET empty_threshold_assert_value=2
+CSET empty_threshold_negate_value=3
+CSET enable_ecc=false
+CSET enable_int_clk=false
+CSET fifo_implementation=Common_Clock_Block_RAM
+CSET full_flags_reset_value=1
+CSET full_threshold_assert_value=16382
+CSET full_threshold_negate_value=16381
+CSET input_data_width=36
+CSET input_depth=16384
+CSET output_data_width=36
+CSET output_depth=16384
+CSET overflow_flag=false
+CSET overflow_sense=Active_High
+CSET performance_options=Standard_FIFO
+CSET programmable_empty_type=No_Programmable_Empty_Threshold
+CSET programmable_full_type=Single_Programmable_Full_Threshold_Input_Port
+CSET read_clock_frequency=1
+CSET read_data_count=false
+CSET read_data_count_width=14
+CSET reset_pin=true
+CSET reset_type=Asynchronous_Reset
+CSET underflow_flag=false
+CSET underflow_sense=Active_High
+CSET use_dout_reset=false
+CSET use_embedded_registers=true
+CSET use_extra_logic=false
+CSET valid_flag=false
+CSET valid_sense=Active_High
+CSET write_acknowledge_flag=false
+CSET write_acknowledge_sense=Active_High
+CSET write_clock_frequency=1
+CSET write_data_count=false
+CSET write_data_count_width=14
+# END Parameters
+GENERATE
+# CRC: 4fce8c61
+
--- /dev/null
+--------------------------------------------------------------------------------
+-- This file is owned and controlled by Xilinx and must be used --
+-- solely for design, simulation, implementation and creation of --
+-- design files limited to Xilinx devices or technologies. Use --
+-- with non-Xilinx devices or technologies is expressly prohibited --
+-- and immediately terminates your license. --
+-- --
+-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
+-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
+-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
+-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
+-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
+-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
+-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
+-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
+-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
+-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
+-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
+-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
+-- FOR A PARTICULAR PURPOSE. --
+-- --
+-- Xilinx products are not intended for use in life support --
+-- appliances, devices, or systems. Use in such applications are --
+-- expressly prohibited. --
+-- --
+-- (c) Copyright 1995-2007 Xilinx, Inc. --
+-- All rights reserved. --
+--------------------------------------------------------------------------------
+-- You must compile the wrapper file fifo_36x32k_oreg.vhd when simulating
+-- the core, fifo_36x32k_oreg. When compiling the wrapper file, be sure to
+-- reference the XilinxCoreLib VHDL simulation library. For detailed
+-- instructions, please refer to the "CORE Generator Help".
+
+-- The synthesis directives "translate_off/translate_on" specified
+-- below are supported by Xilinx, Mentor Graphics and Synplicity
+-- synthesis tools. Ensure they are correct for your synthesis tool(s).
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+-- synthesis translate_off
+Library XilinxCoreLib;
+-- synthesis translate_on
+ENTITY fifo_36x32k_oreg IS
+ port (
+ clk: IN std_logic;
+ din: IN std_logic_VECTOR(35 downto 0);
+ prog_full_thresh: IN std_logic_VECTOR(14 downto 0);
+ rd_en: IN std_logic;
+ rst: IN std_logic;
+ wr_en: IN std_logic;
+ data_count: OUT std_logic_VECTOR(14 downto 0);
+ dout: OUT std_logic_VECTOR(35 downto 0);
+ empty: OUT std_logic;
+ full: OUT std_logic;
+ prog_full: OUT std_logic);
+END fifo_36x32k_oreg;
+
+ARCHITECTURE fifo_36x32k_oreg_a OF fifo_36x32k_oreg IS
+-- synthesis translate_off
+component wrapped_fifo_36x32k_oreg
+ port (
+ clk: IN std_logic;
+ din: IN std_logic_VECTOR(35 downto 0);
+ prog_full_thresh: IN std_logic_VECTOR(14 downto 0);
+ rd_en: IN std_logic;
+ rst: IN std_logic;
+ wr_en: IN std_logic;
+ data_count: OUT std_logic_VECTOR(14 downto 0);
+ dout: OUT std_logic_VECTOR(35 downto 0);
+ empty: OUT std_logic;
+ full: OUT std_logic;
+ prog_full: OUT std_logic);
+end component;
+
+-- Configuration specification
+ for all : wrapped_fifo_36x32k_oreg use entity XilinxCoreLib.fifo_generator_v4_2(behavioral)
+ generic map(
+ c_has_int_clk => 0,
+ c_rd_freq => 1,
+ c_wr_response_latency => 1,
+ c_has_srst => 0,
+ c_has_rd_data_count => 0,
+ c_din_width => 36,
+ c_has_wr_data_count => 0,
+ c_full_flags_rst_val => 1,
+ c_implementation_type => 0,
+ c_family => "virtex4",
+ c_use_embedded_reg => 1,
+ c_has_wr_rst => 0,
+ c_wr_freq => 1,
+ c_use_dout_rst => 0,
+ c_underflow_low => 0,
+ c_has_meminit_file => 0,
+ c_has_overflow => 0,
+ c_preload_latency => 2,
+ c_dout_width => 36,
+ c_rd_depth => 32768,
+ c_default_value => "BlankString",
+ c_mif_file_name => "BlankString",
+ c_has_underflow => 0,
+ c_has_rd_rst => 0,
+ c_has_almost_full => 0,
+ c_has_rst => 1,
+ c_data_count_width => 15,
+ c_has_wr_ack => 0,
+ c_use_ecc => 0,
+ c_wr_ack_low => 0,
+ c_common_clock => 1,
+ c_rd_pntr_width => 15,
+ c_use_fwft_data_count => 0,
+ c_has_almost_empty => 0,
+ c_rd_data_count_width => 15,
+ c_enable_rlocs => 0,
+ c_wr_pntr_width => 15,
+ c_overflow_low => 0,
+ c_prog_empty_type => 0,
+ c_optimization_mode => 0,
+ c_wr_data_count_width => 15,
+ c_preload_regs => 1,
+ c_dout_rst_val => "0",
+ c_has_data_count => 1,
+ c_prog_full_thresh_negate_val => 32765,
+ c_wr_depth => 32768,
+ c_prog_empty_thresh_negate_val => 3,
+ c_prog_empty_thresh_assert_val => 2,
+ c_has_valid => 0,
+ c_init_wr_pntr_val => 0,
+ c_prog_full_thresh_assert_val => 32766,
+ c_use_fifo16_flags => 0,
+ c_has_backup => 0,
+ c_valid_low => 0,
+ c_prim_fifo_type => "4kx9",
+ c_count_type => 0,
+ c_prog_full_type => 3,
+ c_memory_type => 1);
+-- synthesis translate_on
+BEGIN
+-- synthesis translate_off
+U0 : wrapped_fifo_36x32k_oreg
+ port map (
+ clk => clk,
+ din => din,
+ prog_full_thresh => prog_full_thresh,
+ rd_en => rd_en,
+ rst => rst,
+ wr_en => wr_en,
+ data_count => data_count,
+ dout => dout,
+ empty => empty,
+ full => full,
+ prog_full => prog_full);
+-- synthesis translate_on
+
+END fifo_36x32k_oreg_a;
+
--- /dev/null
+##############################################################
+#
+# Xilinx Core Generator version J.40
+# Date: Sun Apr 18 19:02:23 2010
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = False
+SET asysymbol = False
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = False
+SET designentry = VHDL
+SET device = xc4vlx40
+SET devicefamily = virtex4
+SET flowvendor = Other
+SET formalverification = False
+SET foundationsym = False
+SET implementationfiletype = Ngc
+SET package = ff668
+SET removerpms = False
+SET simulationfiles = Behavioral
+SET speedgrade = -11
+SET verilogsim = False
+SET vhdlsim = True
+# END Project Options
+# BEGIN Select
+SELECT Fifo_Generator family Xilinx,_Inc. 4.2
+# END Select
+# BEGIN Parameters
+CSET almost_empty_flag=false
+CSET almost_full_flag=false
+CSET component_name=fifo_36x32k_oreg
+CSET data_count=true
+CSET data_count_width=15
+CSET dout_reset_value=0
+CSET empty_threshold_assert_value=2
+CSET empty_threshold_negate_value=3
+CSET enable_ecc=false
+CSET enable_int_clk=false
+CSET fifo_implementation=Common_Clock_Block_RAM
+CSET full_flags_reset_value=1
+CSET full_threshold_assert_value=32766
+CSET full_threshold_negate_value=32765
+CSET input_data_width=36
+CSET input_depth=32768
+CSET output_data_width=36
+CSET output_depth=32768
+CSET overflow_flag=false
+CSET overflow_sense=Active_High
+CSET performance_options=Standard_FIFO
+CSET programmable_empty_type=No_Programmable_Empty_Threshold
+CSET programmable_full_type=Single_Programmable_Full_Threshold_Input_Port
+CSET read_clock_frequency=1
+CSET read_data_count=false
+CSET read_data_count_width=15
+CSET reset_pin=true
+CSET reset_type=Asynchronous_Reset
+CSET underflow_flag=false
+CSET underflow_sense=Active_High
+CSET use_dout_reset=false
+CSET use_embedded_registers=true
+CSET use_extra_logic=false
+CSET valid_flag=false
+CSET valid_sense=Active_High
+CSET write_acknowledge_flag=false
+CSET write_acknowledge_sense=Active_High
+CSET write_clock_frequency=1
+CSET write_data_count=false
+CSET write_data_count_width=15
+# END Parameters
+GENERATE
+# CRC: d96e9549
+
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+
+entity fifo_var_oreg is
+ generic(
+ FIFO_WIDTH : integer range 1 to 64 := 36;
+ FIFO_DEPTH : integer range 1 to 16 := 8
+ );
+ port(
+ Data : in std_logic_vector(FIFO_WIDTH-1 downto 0);
+ Clock : in std_logic;
+ WrEn : in std_logic;
+ RdEn : in std_logic;
+ Reset : in std_logic;
+ AmFullThresh : in std_logic_vector(FIFO_DEPTH-1 downto 0);
+ Q : out std_logic_vector(FIFO_WIDTH-1 downto 0);
+ WCNT : out std_logic_vector(FIFO_DEPTH downto 0);
+ Empty : out std_logic;
+ Full : out std_logic;
+ AlmostFull : out std_logic
+ );
+end entity;
+
+architecture fifo_var_oreg_arch of fifo_var_oreg is
+
+component fifo_18x512_oreg
+ port (
+ clk : in std_logic;
+ din : in std_logic_vector(17 downto 0);
+ prog_full_thresh : in std_logic_vector(8 downto 0);
+ rd_en : in std_logic;
+ rst : in std_logic;
+ wr_en : in std_logic;
+ data_count : out std_logic_vector(8 downto 0);
+ dout : out std_logic_vector(17 downto 0);
+ empty : out std_logic;
+ full : out std_logic;
+ prog_full : out std_logic
+ );
+end component;
+
+component fifo_36x16k_oreg
+ port (
+ clk : in std_logic;
+ din : in std_logic_vector(35 downto 0);
+ prog_full_thresh : in std_logic_vector(13 downto 0);
+ rd_en : in std_logic;
+ rst : in std_logic;
+ wr_en : in std_logic;
+ data_count : out std_logic_vector(13 downto 0);
+ dout : out std_logic_vector(35 downto 0);
+ empty : out std_logic;
+ full : out std_logic;
+ prog_full : out std_logic
+ );
+end component;
+
+component fifo_36x32k_oreg
+ port (
+ clk : in std_logic;
+ din : in std_logic_vector(35 downto 0);
+ prog_full_thresh : in std_logic_vector(14 downto 0);
+ rd_en : in std_logic;
+ rst : in std_logic;
+ wr_en : in std_logic;
+ data_count : out std_logic_vector(14 downto 0);
+ dout : out std_logic_vector(35 downto 0);
+ empty : out std_logic;
+ full : out std_logic;
+ prog_full : out std_logic
+ );
+end component;
+
+begin
+
+ assert (FIFO_DEPTH >= 13 and FIFO_DEPTH <= 14 and FIFO_WIDTH = 36)
+ or (FIFO_DEPTH >= 9 and FIFO_DEPTH <= 9 and FIFO_WIDTH = 18)
+ report "Selected data buffer size not implemented" severity error;
+
+
+
+ gen_36_16k : if FIFO_WIDTH = 36 and FIFO_DEPTH = 14 generate
+ THE_FIFO : fifo_36x16k_oreg
+ port map(
+ din => Data,
+ clk => Clock,
+ wr_en => WrEn,
+ rd_en => RdEn,
+ rst => Reset,
+ prog_full_thresh => AmFullThresh,
+ dout => Q,
+ data_count => WCNT(13 downto 0),
+ empty => Empty,
+ full => Full,
+ prog_full => AlmostFull
+ );
+ end generate;
+
+
+ gen_36_32k : if FIFO_WIDTH = 36 and FIFO_DEPTH = 15 generate
+ THE_FIFO : fifo_36x32k_oreg
+ port map(
+ Data => Data,
+ Clock => Clock,
+ WrEn => WrEn,
+ RdEn => RdEn,
+ Reset => Reset,
+ AmFullThresh => AmFullThresh,
+ Q => Q,
+ WCNT => WCNT(14 downto 0),
+ Empty => Empty,
+ Full => Full,
+ AlmostFull => AlmostFull
+ );
+ end generate;
+
+
+ gen_18_512 : if FIFO_WIDTH = 18 and FIFO_DEPTH = 9 generate
+ THE_FIFO : fifo_18x512_oreg
+ port map(
+ Data => Data,
+ Clock => Clock,
+ WrEn => WrEn,
+ RdEn => RdEn,
+ Reset => Reset,
+ AmFullThresh => AmFullThresh,
+ Q => Q,
+ WCNT => WCNT(8 downto 0),
+ Empty => Empty,
+ Full => Full,
+ AlmostFull => AlmostFull
+ );
+ end generate;
+
+
+
+
+
+
+end architecture;
\ No newline at end of file
jspc29 / trbnet.git / commitdiff