--- /dev/null
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+BLOCK RD_DURING_WR_PATHS ;
+
+#################################################################
+# Basic Settings
+#################################################################
+
+# SYSCONFIG MCCLK_FREQ = 2.5;
+
+# FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
+# FREQUENCY PORT CLK_PCLK_LEFT 200 MHz;
+# FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz;
+# FREQUENCY PORT CLK_GPLL_LEFT 200 MHz;
+
+#################################################################
+# Clock I/O
+#################################################################
+LOCATE COMP "CLK_PCLK_RIGHT" SITE "P21"; #CM1 & terminated
+LOCATE COMP "CLK_PCLK_LEFT" SITE "N5"; #CM3
+LOCATE COMP "CLK_GPLL_RIGHT" SITE "T21"; #CM4
+LOCATE COMP "CLK_GPLL_LEFT" SITE "U6"; #CM6
+LOCATE COMP "CLK_EXTERNAL" SITE "V20"; #CM9
+
+LOCATE COMP "CLK_IN_0" SITE "AC17";
+LOCATE COMP "CLK_IN_2" SITE "N23";
+LOCATE COMP "CLK_IN_5" SITE "C14";
+LOCATE COMP "CLK_IN_7" SITE "Y26";
+LOCATE COMP "CLK_IN_8" SITE "V17";
+
+IOBUF PORT "CLK_PCLK_RIGHT" IO_TYPE=LVDS25 DIFFRESISTOR=OFF;
+IOBUF PORT "CLK_PCLK_LEFT" IO_TYPE=LVDS25 DIFFRESISTOR=100;
+IOBUF PORT "CLK_GPLL_RIGHT" IO_TYPE=LVDS25 DIFFRESISTOR=100;
+IOBUF PORT "CLK_GPLL_LEFT" IO_TYPE=LVDS25 DIFFRESISTOR=100;
+IOBUF PORT "EXTERNAL" IO_TYPE=LVDS25 DIFFRESISTOR=100;
+DEFINE PORT GROUP "CLK_group" "CLK_IN*" ;
+IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 DIFFRESISTOR=100;
+
+#################################################################
+# Clock Manager
+#################################################################
+LOCATE COMP "CLK_MNGR_USER_0" SITE "M23";
+LOCATE COMP "CLK_MNGR_USER_1" SITE "M24";
+LOCATE COMP "CLK_MNGR_USER_2" SITE "L24";
+LOCATE COMP "CLK_MNGR_USER_3" SITE "K25";
+DEFINE PORT GROUP "CLK_MNGR_group" "CLK_MNGR*" ;
+IOBUF GROUP "CLK_MNGR_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=8;
+
+
+
+#################################################################
+# DAC & SPI
+#################################################################
+
+LOCATE COMP "FLASH_CLK" SITE "V24";
+LOCATE COMP "FLASH_CS" SITE "T25";
+LOCATE COMP "FLASH_DIN" SITE "T24";
+LOCATE COMP "FLASH_DOUT" SITE "V21";
+
+DEFINE PORT GROUP "FLASH_group" "FLASH*" ;
+IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE;
+
+LOCATE COMP "PROGRAMN" SITE "A20";
+IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
+
+LOCATE COMP "DAC_SCK" SITE "R1";
+LOCATE COMP "DAC_CS" SITE "R2";
+LOCATE COMP "DAC_SDI" SITE "P1";
+LOCATE COMP "DAC_SDO" SITE "P2";
+
+DEFINE PORT GROUP "DAC_group" "DAC*" ;
+IOBUF GROUP "DAC_group" IO_TYPE=LVCMOS25 PULLMODE=NONE;
+
+
+#################################################################
+# LED
+#################################################################
+
+LOCATE COMP "LED_CLK_GREEN" SITE "P23";
+LOCATE COMP "LED_CLK_RED" SITE "R22";
+LOCATE COMP "LED_GREEN" SITE "K24";
+LOCATE COMP "LED_ORANGE" SITE "J24";
+LOCATE COMP "LED_RED" SITE "J26";
+LOCATE COMP "LED_YELLOW" SITE "K26";
+LOCATE COMP "LED_SFP_GREEN" SITE "W17";
+LOCATE COMP "LED_SFP_RED" SITE "AB23";
+
+DEFINE PORT GROUP "LED_group" "LED*" ;
+IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8;
+
+#################################################################
+# INPUT
+#################################################################
+LOCATE COMP "INPUT_1" SITE "W8";
+LOCATE COMP "INPUT_2" SITE "Y6";
+LOCATE COMP "INPUT_3" SITE "AA7";
+LOCATE COMP "INPUT_4" SITE "AB3";
+LOCATE COMP "INPUT_5" SITE "AE2";
+LOCATE COMP "INPUT_6" SITE "AD4";
+LOCATE COMP "INPUT_7" SITE "AD3";
+LOCATE COMP "INPUT_8" SITE "AD1";
+LOCATE COMP "INPUT_9" SITE "Y5";
+LOCATE COMP "INPUT_10" SITE "AA1";
+LOCATE COMP "INPUT_11" SITE "AC2";
+LOCATE COMP "INPUT_12" SITE "AB1";
+LOCATE COMP "INPUT_13" SITE "W7";
+LOCATE COMP "INPUT_14" SITE "AA3";
+LOCATE COMP "INPUT_15" SITE "Y1";
+LOCATE COMP "INPUT_16" SITE "V6";
+LOCATE COMP "INPUT_17" SITE "W1";
+LOCATE COMP "INPUT_18" SITE "U4";
+LOCATE COMP "INPUT_19" SITE "T1";
+LOCATE COMP "INPUT_20" SITE "R5";
+LOCATE COMP "INPUT_21" SITE "V1";
+LOCATE COMP "INPUT_22" SITE "P4";
+LOCATE COMP "INPUT_23" SITE "T7";
+LOCATE COMP "INPUT_24" SITE "T3";
+LOCATE COMP "INPUT_25" SITE "M1";
+LOCATE COMP "INPUT_26" SITE "M4";
+LOCATE COMP "INPUT_27" SITE "M5";
+LOCATE COMP "INPUT_28" SITE "M3";
+LOCATE COMP "INPUT_29" SITE "L2";
+LOCATE COMP "INPUT_30" SITE "K3";
+LOCATE COMP "INPUT_31" SITE "H1";
+LOCATE COMP "INPUT_32" SITE "H2";
+LOCATE COMP "INPUT_33" SITE "K2";
+LOCATE COMP "INPUT_34" SITE "H4";
+LOCATE COMP "INPUT_35" SITE "H5";
+LOCATE COMP "INPUT_36" SITE "L8";
+LOCATE COMP "INPUT_37" SITE "J4";
+LOCATE COMP "INPUT_38" SITE "D1";
+LOCATE COMP "INPUT_39" SITE "K4";
+LOCATE COMP "INPUT_40" SITE "E1";
+LOCATE COMP "INPUT_41" SITE "E3";
+LOCATE COMP "INPUT_42" SITE "C2";
+LOCATE COMP "INPUT_43" SITE "K8";
+LOCATE COMP "INPUT_44" SITE "G5";
+LOCATE COMP "INPUT_45" SITE "D4";
+LOCATE COMP "INPUT_46" SITE "H6";
+LOCATE COMP "INPUT_47" SITE "C3";
+LOCATE COMP "INPUT_48" SITE "B2";
+LOCATE COMP "INPUT_49" SITE "D6";
+LOCATE COMP "INPUT_50" SITE "B6";
+LOCATE COMP "INPUT_51" SITE "D5";
+LOCATE COMP "INPUT_52" SITE "C5";
+LOCATE COMP "INPUT_53" SITE "A3";
+LOCATE COMP "INPUT_54" SITE "D8";
+LOCATE COMP "INPUT_55" SITE "G7";
+LOCATE COMP "INPUT_56" SITE "F7";
+LOCATE COMP "INPUT_57" SITE "A5";
+LOCATE COMP "INPUT_58" SITE "G8";
+LOCATE COMP "INPUT_59" SITE "E8";
+LOCATE COMP "INPUT_60" SITE "C9";
+LOCATE COMP "INPUT_61" SITE "A8";
+LOCATE COMP "INPUT_62" SITE "F10";
+LOCATE COMP "INPUT_63" SITE "D9";
+LOCATE COMP "INPUT_64" SITE "G10";
+DEFINE PORT GROUP "INPUT_group" "INPUT*" ;
+IOBUF GROUP "INPUT_group" IO_TYPE=LVDS25 DIFFRESISTOR=OFF;
+
+
+
+#################################################################
+# SFP
+#################################################################
+LOCATE COMP "SFP_LOS" SITE "AF23";
+LOCATE COMP "SFP_TXDIS" SITE "AD23";
+LOCATE COMP "SFP_MOD_0" SITE "AC23";
+LOCATE COMP "SFP_MOD_1" SITE "AB20";
+LOCATE COMP "SFP_MOD_2" SITE "AB21";
+DEFINE PORT GROUP "SFP_group" "SFP*" ;
+IOBUF GROUP "SFP_group" IO_TYPE=LVCMOS25 PULLMODE=UP;
+
+
+#################################################################
+# Other I/O
+#################################################################
+LOCATE COMP "SPARE_LINE_0" SITE "E13";
+LOCATE COMP "SPARE_LINE_1" SITE "L21";
+LOCATE COMP "SPARE_LINE_2" SITE "U20";
+DEFINE PORT GROUP "SPARE_LINE_group" "SPARE_LINE*" ;
+IOBUF GROUP "SPARE_LINE_group" IO_TYPE=LVDS25 DIFFRESISTOR=OFF;
+
+LOCATE COMP "LVDS_1" SITE "J23";
+LOCATE COMP "LVDS_2" SITE "G26";
+DEFINE PORT GROUP "LVDS_group" "LVDS*" ;
+IOBUF GROUP "LVDS_group" IO_TYPE=LVDS25 DIFFRESISTOR=100;
+
+LOCATE COMP "TEMPSENS" SITE "K23";
+IOBUF PORT "TEMPSENS" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8;
+
+
+#################################################################
+# Test Connector
+#################################################################
+LOCATE COMP "TEST_LINE_0" SITE "C18";
+LOCATE COMP "TEST_LINE_1" SITE "D18";
+LOCATE COMP "TEST_LINE_2" SITE "F17";
+LOCATE COMP "TEST_LINE_3" SITE "G17";
+LOCATE COMP "TEST_LINE_4" SITE "E19";
+LOCATE COMP "TEST_LINE_5" SITE "E20";
+LOCATE COMP "TEST_LINE_6" SITE "E18";
+LOCATE COMP "TEST_LINE_7" SITE "D17";
+LOCATE COMP "TEST_LINE_8" SITE "B21";
+LOCATE COMP "TEST_LINE_9" SITE "A22";
+LOCATE COMP "TEST_LINE_10" SITE "F19";
+LOCATE COMP "TEST_LINE_11" SITE "F20";
+LOCATE COMP "TEST_LINE_12" SITE "C22";
+LOCATE COMP "TEST_LINE_13" SITE "C21";
+LOCATE COMP "TEST_LINE_14" SITE "G18";
+LOCATE COMP "TEST_LINE_15" SITE "G19";
+
+DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ;
+IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=8;
+
+
--- /dev/null
+\ 2 \r
+*\r
+NOTE Version: PAC-Designer 6.1.0 *\r
+NOTE Copyright (C), 1995-2011, Lattice Semiconductor Corporation. *\r
+NOTE All Rights Reserved *\r
+NOTE DATE CREATED: 6/11/2012 *\r
+NOTE DESIGN NAME: CBMRICH.PAC *\r
+NOTE DEVICE NAME: ispPAC-CLK5410D *\r
+NOTE PIN ASSIGNMENTS *\r
+\r
+\r
+\r
+QF420*\r
+QP64*\r
+G0*\r
+F0*\r
+L00000 110011111111101111111110010111111111111111*\r
+L00042 100011011111010000001111110110000011111111*\r
+L00084 110011011111110000001110101110000001011111*\r
+L00126 100011011111110000001111001110000001011111*\r
+L00168 100011011111010000001111101110000001011111*\r
+L00210 110010011100101000001111100110000000000111*\r
+L00252 100010011111001000001111101110000010000111*\r
+L00294 110010011111001000001111011110000010011111*\r
+L00336 110000011100001000001111111110000010000111*\r
+L00378 100000011111001111111111111111001110011111*\r
+C1D00*\r
+U11111111111111111111111111111111*\r
+\ 3B44B
\ No newline at end of file
--- /dev/null
+<?xml version="1.0"?>\r
+\r
+<PacDesignData>\r
+\r
+<DocFmtVersion>1</DocFmtVersion>\r
+<DeviceType>ispPAC-CLK5410D</DeviceType>\r
+\r
+<CreatedBy>PAC-Designer 6.1.0</CreatedBy>\r
+\r
+<FuseMap>11111111111010010110111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111001111111111110111111111101011001100000111000111111111101000000000000000000000000000000000000000000000001010010110000000000000001000100010001000100010001000100010001111111111111111111110000000000000000000100000100000000100000100100000000100100100000000001111111100001111111111111111111111111111111111111111111111111111111111111111111111111101100100000000000000000000000000000000000000000001111111111111111111111111111111111111111111111111111111111111111000000000000000000000000000000000000000000000000000000000000000000000000011111111111111111111111111111111</FuseMap>\r
+\r
+<SecurityFuse>0</SecurityFuse>\r
+\r
+<SummaryInformation>\r
+<Title></Title>\r
+<Subject></Subject>\r
+<Author>Unknown User</Author>\r
+<Keywords>ispPAC-CLK5410D</Keywords>\r
+<Comments>\r
+<![CDATA[\r
+]]>\r
+</Comments>\r
+</SummaryInformation>\r
+\r
+<GeneralPurposeLogicEnvOption>\r
+ <PACMode>0</PACMode>\r
+ <HDLMode>0</HDLMode>\r
+ <PreferSynthesis>0</PreferSynthesis>\r
+ <PROJName></PROJName>\r
+ <PROJDIR></PROJDIR>\r
+</GeneralPurposeLogicEnvOption>\r
+\r
+<RemoteFileList>\r
+</RemoteFileList>\r
+\r
+<SymbolicSchematicData>\r
+ <Symbol>\r
+ <SymKey>153</SymKey>\r
+ <NameText>Profile 0 Ref Frequency</NameText>\r
+ <Value>100.0000MHz</Value>\r
+ </Symbol>\r
+ <Symbol>\r
+ <SymKey>891</SymKey>\r
+ <NameText>OEw</NameText>\r
+ <Value>0</Value>\r
+ </Symbol>\r
+ <Symbol>\r
+ <SymKey>892</SymKey>\r
+ <NameText>OEx</NameText>\r
+ <Value>0</Value>\r
+ </Symbol>\r
+ <Symbol>\r
+ <SymKey>893</SymKey>\r
+ <NameText>OEy</NameText>\r
+ <Value>0</Value>\r
+ </Symbol>\r
+ <Symbol>\r
+ <SymKey>894</SymKey>\r
+ <NameText>OEz</NameText>\r
+ <Value>0</Value>\r
+ </Symbol>\r
+ <Symbol>\r
+ <SymKey>881</SymKey>\r
+ <NameText>OE0</NameText>\r
+ <Value>1</Value>\r
+ </Symbol>\r
+ <Symbol>\r
+ <SymKey>882</SymKey>\r
+ <NameText>OE1</NameText>\r
+ <Value>0</Value>\r
+ </Symbol>\r
+ <Symbol>\r
+ <SymKey>883</SymKey>\r
+ <NameText>OE2</NameText>\r
+ <Value>1</Value>\r
+ </Symbol>\r
+ <Symbol>\r
+ <SymKey>884</SymKey>\r
+ <NameText>OE3</NameText>\r
+ <Value>0</Value>\r
+ </Symbol>\r
+ <Symbol>\r
+ <SymKey>885</SymKey>\r
+ <NameText>OE4</NameText>\r
+ <Value>0</Value>\r
+ </Symbol>\r
+ <Symbol>\r
+ <SymKey>886</SymKey>\r
+ <NameText>OE5</NameText>\r
+ <Value>1</Value>\r
+ </Symbol>\r
+ <Symbol>\r
+ <SymKey>887</SymKey>\r
+ <NameText>OE6</NameText>\r
+ <Value>0</Value>\r
+ </Symbol>\r
+ <Symbol>\r
+ <SymKey>888</SymKey>\r
+ <NameText>OE7</NameText>\r
+ <Value>1</Value>\r
+ </Symbol>\r
+ <Symbol>\r
+ <SymKey>889</SymKey>\r
+ <NameText>OE8</NameText>\r
+ <Value>1</Value>\r
+ </Symbol>\r
+ <Symbol>\r
+ <SymKey>890</SymKey>\r
+ <NameText>OE9</NameText>\r
+ <Value>0</Value>\r
+ </Symbol>\r
+ <Symbol>\r
+ <SymKey>339</SymKey>\r
+ <NameText>ispCLK Performance Grade</NameText>\r
+ <Value>0</Value>\r
+ </Symbol>\r
+ <Symbol>\r
+ <SymKey>596</SymKey>\r
+ <NameText>ispCLK Feedback Output Pin</NameText>\r
+ <Value>0</Value>\r
+ </Symbol>\r
+</SymbolicSchematicData>\r
+\r
+</PacDesignData>\r
+\r
--- /dev/null
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+BLOCK RD_DURING_WR_PATHS ;
+
+#################################################################
+# Basic Settings
+#################################################################
+
+ SYSCONFIG MCCLK_FREQ = 2.5;
+
+ FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
+ FREQUENCY PORT CLK_PCLK_LEFT 200 MHz;
+ FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz;
+ FREQUENCY PORT CLK_GPLL_LEFT 125 MHz;
+
+#################################################################
+# Clock I/O
+#################################################################
+LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20";
+LOCATE COMP "CLK_PCLK_LEFT" SITE "M4";
+LOCATE COMP "CLK_SERDES_INT_RIGHT" SITE "AC18";
+LOCATE COMP "CLK_SERDES_INT_LEFT" SITE "AC10";
+LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1";
+LOCATE COMP "CLK_GPLL_LEFT" SITE "U25";
+
+DEFINE PORT GROUP "CLK_group" "CLK*" ;
+IOBUF GROUP "CLK_group" IO_TYPE=LVDS25;
+
+
+#################################################################
+# Trigger I/O
+#################################################################
+
+#Trigger from fan-out
+LOCATE COMP "TRIGGER_LEFT" SITE "V3";
+LOCATE COMP "TRIGGER_RIGHT" SITE "N24";
+IOBUF PORT "TRIGGER_RIGHT" IO_TYPE=LVDS25 ;
+IOBUF PORT "TRIGGER_LEFT" IO_TYPE=LVDS25 ;
+
+
+
+
+#################################################################
+# To central FPGA
+#################################################################
+
+LOCATE COMP "FPGA5_COMM_0" SITE "AD4";
+LOCATE COMP "FPGA5_COMM_1" SITE "AE3";
+LOCATE COMP "FPGA5_COMM_2" SITE "AA7";
+LOCATE COMP "FPGA5_COMM_3" SITE "AB7";
+LOCATE COMP "FPGA5_COMM_4" SITE "AD3";
+LOCATE COMP "FPGA5_COMM_5" SITE "AC4";
+LOCATE COMP "FPGA5_COMM_6" SITE "AE2";
+LOCATE COMP "FPGA5_COMM_7" SITE "AF3";
+LOCATE COMP "FPGA5_COMM_8" SITE "AE4";
+LOCATE COMP "FPGA5_COMM_9" SITE "AF4";
+LOCATE COMP "FPGA5_COMM_10" SITE "V10";
+LOCATE COMP "FPGA5_COMM_11" SITE "W10";
+DEFINE PORT GROUP "FPGA_group" "FPGA*" ;
+IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
+
+LOCATE COMP "TEST_LINE_0" SITE "A5";
+LOCATE COMP "TEST_LINE_1" SITE "A6";
+LOCATE COMP "TEST_LINE_2" SITE "G8";
+LOCATE COMP "TEST_LINE_3" SITE "F9";
+LOCATE COMP "TEST_LINE_4" SITE "D9";
+LOCATE COMP "TEST_LINE_5" SITE "D10";
+LOCATE COMP "TEST_LINE_6" SITE "F10";
+LOCATE COMP "TEST_LINE_7" SITE "E10";
+LOCATE COMP "TEST_LINE_8" SITE "A8";
+LOCATE COMP "TEST_LINE_9" SITE "B8";
+LOCATE COMP "TEST_LINE_10" SITE "G10";
+LOCATE COMP "TEST_LINE_11" SITE "G9";
+LOCATE COMP "TEST_LINE_12" SITE "C9";
+LOCATE COMP "TEST_LINE_13" SITE "C10";
+LOCATE COMP "TEST_LINE_14" SITE "H10";
+LOCATE COMP "TEST_LINE_15" SITE "H11";
+DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ;
+IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12;
+
+#################################################################
+# Connection to AddOn
+#################################################################
+
+LOCATE COMP "LED_LINKOK_1" SITE "P1"; #DQLL0_0 #1
+LOCATE COMP "LED_RX_1" SITE "P2"; #DQLL0_1 #3
+LOCATE COMP "LED_TX_1" SITE "T2"; #DQLL0_2 #5
+LOCATE COMP "SFP_MOD0_1" SITE "U3"; #DQLL0_3 #7
+LOCATE COMP "SFP_MOD1_1" SITE "R1"; #DQLL0_4 #9
+LOCATE COMP "SFP_MOD2_1" SITE "R2"; #DQLL0_5 #11
+LOCATE COMP "SFP_RATESEL_1" SITE "N3"; #DQSLL0_T #13
+LOCATE COMP "SFP_TXDIS_1" SITE "P3"; #DQSLL0_C #15
+LOCATE COMP "SFP_LOS_1" SITE "P5"; #DQLL0_6 #17
+LOCATE COMP "SFP_TXFAULT_1" SITE "P6"; #DQLL0_7 #19
+
+LOCATE COMP "LED_LINKOK_2" SITE "N5"; #DQLL0_8 #21
+LOCATE COMP "LED_RX_2" SITE "N6"; #DQLL0_9 #23
+LOCATE COMP "LED_TX_2" SITE "AC2"; #DQLL2_0 #25
+LOCATE COMP "SFP_MOD0_2" SITE "AC3"; #DQLL2_1 #27
+LOCATE COMP "SFP_MOD1_2" SITE "AB1"; #DQLL2_2 #29
+LOCATE COMP "SFP_MOD2_2" SITE "AC1"; #DQLL2_3 #31
+LOCATE COMP "SFP_RATESEL_2" SITE "AA1"; #DQLL2_4 #33
+LOCATE COMP "SFP_TXDIS_2" SITE "AA2"; #DQLL2_5 #35
+LOCATE COMP "SFP_LOS_2" SITE "W7"; #DQLL2_T #37 #should be DQSLL2
+LOCATE COMP "SFP_TXFAULT_2" SITE "W6"; #DQLL2_C #39 #should be DQSLL2
+
+LOCATE COMP "LED_LINKOK_3" SITE "AD1"; #DQLL3_0 #2
+LOCATE COMP "LED_RX_3" SITE "AD2"; #DQLL3_1 #4
+LOCATE COMP "LED_TX_3" SITE "AB5"; #DQLL3_2 #6
+LOCATE COMP "SFP_MOD0_3" SITE "AB6"; #DQLL3_3 #8
+LOCATE COMP "SFP_MOD1_3" SITE "AB3"; #DQLL3_4 #10
+LOCATE COMP "SFP_MOD2_3" SITE "AB4"; #DQLL3_5 #12
+LOCATE COMP "SFP_RATESEL_3" SITE "Y6"; #DQLL3_T #14 #should be DQSLL3
+LOCATE COMP "SFP_TXDIS_3" SITE "Y7"; #DQLL3_C #16 #should be DQSLL3
+LOCATE COMP "SFP_LOS_3" SITE "AA3"; #DQLL3_6 #18
+LOCATE COMP "SFP_TXFAULT_3" SITE "AA4"; #DQLL3_7 #20
+
+LOCATE COMP "LED_LINKOK_4" SITE "W8"; #DQLL3_8 #22
+LOCATE COMP "LED_RX_4" SITE "W9"; #DQLL3_9 #24
+LOCATE COMP "LED_TX_4" SITE "V1"; #DQLL1_0 #26
+LOCATE COMP "SFP_MOD0_4" SITE "U2"; #DQLL1_1 #28
+LOCATE COMP "SFP_MOD1_4" SITE "T1"; #DQLL1_2 #30
+LOCATE COMP "SFP_MOD2_4" SITE "U1"; #DQLL1_3 #32
+LOCATE COMP "SFP_RATESEL_4" SITE "P4"; #DQLL1_4 #34
+LOCATE COMP "SFP_TXDIS_4" SITE "R3"; #DQLL1_5 #36
+LOCATE COMP "SFP_LOS_4" SITE "T3"; #DQSLL1_T #38
+LOCATE COMP "SFP_TXFAULT_4" SITE "R4"; #DQSLL1_C #40
+
+
+
+LOCATE COMP "LED_LINKOK_5" SITE "W23"; #DQLR1_0 #169
+LOCATE COMP "LED_RX_5" SITE "W22"; #DQLR1_1 #171
+LOCATE COMP "LED_TX_5" SITE "AA25"; #DQLR1_2 #173
+LOCATE COMP "SFP_MOD0_5" SITE "Y24"; #DQLR1_3 #175
+LOCATE COMP "SFP_MOD1_5" SITE "AA26"; #DQLR1_4 #177
+LOCATE COMP "SFP_MOD2_5" SITE "AB26"; #DQLR1_5 #179
+LOCATE COMP "SFP_RATESEL_5" SITE "W21"; #DQSLR1_T #181
+LOCATE COMP "SFP_TXDIS_5" SITE "W20"; #DQSLR1_C #183
+LOCATE COMP "SFP_LOS_5" SITE "AA24"; #DQLR1_6 #185
+LOCATE COMP "SFP_TXFAULT_5" SITE "AA23"; #DQLR1_7 #187
+
+LOCATE COMP "LED_LINKOK_6" SITE "R25"; #DQLR2_0 #170
+LOCATE COMP "LED_RX_6" SITE "R26"; #DQLR2_1 #172
+LOCATE COMP "LED_TX_6" SITE "T25"; #DQLR2_2 #174
+LOCATE COMP "SFP_MOD0_6" SITE "T24"; #DQLR2_3 #176
+LOCATE COMP "SFP_MOD1_6" SITE "T26"; #DQLR2_4 #178
+LOCATE COMP "SFP_MOD2_6" SITE "U26"; #DQLR2_5 #180
+LOCATE COMP "SFP_RATESEL_6" SITE "V21"; #DQSLR2_T #182
+LOCATE COMP "SFP_TXDIS_6" SITE "V22"; #DQSLR2_C #184
+LOCATE COMP "SFP_LOS_6" SITE "U24"; #DQLR2_6 #186
+LOCATE COMP "SFP_TXFAULT_6" SITE "V24"; #DQLR2_7 #188
+
+
+DEFINE PORT GROUP "SFP_group" "SFP*" ;
+IOBUF GROUP "SFP_group" IO_TYPE=LVCMOS25 PULLMODE=UP;
+
+
+
+
+#################################################################
+# Additional Lines to AddOn
+#################################################################
+
+#Lines 0/1 are terminated with 100 Ohm, pads available on 0-3
+#all lines are input only
+#line 4/5 go to PLL input
+LOCATE COMP "SPARE_LINE_0" SITE "M25"; #194
+LOCATE COMP "SPARE_LINE_1" SITE "M26"; #196
+LOCATE COMP "SPARE_LINE_2" SITE "W4"; #198
+LOCATE COMP "SPARE_LINE_3" SITE "W5"; #200
+LOCATE COMP "SPARE_LINE_4" SITE "M3"; #DQUL3_8_OUTOFLANE_FPGA__3 #69
+LOCATE COMP "SPARE_LINE_5" SITE "M2"; #DQUL3_9_OUTOFLANE_FPGA__3 #71
+
+#################################################################
+# Flash ROM and Reboot
+#################################################################
+
+LOCATE COMP "FLASH_CLK" SITE "B12";
+LOCATE COMP "FLASH_CS" SITE "E11";
+LOCATE COMP "FLASH_DIN" SITE "E12";
+LOCATE COMP "FLASH_DOUT" SITE "A12";
+
+DEFINE PORT GROUP "FLASH_group" "FLASH*" ;
+IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE;
+
+LOCATE COMP "PROGRAMN" SITE "B11";
+IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
+
+
+#################################################################
+# Misc
+#################################################################
+LOCATE COMP "TEMPSENS" SITE "A13";
+IOBUF PORT "TEMPSENS" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
+
+#coding of FPGA number
+LOCATE COMP "CODE_LINE_1" SITE "AA20";
+LOCATE COMP "CODE_LINE_0" SITE "Y21";
+IOBUF PORT "CODE_LINE_1" IO_TYPE=LVCMOS25 PULLMODE=UP ;
+IOBUF PORT "CODE_LINE_0" IO_TYPE=LVCMOS25 PULLMODE=UP ;
+
+#terminated differential pair to pads
+LOCATE COMP "SUPPL" SITE "C14";
+IOBUF PORT "SUPPL" IO_TYPE=LVDS25 ;
+
+
+#################################################################
+# LED
+#################################################################
+LOCATE COMP "LED_GREEN" SITE "F12";
+LOCATE COMP "LED_ORANGE" SITE "G13";
+LOCATE COMP "LED_RED" SITE "A15";
+LOCATE COMP "LED_YELLOW" SITE "A16";
+DEFINE PORT GROUP "LED_group" "LED*" ;
+IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12;
--- /dev/null
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+BLOCK RD_DURING_WR_PATHS ;
+
+#################################################################
+# Basic Settings
+#################################################################
+
+# SYSCONFIG MCCLK_FREQ = 2.5;
+
+# FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
+# FREQUENCY PORT CLK_PCLK_LEFT 200 MHz;
+# FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz;
+# FREQUENCY PORT CLK_GPLL_LEFT 125 MHz;
+
+
+#################################################################
+# Clock I/O
+#################################################################
+LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20";
+LOCATE COMP "CLK_PCLK_LEFT" SITE "M4";
+LOCATE COMP "CLK_SERDES_INT_RIGHT" SITE "AC18";
+LOCATE COMP "CLK_SERDES_INT_LEFT" SITE "AC10";
+LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1";
+LOCATE COMP "CLK_GPLL_LEFT" SITE "U25";
+
+DEFINE PORT GROUP "CLK_group" "CLK*" ;
+IOBUF GROUP "CLK_group" IO_TYPE=LVDS25;
+
+
+#################################################################
+# Trigger I/O
+#################################################################
+
+#Trigger from fan-out
+LOCATE COMP "TRIGGER_LEFT" SITE "V3";
+LOCATE COMP "TRIGGER_RIGHT" SITE "N24";
+IOBUF PORT "TRIGGER_RIGHT" IO_TYPE=LVDS25 ;
+IOBUF PORT "TRIGGER_LEFT" IO_TYPE=LVDS25 ;
+
+
+
+
+#################################################################
+# To central FPGA
+#################################################################
+
+LOCATE COMP "FPGA5_COMM_0" SITE "AD4";
+LOCATE COMP "FPGA5_COMM_1" SITE "AE3";
+LOCATE COMP "FPGA5_COMM_2" SITE "AA7";
+LOCATE COMP "FPGA5_COMM_3" SITE "AB7";
+LOCATE COMP "FPGA5_COMM_4" SITE "AD3";
+LOCATE COMP "FPGA5_COMM_5" SITE "AC4";
+LOCATE COMP "FPGA5_COMM_6" SITE "AE2";
+LOCATE COMP "FPGA5_COMM_7" SITE "AF3";
+LOCATE COMP "FPGA5_COMM_8" SITE "AE4";
+LOCATE COMP "FPGA5_COMM_9" SITE "AF4";
+LOCATE COMP "FPGA5_COMM_10" SITE "V10";
+LOCATE COMP "FPGA5_COMM_11" SITE "W10";
+DEFINE PORT GROUP "FPGA_group" "FPGA*" ;
+IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
+
+LOCATE COMP "TEST_LINE_0" SITE "A5";
+LOCATE COMP "TEST_LINE_1" SITE "A6";
+LOCATE COMP "TEST_LINE_2" SITE "G8";
+LOCATE COMP "TEST_LINE_3" SITE "F9";
+LOCATE COMP "TEST_LINE_4" SITE "D9";
+LOCATE COMP "TEST_LINE_5" SITE "D10";
+LOCATE COMP "TEST_LINE_6" SITE "F10";
+LOCATE COMP "TEST_LINE_7" SITE "E10";
+LOCATE COMP "TEST_LINE_8" SITE "A8";
+LOCATE COMP "TEST_LINE_9" SITE "B8";
+LOCATE COMP "TEST_LINE_10" SITE "G10";
+LOCATE COMP "TEST_LINE_11" SITE "G9";
+LOCATE COMP "TEST_LINE_12" SITE "C9";
+LOCATE COMP "TEST_LINE_13" SITE "C10";
+LOCATE COMP "TEST_LINE_14" SITE "H10";
+LOCATE COMP "TEST_LINE_15" SITE "H11";
+DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ;
+IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12;
+
+
+
+#################################################################
+# Flash ROM and Reboot
+#################################################################
+
+LOCATE COMP "FLASH_CLK" SITE "B12";
+LOCATE COMP "FLASH_CS" SITE "E11";
+LOCATE COMP "FLASH_DIN" SITE "E12";
+LOCATE COMP "FLASH_DOUT" SITE "A12";
+
+DEFINE PORT GROUP "FLASH_group" "FLASH*" ;
+IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE;
+
+LOCATE COMP "PROGRAMN" SITE "B11";
+IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
+
+
+#################################################################
+# Misc
+#################################################################
+LOCATE COMP "TEMPSENS" SITE "A13";
+IOBUF PORT "TEMPSENS" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
+
+#coding of FPGA number
+LOCATE COMP "CODE_LINE_1" SITE "AA20";
+LOCATE COMP "CODE_LINE_0" SITE "Y21";
+IOBUF PORT "CODE_LINE_1" IO_TYPE=LVCMOS25 PULLMODE=UP ;
+IOBUF PORT "CODE_LINE_0" IO_TYPE=LVCMOS25 PULLMODE=UP ;
+
+#terminated differential pair to pads
+LOCATE COMP "SUPPL" SITE "C14";
+IOBUF PORT "SUPPL" IO_TYPE=LVDS25 ;
+
+
+#################################################################
+# LED
+#################################################################
+LOCATE COMP "LED_GREEN" SITE "F12";
+LOCATE COMP "LED_ORANGE" SITE "G13";
+LOCATE COMP "LED_RED" SITE "A15";
+LOCATE COMP "LED_YELLOW" SITE "A16";
+DEFINE PORT GROUP "LED_group" "LED*" ;
+IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12;
+
+
+
+
+
+
+
+
+
+#################################################################
+# Connection to AddOn
+#################################################################
+#All DQ groups from one bank are grouped.
+#All DQS are inserted in the DQ lines at position 6 and 7
+#DQ 6-9 are shifted to 8-11
+#Order per bank is kept, i.e. adjacent numbers have adjacent pins
+#all DQ blocks are 6+2+4=12 Pins wide, only DQUL3 and DQUR0 are 6+2+2=10.
+#even numbers are positive LVDS line, odd numbers are negative LVDS line
+#DQUL can be switched to 1.8V
+
+ LOCATE COMP "MADC2_FCO" SITE "P1"; #DQLL0_0 #1
+ LOCATE COMP "MADC2_D_1" SITE "T2"; #DQLL0_2 #5
+ LOCATE COMP "MADC2_D_2" SITE "R1"; #DQLL0_4 #9
+ LOCATE COMP "MADC2_DCO" SITE "N3"; #DQSLL0_T #13
+ LOCATE COMP "MADC2_D_3" SITE "P5"; #DQLL0_6 #17
+ LOCATE COMP "MADC2_D_4" SITE "N5"; #DQLL0_8 #21
+
+ LOCATE COMP "MADC2_D_8" SITE "V1"; #DQLL1_0 #26
+ LOCATE COMP "MADC2_D_7" SITE "T1"; #DQLL1_2 #30
+ LOCATE COMP "MADC2_D_5" SITE "P4"; #DQLL1_4 #34
+# LOCATE COMP "DQLL_18" SITE "T3"; #DQSLL1_T #38
+# LOCATE COMP "DQLL_19" SITE "R4"; #DQSLL1_C #40
+ LOCATE COMP "MADC2_D_6" SITE "R5"; #DQLL1_6 #42
+ LOCATE COMP "MADC2_CLK" SITE "T7"; #DQLL1_8 #46
+
+ LOCATE COMP "MADC1_D_6" SITE "AC2"; #DQLL2_0 #25
+ LOCATE COMP "MADC1_D_8" SITE "AB1"; #DQLL2_2 #29
+# LOCATE COMP "DQLL_28" SITE "AA1"; #DQLL2_4 #33
+# LOCATE COMP "DQLL_29" SITE "AA2"; #DQLL2_5 #35
+ LOCATE COMP "MADC1_D_7" SITE "W7"; #DQLL2_T #37 #should be DQSLL2
+ LOCATE COMP "MADC1_D_5" SITE "Y5"; #DQLL2_6 #41
+ LOCATE COMP "MADC1_CLK" SITE "V6"; #DQLL2_8 #45
+
+ LOCATE COMP "MADC1_D_1" SITE "AD1"; #DQLL3_0 #2
+ LOCATE COMP "MADC1_D_2" SITE "AB5"; #DQLL3_2 #6
+ LOCATE COMP "MADC1_D_3" SITE "AB3"; #DQLL3_4 #10
+ LOCATE COMP "MADC1_DCO" SITE "Y6"; #DQLL3_T #14 #should be DQSLL3
+ LOCATE COMP "MADC1_FCO" SITE "AA3"; #DQLL3_6 #18
+ LOCATE COMP "MADC1_D_4" SITE "W8"; #DQLL3_8 #22
+
+ LOCATE COMP "DAC_MUTEB" SITE "AC26"; #DQLR0_0 #129
+ LOCATE COMP "DAC_FSYNC" SITE "AC25"; #DQLR0_1 #131
+ LOCATE COMP "DAC_SCLK" SITE "Y19"; #DQLR0_2 #133
+ LOCATE COMP "DAC_DIN" SITE "Y20"; #DQLR0_3 #135
+ LOCATE COMP "DAC_BPB" SITE "AB24"; #DQLR0_4 #137
+ LOCATE COMP "DAC_RSTB" SITE "AC24"; #DQLR0_5 #139
+ LOCATE COMP "DAC_OSR2" SITE "Y22"; #DQSLR0_T #141
+ LOCATE COMP "DAC_OSR1" SITE "AA22"; #DQSLR0_C #143
+# LOCATE COMP "DQLR_8" SITE "AD24"; #DQLR0_6 #145
+ LOCATE COMP "LEDADDON_LINKOK" SITE "AE24"; #DQLR0_7 #147
+ LOCATE COMP "LEDADDON_RXTX" SITE "AE25"; #DQLR0_8 #149
+ LOCATE COMP "SFP1_RATESEL" SITE "AF24"; #DQLR0_9 #151
+
+ LOCATE COMP "LVDS_IO_10" SITE "W23"; #DQLR1_0 #169
+# LOCATE COMP "LVDS_IO_N_10" SITE "W22"; #DQLR1_1 #171
+ LOCATE COMP "LVDS_INP_4" SITE "AA25"; #DQLR1_2 #173
+# LOCATE COMP "LVDS_INP_N_4" SITE "Y24"; #DQLR1_3 #175
+ LOCATE COMP "LVDS_IO_11" SITE "AA26"; #DQLR1_4 #177
+# LOCATE COMP "LVDS_IO_N_11" SITE "AB26"; #DQLR1_5 #179
+ LOCATE COMP "LVDS_INP_5" SITE "W21"; #DQSLR1_T #181
+# LOCATE COMP "LVDS_INP_N_5" SITE "W20"; #DQSLR1_C #183
+ LOCATE COMP "LVDS_IO_12" SITE "AA24"; #DQLR1_6 #185
+# LOCATE COMP "LVDS_IO_N_12" SITE "AA23"; #DQLR1_7 #187
+ LOCATE COMP "LVDS_INP_6" SITE "AD26"; #DQLR1_8 #189
+# LOCATE COMP "LVDS_INP_N_6" SITE "AD25"; #DQLR1_9 #191
+
+ LOCATE COMP "LVDS_INP_1" SITE "R25"; #DQLR2_0 #170
+# LOCATE COMP "LVDS_INP_N_1" SITE "R26"; #DQLR2_1 #172
+ LOCATE COMP "LVDS_IO_13" SITE "T25"; #DQLR2_2 #174
+# LOCATE COMP "LVDS_IO_N_13" SITE "T24"; #DQLR2_3 #176
+ LOCATE COMP "PWM_DAC_INPUT_1" SITE "T26"; #DQLR2_4 #178
+ LOCATE COMP "PWM_DAC_INPUT_2" SITE "U26"; #DQLR2_5 #180
+ LOCATE COMP "PWM_DAC_INPUT_3" SITE "V21"; #DQSLR2_T #182
+ LOCATE COMP "PWM_DAC_INPUT_4" SITE "V22"; #DQSLR2_C #184
+ LOCATE COMP "LVDS_IO_14" SITE "U24"; #DQLR2_6 #186
+# LOCATE COMP "LVDS_IO_N_14" SITE "V24"; #DQLR2_7 #188
+ LOCATE COMP "LVDS_IO_15" SITE "U23"; #DQLR2_8 #190
+# LOCATE COMP "LVDS_IO_N_15" SITE "U22"; #DQLR2_9 #192
+
+# LOCATE COMP "DQUL_0" SITE "B2"; #DQUL0_0 #74
+# LOCATE COMP "DQUL_1" SITE "B3"; #DQUL0_1 #76
+ LOCATE COMP "LVDS_IO_7" SITE "D4"; #DQUL0_2 #78
+# LOCATE COMP "LVDS_IO_N_7" SITE "E4"; #DQUL0_3 #80
+ LOCATE COMP "LVDS_IO_8" SITE "C3"; #DQUL0_4 #82
+# LOCATE COMP "LVDS_IO_N_8" SITE "D3"; #DQUL0_5 #84
+ LOCATE COMP "LVDS_INP_7" SITE "G5"; #DQSUL0_T #86
+# LOCATE COMP "LVDS_INP_N_7" SITE "G6"; #DQSUL0_C #88
+ LOCATE COMP "LVDS_INP_8" SITE "E3"; #DQUL0_6 #90
+# LOCATE COMP "LVDS_INP_N_8" SITE "F4"; #DQUL0_7 #92
+ LOCATE COMP "LVDS_IO_9" SITE "H6"; #DQUL0_8 #94
+# LOCATE COMP "LVDS_IO_N_9" SITE "J6"; #DQUL0_9 #96
+
+ LOCATE COMP "KONR_ADC_DISCH_1" SITE "G2"; #DQUL1_0 #73
+ LOCATE COMP "KONR_ADC_DISCH_2" SITE "G3"; #DQUL1_1 #75
+ LOCATE COMP "LVDS_IO_2" SITE "F2"; #DQUL1_2 #77
+# LOCATE COMP "LVDS_IO_N_2" SITE "F3"; #DQUL1_3 #79
+# LOCATE COMP "DQUL_16" SITE "C2"; #DQUL1_4 #81
+# LOCATE COMP "DQUL_17" SITE "D2"; #DQUL1_5 #83
+# LOCATE COMP "DQUL_18" SITE "K7"; #DQSUL1_T #85
+# LOCATE COMP "DQUL_19" SITE "K6"; #DQSUL1_C #87
+ LOCATE COMP "WU_RAMP" SITE "H5"; #DQUL1_6 #89
+# LOCATE COMP "DQUL_21" SITE "J5"; #DQUL1_7 #91
+ LOCATE COMP "LVDS_IO_3" SITE "K8"; #DQUL1_8 #93
+# LOCATE COMP "LVDS_IO_N_3" SITE "J7"; #DQUL1_9 #95
+
+# LOCATE COMP "DQUL_24" SITE "K2"; #DQUL2_0 #50
+# LOCATE COMP "DQUL_25" SITE "K1"; #DQUL2_1 #52
+ LOCATE COMP "LVDS_IO_4" SITE "J4"; #DQUL2_2 #54
+# LOCATE COMP "LVDS_IO_N_4" SITE "J3"; #DQUL2_3 #56
+ LOCATE COMP "LVDS_IO_5" SITE "D1"; #DQUL2_4 #58
+# LOCATE COMP "LVDS_IO_N_5" SITE "C1"; #DQUL2_5 #60
+# LOCATE COMP "DQUL_30" SITE "K4"; #DQSUL2_T #62
+# LOCATE COMP "DQUL_31" SITE "K5"; #DQSUL2_C #64
+# LOCATE COMP "DQUL_32" SITE "E1"; #DQUL2_6 #66
+# LOCATE COMP "DQUL_33" SITE "F1"; #DQUL2_7 #68
+ LOCATE COMP "LVDS_IO_6" SITE "L5"; #DQUL2_8 #70
+# LOCATE COMP "LVDS_IO_N_6" SITE "L6"; #DQUL2_9 #72
+
+ LOCATE COMP "KONR_ADC_1" SITE "H2"; #DQUL3_0 #49
+ LOCATE COMP "LVDS_IO_1" SITE "K3"; #DQUL3_2 #53
+# LOCATE COMP "LVDS_IO_N_1" SITE "L3"; #DQUL3_3 #55
+ LOCATE COMP "KONR_ADC_THR_1" SITE "H1"; #DQUL3_4 #57
+ LOCATE COMP "KONR_ADC_N_1" SITE "J1"; #DQUL3_5 #59
+ LOCATE COMP "KONR_ADC_2" SITE "M5"; #DQSUL3_T #61
+# LOCATE COMP "DQUL_43" SITE "M6"; #DQSUL3_C #63
+ LOCATE COMP "KONR_ADC_THR_2" SITE "L2"; #DQUL3_6 #65
+ LOCATE COMP "KONR_ADC_N_2" SITE "L1"; #DQUL3_7 #67
+
+
+LOCA TE COMP "LVDS_IO_16" SITE "J23"; #DQUR0_0 #105
+# LOCATE COMP "LVDS_IO_N_16" SITE "H23"; #DQUR0_1 #107
+LOCA TE COMP "LVDS_IO_17" SITE "G26"; #DQUR0_2 #109
+# LOCATE COMP "LVDS_IO_N_17" SITE "F26"; #DQUR0_3 #111
+ LOCATE COMP "MADC2_SCLK" SITE "H26"; #DQUR0_4 #113
+ LOCATE COMP "MADC2_SDIO" SITE "H25"; #DQUR0_5 #115
+ LOCATE COMP "MADC2_CSB" SITE "F24"; #DQSUR0_T #117
+ LOCATE COMP "MADC2_PDWN" SITE "G24"; #DQSUR0_C #119
+ LOCATE COMP "MADC1_SCLK" SITE "K23"; #DQUR0_6 #121
+ LOCATE COMP "MADC1_SDIO" SITE "K22"; #DQUR0_7 #123
+# LOCATE COMP "MADC1_CSB" SITE "F25"; #DQUR0_8 #125 #input only
+# LOCATE COMP "MADC1_PDWN" SITE "E26"; #DQUR0_9 #127 #input only
+
+# LOCATE COMP "DQUR_10" SITE "H24"; #DQUR1_0 #106
+ LOCATE COMP "LEDADDON_RED" SITE "G25"; #DQUR1_1 #108
+ LOCATE COMP "LEDADDON_GREEN" SITE "L20"; #DQUR1_2 #110
+ LOCATE COMP "LEDADDON_YELLOW" SITE "M21"; #DQUR1_3 #112
+ LOCATE COMP "LEDADDON_ORANGE" SITE "K24"; #DQUR1_4 #114
+ LOCATE COMP "DAC12_SCK" SITE "J24"; #DQUR1_5 #116
+ LOCATE COMP "DAC12_CSB" SITE "M23"; #DQSUR1_T #118
+ LOCATE COMP "DAC12_SDI" SITE "M24"; #DQSUR1_C #120
+ LOCATE COMP "DAC12_SDO" SITE "L24"; #DQUR1_6 #122
+ LOCATE COMP "DAC12_CLRB" SITE "K25"; #DQUR1_7 #124
+ LOCATE COMP "RJ45_LVDS_4" SITE "M22"; #DQUR1_8 #126
+# LOCATE COMP "RJ45_LVDS_N_4" SITE "N21"; #DQUR1_9 #128
+ LOCATE COMP "SFP1_TXFAULT" SITE "J26"; #DQUR2_0 #130
+ LOCATE COMP "SFP1_LOS" SITE "K26"; #DQUR2_1 #132
+ LOCATE COMP "RJ45_LVDS_3" SITE "N23"; #DQUR2_2 #134
+# LOCATE COMP "RJ45_LVDS_N_3" SITE "N22"; #DQUR2_3 #136
+LOCATE C OMP "RJ45_LVDS_2" SITE "K19"; #DQUR2_4 #138
+# LOCATE COMP "RJ45_LVDS_N_2" SITE "L19"; #DQUR2_5 #140
+ LOCATE COMP "SFP1_TXDIS" SITE "P23"; #DQSUR2_T #142
+ LOCATE COMP "SFP1_MOD_0" SITE "R22"; #DQSUR2_C #144
+ LOCATE COMP "SFP1_MOD_1" SITE "L25"; #DQUR2_6 #146
+ LOCATE COMP "SFP1_MOD_2" SITE "L26"; #DQUR2_7 #148
+ LOCATE COMP "RJ45_LVDS_1" SITE "P21"; #DQUR2_8 #150
+# LOCATE COMP "RJ45_LVDS_N_1" SITE "P22"; #DQUR2_9 #152
+
+# DEFINE PORT GROUP "DQ_group" "DQ*" ;
+# IOBUF GROUP "DQ_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN;
+
+#################################################################
+# Additional Lines to AddOn
+#################################################################
+
+#Lines 0/1 are terminated with 100 Ohm, pads available on 0-3
+#all lines are input only
+#line 4/5 go to PLL input
+ LOCATE COMP "LVDS_INP_2" SITE "M25"; #194 --terminated on-board!
+# LOCATE COMP "LVDS_INP_N_2" SITE "M26"; #196
+ LOCATE COMP "LVDS_INP_3" SITE "W4"; #198
+# LOCATE COMP "LVDS_INP_N_3" SITE "W5"; #200
+ LOCATE COMP "MADC2_DCO_OPT" SITE "M3"; #DQUL3_8_OUTOFLANE_FPGA__3 #69
+# LOCATE COMP "SPARE_LINE_5" SITE "M2"; #DQUL3_9_OUTOFLANE_FPGA__3 #71
+
+
\ No newline at end of file
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.trb3_components.all;
+use work.version.all;
+
+
+
+entity trb3_periph is
+ port(
+ --Clocks
+ CLK_GPLL_LEFT : in std_logic; --Clock Manager 1/(2468), 125 MHz
+ CLK_GPLL_RIGHT : in std_logic; --Clock Manager 2/(2468), 200 MHz <-- MAIN CLOCK for FPGA
+ CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
+ CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
+
+ --Trigger
+ TRIGGER_LEFT : in std_logic; --left side trigger input from fan-out
+ TRIGGER_RIGHT : in std_logic; --right side trigger input from fan-out
+
+ --Serdes
+ CLK_SERDES_INT_LEFT : in std_logic; --Clock Manager 1/(1357), off, 125 MHz possible
+ CLK_SERDES_INT_RIGHT : in std_logic; --Clock Manager 2/(1357), 200 MHz, only in case of problems
+ SERDES_INT_TX : out std_logic_vector(3 downto 0);
+ SERDES_INT_RX : in std_logic_vector(3 downto 0);
+ SERDES_ADDON_TX : out std_logic_vector(11 downto 0);
+ SERDES_ADDON_RX : in std_logic_vector(11 downto 0);
+
+ --Inter-FPGA Communication
+ FPGA5_COMM : inout std_logic_vector(11 downto 0);
+ --Bit 0/1 input, serial link RX active
+ --Bit 2/3 output, serial link TX active
+ --others yet undefined
+ --Connection to AddOn
+ MADC1_CLK : out std_logic;
+ MADC1_FCO : in std_logic;
+ MADC1_DCO : in std_logic;
+ MADC1_D : in std_logic_vector(8 downto 1);
+ MADC1_SCLK : out std_logic;
+ MADC1_SDIO : inout std_logic;
+ -- MADC1_CSB : out std_logic; --input only pin...
+ -- MADC1_PDWN : out std_logic; --input only pin...
+
+ MADC2_CLK : out std_logic;
+ MADC2_FCO : in std_logic;
+ MADC2_DCO : in std_logic;
+ -- MADC2_DCO_OPT : in std_logic;
+ MADC2_D : in std_logic_vector(8 downto 1);
+ MADC2_SCLK : out std_logic;
+ MADC2_SDIO : inout std_logic;
+ MADC2_CSB : out std_logic;
+ MADC2_PDWN : out std_logic;
+
+ KONR_ADC : in std_logic_vector(2 downto 1);
+ KONR_ADC_THR : out std_logic_vector(2 downto 1);
+ KONR_ADC_N : out std_logic_vector(2 downto 1);
+ KONR_ADC_DISCH : out std_logic_vector(2 downto 1);
+
+ WU_RAMP : out std_logic;
+
+ LVDS_IO : inout std_logic_vector(17 downto 1);
+ LVDS_INP : inout std_logic_vector( 8 downto 1);
+ RJ45_LVDS : inout std_logic_vector( 4 downto 1);
+
+ PWM_DAC_INPUT : out std_logic_vector(4 downto 1);
+
+ DAC_MUTEB : out std_logic;
+ DAC_FSYNC : out std_logic;
+ DAC_SCLK : out std_logic;
+ DAC_DIN : out std_logic;
+ DAC_BPB : out std_logic;
+ DAC_RSTB : out std_logic;
+ DAC_OSR : inout std_logic_vector(2 downto 1);
+
+ DAC12_SCK : out std_logic;
+ DAC12_CSB : out std_logic;
+ DAC12_SDI : out std_logic;
+ DAC12_SDO : in std_logic;
+ DAC12_CLRB : out std_logic;
+
+ LEDADDON_LINKOK : out std_logic;
+ LEDADDON_RXTX : out std_logic;
+ LEDADDON_RED : out std_logic;
+ LEDADDON_YELLOW : out std_logic;
+ LEDADDON_GREEN : out std_logic;
+ LEDADDON_ORANGE : out std_logic;
+
+ SFP1_RATESEL : out std_logic;
+ SFP1_TXDIS : out std_logic;
+ SFP1_TXFAULT : in std_logic;
+ SFP1_LOS : in std_logic;
+ SFP1_MOD : inout std_logic_vector(2 downto 0);
+
+ --Flash ROM & Reboot
+ FLASH_CLK : out std_logic;
+ FLASH_CS : out std_logic;
+ FLASH_DIN : out std_logic;
+ FLASH_DOUT : in std_logic;
+ PROGRAMN : out std_logic; --reboot FPGA
+
+ --Misc
+ TEMPSENS : inout std_logic; --Temperature Sensor
+ CODE_LINE : in std_logic_vector(1 downto 0);
+ LED_GREEN : out std_logic;
+ LED_ORANGE : out std_logic;
+ LED_RED : out std_logic;
+ LED_YELLOW : out std_logic;
+ SUPPL : in std_logic; --terminated diff pair, PCLK, Pads
+
+ --Test Connectors
+ TEST_LINE : out std_logic_vector(15 downto 0)
+ );
+
+
+ attribute syn_useioff : boolean;
+ --no IO-FF for LEDs relaxes timing constraints
+ attribute syn_useioff of LED_GREEN : signal is false;
+ attribute syn_useioff of LED_ORANGE : signal is false;
+ attribute syn_useioff of LED_RED : signal is false;
+ attribute syn_useioff of LED_YELLOW : signal is false;
+ attribute syn_useioff of LEDADDON_GREEN : signal is false;
+ attribute syn_useioff of LEDADDON_ORANGE : signal is false;
+ attribute syn_useioff of LEDADDON_RED : signal is false;
+ attribute syn_useioff of LEDADDON_YELLOW : signal is false;
+ attribute syn_useioff of LEDADDON_LINKOK : signal is false;
+ attribute syn_useioff of LEDADDON_RXTX : signal is false;
+ attribute syn_useioff of SFP1_RATESEL : signal is false;
+ attribute syn_useioff of SFP1_TXDIS : signal is false;
+ attribute syn_useioff of SFP1_TXFAULT : signal is false;
+ attribute syn_useioff of SFP1_LOS : signal is false;
+ attribute syn_useioff of TEMPSENS : signal is false;
+ attribute syn_useioff of PROGRAMN : signal is false;
+ attribute syn_useioff of CODE_LINE : signal is false;
+ attribute syn_useioff of TRIGGER_LEFT : signal is false;
+ attribute syn_useioff of TRIGGER_RIGHT : signal is false;
+
+ --important signals _with_ IO-FF
+ attribute syn_useioff of FLASH_CLK : signal is true;
+ attribute syn_useioff of FLASH_CS : signal is true;
+ attribute syn_useioff of FLASH_DIN : signal is true;
+ attribute syn_useioff of FLASH_DOUT : signal is true;
+ attribute syn_useioff of FPGA5_COMM : signal is true;
+ attribute syn_useioff of TEST_LINE : signal is true;
+
+
+end entity;
+
+architecture trb3_periph_arch of trb3_periph is
+ --Constants
+ constant REGIO_NUM_STAT_REGS : integer := 2;
+ constant REGIO_NUM_CTRL_REGS : integer := 2;
+
+ attribute syn_keep : boolean;
+ attribute syn_preserve : boolean;
+
+ --Clock / Reset
+ signal clk_100_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL
+ signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL
+ signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic.
+ signal clear_i : std_logic;
+ signal reset_i : std_logic;
+ signal GSR_N : std_logic;
+ attribute syn_keep of GSR_N : signal is true;
+ attribute syn_preserve of GSR_N : signal is true;
+
+ --Media Interface
+ signal med_stat_op : std_logic_vector (1*16-1 downto 0);
+ signal med_ctrl_op : std_logic_vector (1*16-1 downto 0);
+ signal med_stat_debug : std_logic_vector (1*64-1 downto 0);
+ signal med_ctrl_debug : std_logic_vector (1*64-1 downto 0);
+ signal med_data_out : std_logic_vector (1*16-1 downto 0);
+ signal med_packet_num_out : std_logic_vector (1*3-1 downto 0);
+ signal med_dataready_out : std_logic;
+ signal med_read_out : std_logic;
+ signal med_data_in : std_logic_vector (1*16-1 downto 0);
+ signal med_packet_num_in : std_logic_vector (1*3-1 downto 0);
+ signal med_dataready_in : std_logic;
+ signal med_read_in : std_logic;
+
+ --LVL1 channel
+ signal timing_trg_received_i : std_logic;
+ signal trg_data_valid_i : std_logic;
+ signal trg_timing_valid_i : std_logic;
+ signal trg_notiming_valid_i : std_logic;
+ signal trg_invalid_i : std_logic;
+ signal trg_type_i : std_logic_vector(3 downto 0);
+ signal trg_number_i : std_logic_vector(15 downto 0);
+ signal trg_code_i : std_logic_vector(7 downto 0);
+ signal trg_information_i : std_logic_vector(23 downto 0);
+ signal trg_int_number_i : std_logic_vector(15 downto 0);
+ signal trg_multiple_trg_i : std_logic;
+ signal trg_timeout_detected_i: std_logic;
+ signal trg_spurious_trg_i : std_logic;
+ signal trg_missing_tmg_trg_i : std_logic;
+ signal trg_spike_detected_i : std_logic;
+
+ --Data channel
+ signal fee_trg_release_i : std_logic;
+ signal fee_trg_statusbits_i : std_logic_vector(31 downto 0);
+ signal fee_data_i : std_logic_vector(31 downto 0);
+ signal fee_data_write_i : std_logic;
+ signal fee_data_finished_i : std_logic;
+ signal fee_almost_full_i : std_logic;
+
+ --Slow Control channel
+ signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0);
+ signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
+ signal stat_reg : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0);
+ signal ctrl_reg : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0);
+ signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0);
+ signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0);
+ signal stat_reg_strobe : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0);
+ signal ctrl_reg_strobe : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0);
+
+ --RegIO
+ signal my_address : std_logic_vector (15 downto 0);
+ signal regio_addr_out : std_logic_vector (15 downto 0);
+ signal regio_read_enable_out : std_logic;
+ signal regio_write_enable_out : std_logic;
+ signal regio_data_out : std_logic_vector (31 downto 0);
+ signal regio_data_in : std_logic_vector (31 downto 0);
+ signal regio_dataready_in : std_logic;
+ signal regio_no_more_data_in : std_logic;
+ signal regio_write_ack_in : std_logic;
+ signal regio_unknown_addr_in : std_logic;
+ signal regio_timeout_out : std_logic;
+
+ --Timer
+ signal global_time : std_logic_vector(31 downto 0);
+ signal local_time : std_logic_vector(7 downto 0);
+ signal time_since_last_trg : std_logic_vector(31 downto 0);
+ signal timer_ticks : std_logic_vector(1 downto 0);
+
+ --Flash
+ signal spictrl_read_en : std_logic;
+ signal spictrl_write_en : std_logic;
+ signal spictrl_data_in : std_logic_vector(31 downto 0);
+ signal spictrl_addr : std_logic;
+ signal spictrl_data_out : std_logic_vector(31 downto 0);
+ signal spictrl_ack : std_logic;
+ signal spictrl_busy : std_logic;
+ signal spimem_read_en : std_logic;
+ signal spimem_write_en : std_logic;
+ signal spimem_data_in : std_logic_vector(31 downto 0);
+ signal spimem_addr : std_logic_vector(5 downto 0);
+ signal spimem_data_out : std_logic_vector(31 downto 0);
+ signal spimem_ack : std_logic;
+
+ signal spi_bram_addr : std_logic_vector(7 downto 0);
+ signal spi_bram_wr_d : std_logic_vector(7 downto 0);
+ signal spi_bram_rd_d : std_logic_vector(7 downto 0);
+ signal spi_bram_we : std_logic;
+
+
+ --FPGA Test
+ signal time_counter : unsigned(31 downto 0);
+
+
+begin
+---------------------------------------------------------------------------
+-- Reset Generation
+---------------------------------------------------------------------------
+
+ GSR_N <= pll_lock;
+
+ THE_RESET_HANDLER : trb_net_reset_handler
+ generic map(
+ RESET_DELAY => x"FEEE"
+ )
+ port map(
+ CLEAR_IN => '0', -- reset input (high active, async)
+ CLEAR_N_IN => '1', -- reset input (low active, async)
+ CLK_IN => clk_200_i, -- raw master clock, NOT from PLL/DLL!
+ SYSCLK_IN => clk_100_i, -- PLL/DLL remastered clock
+ PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async)
+ RESET_IN => '0', -- general reset signal (SYSCLK)
+ TRB_RESET_IN => med_stat_op(13), -- TRBnet reset signal (SYSCLK)
+ CLEAR_OUT => clear_i, -- async reset out, USE WITH CARE!
+ RESET_OUT => reset_i, -- synchronous reset out (SYSCLK)
+ DEBUG_OUT => open
+ );
+
+
+---------------------------------------------------------------------------
+-- Clock Handling
+---------------------------------------------------------------------------
+
+ THE_MAIN_PLL : pll_in200_out100
+ port map(
+ CLK => CLK_GPLL_RIGHT,
+ CLKOP => clk_100_i,
+ CLKOK => clk_200_i,
+ LOCK => pll_lock
+ );
+
+
+---------------------------------------------------------------------------
+-- The TrbNet media interface (to other FPGA)
+---------------------------------------------------------------------------
+ THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp
+ generic map(
+ SERDES_NUM => 1, --number of serdes in quad
+ EXT_CLOCK => c_NO, --use internal clock
+ USE_200_MHZ => c_YES --run on 200 MHz clock
+ )
+ port map(
+ CLK => clk_200_i,
+ SYSCLK => clk_100_i,
+ RESET => reset_i,
+ CLEAR => clear_i,
+ CLK_EN => '1',
+ --Internal Connection
+ MED_DATA_IN => med_data_out,
+ MED_PACKET_NUM_IN => med_packet_num_out,
+ MED_DATAREADY_IN => med_dataready_out,
+ MED_READ_OUT => med_read_in,
+ MED_DATA_OUT => med_data_in,
+ MED_PACKET_NUM_OUT => med_packet_num_in,
+ MED_DATAREADY_OUT => med_dataready_in,
+ MED_READ_IN => med_read_out,
+ REFCLK2CORE_OUT => open,
+ --SFP Connection
+ SD_RXD_P_IN => SERDES_INT_RX(2),
+ SD_RXD_N_IN => SERDES_INT_RX(3),
+ SD_TXD_P_OUT => SERDES_INT_TX(2),
+ SD_TXD_N_OUT => SERDES_INT_TX(3),
+ SD_REFCLK_P_IN => open,
+ SD_REFCLK_N_IN => open,
+ SD_PRSNT_N_IN => FPGA5_COMM(0),
+ SD_LOS_IN => FPGA5_COMM(0),
+ SD_TXDIS_OUT => FPGA5_COMM(2),
+ -- Status and control port
+ STAT_OP => med_stat_op,
+ CTRL_OP => med_ctrl_op,
+ STAT_DEBUG => med_stat_debug,
+ CTRL_DEBUG => (others => '0')
+ );
+
+---------------------------------------------------------------------------
+-- Endpoint
+---------------------------------------------------------------------------
+ THE_ENDPOINT : trb_net16_endpoint_hades_full_handler
+ generic map(
+ REGIO_NUM_STAT_REGS => REGIO_NUM_STAT_REGS, --4, --16 stat reg
+ REGIO_NUM_CTRL_REGS => REGIO_NUM_CTRL_REGS, --3, --8 cotrol reg
+ ADDRESS_MASK => x"FFFF",
+ BROADCAST_BITMASK => x"FF",
+ BROADCAST_SPECIAL_ADDR => x"45",
+ REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)),
+ REGIO_HARDWARE_VERSION => x"91000001",
+ REGIO_INIT_ADDRESS => x"f300",
+ REGIO_USE_VAR_ENDPOINT_ID => c_YES,
+ CLOCK_FREQUENCY => 125,
+ TIMING_TRIGGER_RAW => c_YES,
+ --Configure data handler
+ DATA_INTERFACE_NUMBER => 1,
+ DATA_BUFFER_DEPTH => 13, --13
+ DATA_BUFFER_WIDTH => 32,
+ DATA_BUFFER_FULL_THRESH => 2**13-800, --2**13-1024
+ TRG_RELEASE_AFTER_DATA => c_YES,
+ HEADER_BUFFER_DEPTH => 9,
+ HEADER_BUFFER_FULL_THRESH => 2**9-16
+ )
+ port map(
+ CLK => clk_100_i,
+ RESET => reset_i,
+ CLK_EN => '1',
+ MED_DATAREADY_OUT => med_dataready_out, -- open, --
+ MED_DATA_OUT => med_data_out, -- open, --
+ MED_PACKET_NUM_OUT => med_packet_num_out, -- open, --
+ MED_READ_IN => med_read_in,
+ MED_DATAREADY_IN => med_dataready_in,
+ MED_DATA_IN => med_data_in,
+ MED_PACKET_NUM_IN => med_packet_num_in,
+ MED_READ_OUT => med_read_out, -- open, --
+ MED_STAT_OP_IN => med_stat_op,
+ MED_CTRL_OP_OUT => med_ctrl_op,
+
+ --Timing trigger in
+ TRG_TIMING_TRG_RECEIVED_IN => timing_trg_received_i,
+ --LVL1 trigger to FEE
+ LVL1_TRG_DATA_VALID_OUT => trg_data_valid_i,
+ LVL1_VALID_TIMING_TRG_OUT => trg_timing_valid_i,
+ LVL1_VALID_NOTIMING_TRG_OUT => trg_notiming_valid_i,
+ LVL1_INVALID_TRG_OUT => trg_invalid_i,
+
+ LVL1_TRG_TYPE_OUT => trg_type_i,
+ LVL1_TRG_NUMBER_OUT => trg_number_i,
+ LVL1_TRG_CODE_OUT => trg_code_i,
+ LVL1_TRG_INFORMATION_OUT => trg_information_i,
+ LVL1_INT_TRG_NUMBER_OUT => trg_int_number_i,
+
+ --Information about trigger handler errors
+ TRG_MULTIPLE_TRG_OUT => trg_multiple_trg_i,
+ TRG_TIMEOUT_DETECTED_OUT => trg_timeout_detected_i,
+ TRG_SPURIOUS_TRG_OUT => trg_spurious_trg_i,
+ TRG_MISSING_TMG_TRG_OUT => trg_missing_tmg_trg_i,
+ TRG_SPIKE_DETECTED_OUT => trg_spike_detected_i,
+
+ --Response from FEE
+ FEE_TRG_RELEASE_IN(0) => fee_trg_release_i,
+ FEE_TRG_STATUSBITS_IN => fee_trg_statusbits_i,
+ FEE_DATA_IN => fee_data_i,
+ FEE_DATA_WRITE_IN(0) => fee_data_write_i,
+ FEE_DATA_FINISHED_IN(0) => fee_data_finished_i,
+ FEE_DATA_ALMOST_FULL_OUT(0) => fee_almost_full_i,
+
+ -- Slow Control Data Port
+ REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00
+ REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20
+ REGIO_COMMON_STAT_STROBE_OUT => common_stat_reg_strobe,
+ REGIO_COMMON_CTRL_STROBE_OUT => common_ctrl_reg_strobe,
+ REGIO_STAT_REG_IN => stat_reg, --start 0x80
+ REGIO_CTRL_REG_OUT => ctrl_reg, --start 0xc0
+ REGIO_STAT_STROBE_OUT => stat_reg_strobe,
+ REGIO_CTRL_STROBE_OUT => ctrl_reg_strobe,
+ REGIO_VAR_ENDPOINT_ID(1 downto 0) => CODE_LINE,
+ REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'),
+
+ BUS_ADDR_OUT => regio_addr_out,
+ BUS_READ_ENABLE_OUT => regio_read_enable_out,
+ BUS_WRITE_ENABLE_OUT => regio_write_enable_out,
+ BUS_DATA_OUT => regio_data_out,
+ BUS_DATA_IN => regio_data_in,
+ BUS_DATAREADY_IN => regio_dataready_in,
+ BUS_NO_MORE_DATA_IN => regio_no_more_data_in,
+ BUS_WRITE_ACK_IN => regio_write_ack_in,
+ BUS_UNKNOWN_ADDR_IN => regio_unknown_addr_in,
+ BUS_TIMEOUT_OUT => regio_timeout_out,
+ ONEWIRE_INOUT => TEMPSENS,
+ ONEWIRE_MONITOR_OUT => open,
+
+ TIME_GLOBAL_OUT => global_time,
+ TIME_LOCAL_OUT => local_time,
+ TIME_SINCE_LAST_TRG_OUT => time_since_last_trg,
+ TIME_TICKS_OUT => timer_ticks,
+
+ STAT_DEBUG_IPU => open,
+ STAT_DEBUG_1 => open,
+ STAT_DEBUG_2 => open,
+ STAT_DEBUG_DATA_HANDLER_OUT => open,
+ STAT_DEBUG_IPU_HANDLER_OUT => open,
+ STAT_TRIGGER_OUT => open,
+ CTRL_MPLEX => (others => '0'),
+ IOBUF_CTRL_GEN => (others => '0'),
+ STAT_ONEWIRE => open,
+ STAT_ADDR_DEBUG => open,
+ DEBUG_LVL1_HANDLER_OUT => open
+ );
+
+---------------------------------------------------------------------------
+-- AddOn
+---------------------------------------------------------------------------
+
+
+---------------------------------------------------------------------------
+-- Bus Handler
+---------------------------------------------------------------------------
+ THE_BUS_HANDLER : trb_net16_regio_bus_handler
+ generic map(
+ PORT_NUMBER => 2,
+ PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", others => x"0000"),
+ PORT_ADDR_MASK => (0 => 1, 1 => 6, others => 0)
+ )
+ port map(
+ CLK => clk_100_i,
+ RESET => reset_i,
+
+ DAT_ADDR_IN => regio_addr_out,
+ DAT_DATA_IN => regio_data_out,
+ DAT_DATA_OUT => regio_data_in,
+ DAT_READ_ENABLE_IN => regio_read_enable_out,
+ DAT_WRITE_ENABLE_IN => regio_write_enable_out,
+ DAT_TIMEOUT_IN => regio_timeout_out,
+ DAT_DATAREADY_OUT => regio_dataready_in,
+ DAT_WRITE_ACK_OUT => regio_write_ack_in,
+ DAT_NO_MORE_DATA_OUT => regio_no_more_data_in,
+ DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in,
+
+ --Bus Handler (SPI CTRL)
+ BUS_READ_ENABLE_OUT(0) => spictrl_read_en,
+ BUS_WRITE_ENABLE_OUT(0) => spictrl_write_en,
+ BUS_DATA_OUT(0*32+31 downto 0*32) => spictrl_data_in,
+ BUS_ADDR_OUT(0*16) => spictrl_addr,
+ BUS_ADDR_OUT(0*16+15 downto 0*16+1) => open,
+ BUS_TIMEOUT_OUT(0) => open,
+ BUS_DATA_IN(0*32+31 downto 0*32) => spictrl_data_out,
+ BUS_DATAREADY_IN(0) => spictrl_ack,
+ BUS_WRITE_ACK_IN(0) => spictrl_ack,
+ BUS_NO_MORE_DATA_IN(0) => spictrl_busy,
+ BUS_UNKNOWN_ADDR_IN(0) => '0',
+ --Bus Handler (SPI Memory)
+ BUS_READ_ENABLE_OUT(1) => spimem_read_en,
+ BUS_WRITE_ENABLE_OUT(1) => spimem_write_en,
+ BUS_DATA_OUT(1*32+31 downto 1*32) => spimem_data_in,
+ BUS_ADDR_OUT(1*16+5 downto 1*16) => spimem_addr,
+ BUS_ADDR_OUT(1*16+15 downto 1*16+6) => open,
+ BUS_TIMEOUT_OUT(1) => open,
+ BUS_DATA_IN(1*32+31 downto 1*32) => spimem_data_out,
+ BUS_DATAREADY_IN(1) => spimem_ack,
+ BUS_WRITE_ACK_IN(1) => spimem_ack,
+ BUS_NO_MORE_DATA_IN(1) => '0',
+ BUS_UNKNOWN_ADDR_IN(1) => '0',
+
+ STAT_DEBUG => open
+ );
+
+---------------------------------------------------------------------------
+-- SPI / Flash
+---------------------------------------------------------------------------
+
+ THE_SPI_MASTER : spi_master
+ port map(
+ CLK_IN => clk_100_i,
+ RESET_IN => reset_i,
+ -- Slave bus
+ BUS_READ_IN => spictrl_read_en,
+ BUS_WRITE_IN => spictrl_write_en,
+ BUS_BUSY_OUT => spictrl_busy,
+ BUS_ACK_OUT => spictrl_ack,
+ BUS_ADDR_IN(0) => spictrl_addr,
+ BUS_DATA_IN => spictrl_data_in,
+ BUS_DATA_OUT => spictrl_data_out,
+ -- SPI connections
+ SPI_CS_OUT => FLASH_CS,
+ SPI_SDI_IN => FLASH_DOUT,
+ SPI_SDO_OUT => FLASH_DIN,
+ SPI_SCK_OUT => FLASH_CLK,
+ -- BRAM for read/write data
+ BRAM_A_OUT => spi_bram_addr,
+ BRAM_WR_D_IN => spi_bram_wr_d,
+ BRAM_RD_D_OUT => spi_bram_rd_d,
+ BRAM_WE_OUT => spi_bram_we,
+ -- Status lines
+ STAT => open
+ );
+
+-- data memory for SPI accesses
+ THE_SPI_MEMORY : spi_databus_memory
+ port map(
+ CLK_IN => clk_100_i,
+ RESET_IN => reset_i,
+ -- Slave bus
+ BUS_ADDR_IN => spimem_addr,
+ BUS_READ_IN => spimem_read_en,
+ BUS_WRITE_IN => spimem_write_en,
+ BUS_ACK_OUT => spimem_ack,
+ BUS_DATA_IN => spimem_data_in,
+ BUS_DATA_OUT => spimem_data_out,
+ -- state machine connections
+ BRAM_ADDR_IN => spi_bram_addr,
+ BRAM_WR_D_OUT => spi_bram_wr_d,
+ BRAM_RD_D_IN => spi_bram_rd_d,
+ BRAM_WE_IN => spi_bram_we,
+ -- Status lines
+ STAT => open
+ );
+
+---------------------------------------------------------------------------
+-- Reboot FPGA
+---------------------------------------------------------------------------
+ THE_FPGA_REBOOT : fpga_reboot
+ port map(
+ CLK => clk_100_i,
+ RESET => reset_i,
+ DO_REBOOT => common_ctrl_reg(15),
+ PROGRAMN => PROGRAMN
+ );
+
+
+
+---------------------------------------------------------------------------
+-- LED
+---------------------------------------------------------------------------
+ LED_GREEN <= not med_stat_op(9);
+ LED_ORANGE <= not med_stat_op(10);
+ LED_RED <= not time_counter(26);
+ LED_YELLOW <= not med_stat_op(11);
+
+
+---------------------------------------------------------------------------
+-- Test Connector
+---------------------------------------------------------------------------
+ TEST_LINE(7 downto 0) <= med_data_in(7 downto 0);
+ TEST_LINE(8) <= med_dataready_in;
+ TEST_LINE(9) <= med_dataready_out;
+ TEST_LINE(10) <= stat_reg_strobe(0);
+ TEST_LINE(15 downto 11) <= (others => '0');
+
+
+---------------------------------------------------------------------------
+-- Test Circuits
+---------------------------------------------------------------------------
+ process
+ begin
+ wait until rising_edge(clk_100_i);
+ time_counter <= time_counter + 1;
+ end process;
+
+end architecture;
jspc29 / trb3.git / commitdiff