update reset handling

diff --git a/backplanemaster/trb3sc_master.vhd b/backplanemaster/trb3sc_master.vhd
index 23527b98f61eddda3aaadeb6fe204537ce37eb80..ec0584a2947e4c4d667c4c895023c9d80cea7427 100644 (file)
--- a/backplanemaster/trb3sc_master.vhd
+++ b/backplanemaster/trb3sc_master.vhd
@@ -82,7 +82,7 @@ entity trb3sc_master is
   attribute syn_useioff of FLASH_CS   : signal is true;
   attribute syn_useioff of FLASH_IN   : signal is true;
   attribute syn_useioff of FLASH_OUT  : signal is true;
-
+  attribute syn_useioff of HDR_IO     : signal is false;
   
   --Serdes:                                Backplane
   --Backplane A2,A3,A0,A1                  Slave 3,4,1,2,             A0: TrbNet from backplane
@@ -166,6 +166,8 @@ architecture trb3sc_arch of trb3sc_master is
   signal med_ctrl_op          : std_logic_vector (11*16-1 downto 0);
   signal rdack, wrack         : std_logic;
   signal reset_from_net_i     : std_logic;
+  signal send_reset_i         : std_logic;
+  signal external_reset_delayed : std_logic_vector(4 downto 0);
   
   signal trig_gen_out_i   : std_logic_vector(3 downto 0);
   signal monitor_inputs_i : std_logic_vector(17 downto 0);
@@ -193,7 +195,7 @@ THE_CLOCK_RESET :  entity work.clock_reset_handler
     NET_CLK_FULL_IN => med2int(9).clk_full,
     NET_CLK_HALF_IN => med2int(9).clk_half,
     RESET_FROM_NET  => reset_from_net_i,
-    SEND_RESET_IN   => med2int(9).stat_op(15),
+    SEND_RESET_IN   => send_reset_i,
     
     BUS_RX          => bustc_rx,
     BUS_TX          => bustc_tx,
@@ -211,7 +213,8 @@ THE_CLOCK_RESET :  entity work.clock_reset_handler
     LED_GREEN_OUT   => LED_RJ_GREEN,
     DEBUG_OUT       => debug_clock_reset
     );
-reset_from_net_i <= med2int(9).stat_op(13) or reset_via_gbe;
+reset_from_net_i <= med2int(9).stat_op(13)  or external_reset_delayed(4) ;
+send_reset_i <= med2int(9).stat_op(15); --int2med(0).ctrl_op(15) or;
 
 ---------------------------------------------------------------------------
 -- TrbNet Uplink
@@ -254,7 +257,7 @@ THE_MEDIA_INT_MIXED : entity work.med_ecp3_sfp_sync_4_slave3  --PCSB
     SD_LOS_IN(2)       => backplane_rx_present(5),
     SD_TXDIS_OUT(2)    => backplane_tx_present(5),    
     SD_PRSNT_N_IN(3)   => SFP_MOD0(1),
-    SD_LOS_IN(3)       => SFP_LOS(1),
+    SD_LOS_IN(3)       => '0', --SFP_LOS(1),
     SD_TXDIS_OUT(3)    => SFP_TX_DIS(1),
     --Control Interface
     BUS_RX             => bussci2_rx,
@@ -573,7 +576,22 @@ begin
     CTRL_DEBUG              => (others => '0')
   );
   
-  external_reset_i <= reset_via_gbe or med2int(INTERFACE_NUM-1).stat_op(15);
+  external_reset_i <= reset_via_gbe; -- or med2int(9).stat_op(13);
+  
+  process begin
+    wait until rising_edge(clk_sys);
+    external_reset_delayed(0) <= external_reset_delayed(0) or external_reset_i;
+    external_reset_delayed(3) <= external_reset_delayed(2);
+    external_reset_delayed(4) <= external_reset_delayed(2) and not external_reset_delayed(3);
+    if timer.tick_us = '1' then
+      external_reset_delayed(1) <= external_reset_delayed(0);
+      external_reset_delayed(2) <= external_reset_delayed(1);
+    end if;
+    if reset_i = '1' then
+      external_reset_delayed <= (others => '0');
+    end if;  
+  end process;  
+  
 end generate;
 
 
@@ -655,6 +673,7 @@ gen_hub_no_gbe : if INCLUDE_GBE = c_NO generate
   wrack <= ctrlbus_tx.ack or ctrlbus_tx.wack;
   reboot_from_gbe <= '0';
   reset_via_gbe   <= '0';
+  external_reset_delayed <= (others => '0');
 end generate;
 
 ---------------------------------------------------------------------------
@@ -807,6 +826,15 @@ end generate;
   
   
 --   TEST_LINE <= med_stat_debug(15 downto 0);
+  TEST_LINE(0) <= med2int(9).stat_op(13);
+  TEST_LINE(1) <= med2int(9).stat_op(15);
+  TEST_LINE(2) <= clear_i;
+  TEST_LINE(3) <= reset_i;
+  TEST_LINE(4) <= med2int(9).dataready;
+  TEST_LINE(5) <= int2med(9).dataready;
+  TEST_LINE(6) <= med2int(7).dataready;
+  TEST_LINE(7) <= int2med(7).dataready;
+--   TEST_LINE(7) <= med2int(9).stat_op(9);
   
 end architecture;
 

diff --git a/hub/trb3sc_hub.vhd b/hub/trb3sc_hub.vhd
index abb1f9c1f8e0a158f75c3400a8790bf5f589418c..969ff5d25c81ad94b4db34a4ea1724423afc81f6 100644 (file)
--- a/hub/trb3sc_hub.vhd
+++ b/hub/trb3sc_hub.vhd
@@ -644,7 +644,7 @@ gen_hub_with_gbe : if INCLUDE_GBE = c_YES generate
       STAT_DEBUG              => open,
       CTRL_DEBUG              => (others => '0')
     );
-  external_reset_i <= reset_via_gbe or med2int(INTERFACE_NUM-1).stat_op(15);
+  external_reset_i <= reset_via_gbe; -- or med2int(INTERFACE_NUM-1).stat_op(15);
 end generate;
 
 
@@ -864,7 +864,15 @@ end generate;
                         not  (med2int(8).stat_op(10) or med2int(8).stat_op(11) or not med2int(8).stat_op(9))    when INCLUDE_GBE = 1 and USE_BACKPLANE = 1 else
                              '1';
 
-  
+  TEST_LINE(0) <= med2int(INTERFACE_NUM-1).stat_op(13);
+  TEST_LINE(1) <= med2int(INTERFACE_NUM-1).stat_op(15);
+  TEST_LINE(2) <= clear_i;
+  TEST_LINE(3) <= reset_i;
+--   TEST_LINE(4) <= time_counter(26);
+--   TEST_LINE(5) <= BACK_GPIO(1);
+--   TEST_LINE(6) <= sfp_txdis_i;
+  TEST_LINE(7) <= med2int(INTERFACE_NUM-1).stat_op(9);
+    
   
 end architecture;
 

diff --git a/tdctemplate/trb3sc_tdctemplate.vhd b/tdctemplate/trb3sc_tdctemplate.vhd
index e6a75733eb68d0b05d4caf529cba142695e07175..2bbf5811434e1596353b7c49fc5aa3762e451ba4 100644 (file)
--- a/tdctemplate/trb3sc_tdctemplate.vhd
+++ b/tdctemplate/trb3sc_tdctemplate.vhd
@@ -165,6 +165,7 @@ begin
       NET_CLK_FULL_IN => med2int(0).clk_full,
       NET_CLK_HALF_IN => med2int(0).clk_half,
       RESET_FROM_NET  => med2int(0).stat_op(13),
+      SEND_RESET_IN   => med2int(0).stat_op(15),
 
       BUS_RX => bustc_rx,
       BUS_TX => bustc_tx,
@@ -463,8 +464,15 @@ end generate;
 
 
 --TEST_LINE <= med2int(0).dataready & int2med(0).dataready & med2int(0).data(6 downto 0) & int2med(0).data(6 downto 0);
-TEST_LINE <=   med_stat_debug(15 downto 0);
-  
+-- TEST_LINE <=   med_stat_debug(15 downto 0);
+  TEST_LINE(0) <= med2int(0).stat_op(13);
+  TEST_LINE(1) <= med2int(0).stat_op(15);
+  TEST_LINE(2) <= clear_i;
+  TEST_LINE(3) <= reset_i;
+  TEST_LINE(4) <= time_counter(26);
+  TEST_LINE(5) <= BACK_GPIO(1);
+  TEST_LINE(6) <= sfp_txdis_i;
+  TEST_LINE(7) <= med2int(0).stat_op(9);
 -------------------------------------------------------------------------------
 -- TDC
 -------------------------------------------------------------------------------

diff --git a/template/trb3sc_basic.vhd b/template/trb3sc_basic.vhd
index a346d1dafb3e14e24a11955de020181b3e82be76..859f2295b53d10a55bd101f4a3d427cfe6be2c2a 100644 (file)
--- a/template/trb3sc_basic.vhd
+++ b/template/trb3sc_basic.vhd
@@ -30,11 +30,11 @@ entity trb3sc_basic is
     --TRIG_RIGHT           : in    std_logic; --not used
     
     --Backplane, all lines
-    BACK_GPIO            : inout std_logic_vector(15 downto 0);
+--     BACK_GPIO            : inout std_logic_vector(15 downto 0);
     BACK_LVDS            : inout std_logic_vector( 1 downto 0);
     BACK_3V3             : inout std_logic_vector( 3 downto 0);
     --Backplane for slaves on trbv3scbp1
---     BACK_GPIO            : inout std_logic_vector(3 downto 0);
+    BACK_GPIO            : inout std_logic_vector(3 downto 0);
     
     --AddOn Connector
     --to be added
@@ -357,7 +357,7 @@ THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record
       --Trigger & Monitor 
       MONITOR_INPUTS   => KEL(32 downto 1),--(others => '0'),
       TRIG_GEN_INPUTS  => KEL(32 downto 1),--(others => '0'),
-      TRIG_GEN_OUTPUTS => BACK_GPIO(3 downto 1),--open,
+      TRIG_GEN_OUTPUTS => BACK_GPIO(3 downto 2),--open,
       --SED
       SED_ERROR_OUT => sed_error_i,
       --Slowcontrol
@@ -426,8 +426,15 @@ THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record
   end process;  
 
 --   TEST_LINE <= med_stat_debug(15 downto 0);
-  TEST_LINE(15 downto 0) <= debug_clock_reset(15 downto 14) & med2int(0).stat_op(13) & clear_i & reset_i & debug_clock_reset(10 downto 0);  
-  
+--   TEST_LINE(15 downto 0) <= debug_clock_reset(15 downto 14) & med2int(0).stat_op(13) & clear_i & reset_i & debug_clock_reset(10 downto 0);  
+  TEST_LINE(0) <= med2int(0).stat_op(13);
+  TEST_LINE(1) <= med2int(0).stat_op(15);
+  TEST_LINE(2) <= clear_i;
+  TEST_LINE(3) <= reset_i;
+  TEST_LINE(4) <= med2int(0).dataready;
+  TEST_LINE(5) <= int2med(0).dataready;
+  TEST_LINE(6) <= sfp_txdis_i;
+  TEST_LINE(7) <= med2int(0).stat_op(9);
 -- readout_tx(0).data_finished <= '1';
 -- readout_tx(0).data_write    <= '0';
 -- readout_tx(0).busy_release  <= '1';