generic (
API_TYPE : integer range 0 to 1 := 1;
- INIT_DEPTH : integer range 0 to 7 := 0;
- REPLY_DEPTH : integer range 0 to 7 := 1;
- FIFO_TO_INT_DEPTH : integer range 0 to 7 := 1;
- FIFO_TO_APL_DEPTH : integer range 0 to 7 := 1;
- FIFO_TERM_BUFFER_DEPTH : integer := 0;
- MULT_WIDTH : integer range 1 to 5 := 3;
- DAT_CHANNEL : integer range 0 to 2**(MULT_WIDTH-1) := 0;
- DATA_WIDTH : integer range 16 to 16 := 16;
- NUM_WIDTH : integer range 2 to 2 := 2
+ INIT_DEPTH : integer range 0 to 6 := 0;
+ REPLY_DEPTH : integer range 0 to 6 := 1;
+ FIFO_TO_INT_DEPTH : integer range 0 to 6 := 1;
+ FIFO_TO_APL_DEPTH : integer range 0 to 6 := 1;
+ SBUF_VERSION : integer range 0 to 1 := 0;
+ MUX_WIDTH : integer range 1 to 5 := 3;
+ MUX_SECURE_MODE : integer range 0 to 1 := 0;
+ DAT_CHANNEL : integer range 0 to 2**(MUX_WIDTH-1) := 0;
+ DATA_WIDTH : integer := 16;
+ NUM_WIDTH : integer := 2
);
port(
-- for the direction to
-- internal world
FIFO_TO_APL_DEPTH : integer := 3; -- direction to application
- FIFO_TERM_BUFFER_DEPTH : integer := 0 -- fifo for auto-answering of
+ FIFO_TERM_BUFFER_DEPTH : integer := 0; -- fifo for auto-answering of
-- the master path, if set to 0
-- no buffer is used at all
+ SBUF_VERSION : integer range 0 to 1 := 0
);
port(
component trb_net16_io_multiplexer is
- generic (BUS_WIDTH : integer := 16;
- MULT_WIDTH : integer := 1);
-
+ generic (
+ DATA_WIDTH : integer := 16;
+ NUM_WIDTH : integer := 2;
+ MUX_WIDTH : integer range 1 to 5 := 3;
+ MUX_SECURE_MODE : integer range 0 to 1 := 0 --use sbufs or not?
+ );
port(
-- Misc
CLK : in std_logic;
MED_READ_IN: in std_logic;
-- Internal direction port
- INT_DATAREADY_OUT: out std_logic_vector (2**MULT_WIDTH-1 downto 0);
- INT_DATA_OUT: out std_logic_vector ((DATA_WIDTH)*(2**MULT_WIDTH)-1 downto 0);
- INT_PACKET_NUM_OUT:out std_logic_vector (2*(2**MULT_WIDTH)-1 downto 0);
- INT_READ_IN: in std_logic_vector (2**MULT_WIDTH-1 downto 0);
-
- INT_DATAREADY_IN: in std_logic_vector (2**MULT_WIDTH-1 downto 0);
- INT_DATA_IN: in std_logic_vector ((DATA_WIDTH)*(2**MULT_WIDTH)-1 downto 0);
- INT_PACKET_NUM_IN: in std_logic_vector (2*(2**MULT_WIDTH)-1 downto 0);
- INT_READ_OUT: out std_logic_vector (2**MULT_WIDTH-1 downto 0);
+ INT_DATAREADY_OUT: out std_logic_vector (2**MUX_WIDTH-1 downto 0);
+ INT_DATA_OUT: out std_logic_vector ((DATA_WIDTH)*(2**MUX_WIDTH)-1 downto 0);
+ INT_PACKET_NUM_OUT:out std_logic_vector (2*(2**MUX_WIDTH)-1 downto 0);
+ INT_READ_IN: in std_logic_vector (2**MUX_WIDTH-1 downto 0);
+
+ INT_DATAREADY_IN: in std_logic_vector (2**MUX_WIDTH-1 downto 0);
+ INT_DATA_IN: in std_logic_vector ((DATA_WIDTH)*(2**MUX_WIDTH)-1 downto 0);
+ INT_PACKET_NUM_IN: in std_logic_vector (2*(2**MUX_WIDTH)-1 downto 0);
+ INT_READ_OUT: out std_logic_vector (2**MUX_WIDTH-1 downto 0);
-- Status and control port
CTRL: in std_logic_vector (31 downto 0);
);
end component;
+ component trb_net16_term_buf is
+ port(
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ MED_INIT_DATAREADY_OUT: out std_logic;
+ MED_INIT_DATA_OUT: out std_logic_vector (15 downto 0);
+ MED_INIT_PACKET_NUM_OUT: out std_logic_vector (1 downto 0);
+ MED_INIT_READ_IN: in std_logic;
+ MED_INIT_DATAREADY_IN: in std_logic;
+ MED_INIT_DATA_IN: in std_logic_vector (15 downto 0);
+ MED_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
+ MED_INIT_READ_OUT: out std_logic;
+ MED_REPLY_DATAREADY_OUT: out std_logic;
+ MED_REPLY_DATA_OUT: out std_logic_vector (15 downto 0);
+ MED_REPLY_PACKET_NUM_OUT: out std_logic_vector (1 downto 0);
+ MED_REPLY_READ_IN: in std_logic;
+ MED_REPLY_DATAREADY_IN: in std_logic;
+ MED_REPLY_DATA_IN: in std_logic_vector (15 downto 0);
+ MED_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
+ MED_REPLY_READ_OUT: out std_logic
+ );
+ end component;
+
signal apl_to_buf_INIT_DATAREADY: std_logic;
signal apl_to_buf_INIT_DATA : std_logic_vector (15 downto 0);
signal apl_to_buf_INIT_PACKET_NUM:std_logic_vector (1 downto 0);
signal MED_REPLY_PACKET_NUM_IN : std_logic_vector (1 downto 0);
signal MED_REPLY_READ_OUT : std_logic;
-signal m_DATAREADY_OUT : std_logic_vector (2**MULT_WIDTH-1 downto 0);
-signal m_DATA_OUT : std_logic_vector (DATA_WIDTH*2**MULT_WIDTH-1 downto 0);
-signal m_PACKET_NUM_OUT: std_logic_vector (NUM_WIDTH*2**MULT_WIDTH-1 downto 0);
-signal m_READ_IN : std_logic_vector (2**MULT_WIDTH-1 downto 0);
+signal m_DATAREADY_OUT : std_logic_vector (2**MUX_WIDTH-1 downto 0);
+signal m_DATA_OUT : std_logic_vector (DATA_WIDTH*2**MUX_WIDTH-1 downto 0);
+signal m_PACKET_NUM_OUT: std_logic_vector (NUM_WIDTH*2**MUX_WIDTH-1 downto 0);
+signal m_READ_IN : std_logic_vector (2**MUX_WIDTH-1 downto 0);
-signal m_DATAREADY_IN : std_logic_vector (2**MULT_WIDTH-1 downto 0);
-signal m_DATA_IN : std_logic_vector (DATA_WIDTH*2**MULT_WIDTH-1 downto 0);
-signal m_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH*2**MULT_WIDTH-1 downto 0);
-signal m_READ_OUT : std_logic_vector (2**MULT_WIDTH-1 downto 0);
+signal m_DATAREADY_IN : std_logic_vector (2**MUX_WIDTH-1 downto 0);
+signal m_DATA_IN : std_logic_vector (DATA_WIDTH*2**MUX_WIDTH-1 downto 0);
+signal m_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH*2**MUX_WIDTH-1 downto 0);
+signal m_READ_OUT : std_logic_vector (2**MUX_WIDTH-1 downto 0);
begin
--Connections for data channel
- genmuxcon : for i in 0 to 2**(MULT_WIDTH-1)-1 generate
+ genmuxcon : for i in 0 to 2**(MUX_WIDTH-1)-1 generate
gendat: if i = DAT_CHANNEL generate
m_DATAREADY_OUT(i*2) <= MED_INIT_DATAREADY_OUT;
m_DATAREADY_OUT(i*2+1) <= MED_REPLY_DATAREADY_OUT;
m_READ_OUT(i*2+1) <= MED_REPLY_READ_OUT;
end generate;
genelse: if i /= DAT_CHANNEL generate
- m_DATAREADY_OUT(i*2) <= '0';
- m_DATAREADY_OUT(i*2+1) <= '0';
- m_DATA_OUT((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2) <= (others => '0');
- m_DATA_OUT((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH) <= (others => '0');
- m_PACKET_NUM_OUT(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2) <= (others => '0');
- m_PACKET_NUM_OUT(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2) <= (others => '0');
-
- m_READ_OUT(i*2) <= '0';
- m_READ_OUT(i*2+1) <= '0';
+ termbuf: trb_net16_term_buf
+ port map(
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+ MED_INIT_DATAREADY_OUT => m_DATAREADY_OUT(i*2),
+ MED_INIT_DATA_OUT => m_DATA_OUT((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2),
+ MED_INIT_PACKET_NUM_OUT => m_PACKET_NUM_OUT(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2),
+ MED_INIT_READ_IN => m_READ_IN(i*2),
+ MED_INIT_DATAREADY_IN => m_DATAREADY_IN(i*2),
+ MED_INIT_DATA_IN => m_DATA_IN((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2),
+ MED_INIT_PACKET_NUM_IN => m_PACKET_NUM_IN(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2),
+ MED_INIT_READ_OUT => m_READ_OUT(i*2),
+
+ MED_REPLY_DATAREADY_OUT => m_DATAREADY_OUT(i*2+1),
+ MED_REPLY_DATA_OUT => m_DATA_OUT((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH),
+ MED_REPLY_PACKET_NUM_OUT => m_PACKET_NUM_OUT(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2),
+ MED_REPLY_READ_IN => m_READ_IN(i*2+1),
+ MED_REPLY_DATAREADY_IN => m_DATAREADY_IN(i*2+1),
+ MED_REPLY_DATA_IN => m_DATA_IN((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH),
+ MED_REPLY_PACKET_NUM_IN => m_PACKET_NUM_IN(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2),
+ MED_REPLY_READ_OUT => m_READ_OUT(i*2+1)
+ );
end generate;
end generate;
API_TYPE => 1,
FIFO_TO_INT_DEPTH => FIFO_TO_INT_DEPTH,
FIFO_TO_APL_DEPTH => FIFO_TO_APL_DEPTH,
- FIFO_TERM_BUFFER_DEPTH => FIFO_TERM_BUFFER_DEPTH
+ FIFO_TERM_BUFFER_DEPTH => 0,
+ SBUF_VERSION => SBUF_VERSION
)
port map (
-- Misc
API_TYPE => 0,
FIFO_TO_INT_DEPTH => FIFO_TO_INT_DEPTH,
FIFO_TO_APL_DEPTH => FIFO_TO_APL_DEPTH,
- FIFO_TERM_BUFFER_DEPTH => FIFO_TERM_BUFFER_DEPTH
+ FIFO_TERM_BUFFER_DEPTH => 0,
+ SBUF_VERSION => SBUF_VERSION
)
port map (
-- Misc
);
MPLEX: trb_net16_io_multiplexer
- generic map (BUS_WIDTH => DATA_WIDTH,
- MULT_WIDTH => MULT_WIDTH)
+ generic map (
+ DATA_WIDTH => DATA_WIDTH,
+ NUM_WIDTH => NUM_WIDTH,
+ MUX_WIDTH => MUX_WIDTH,
+ MUX_SECURE_MODE => MUX_SECURE_MODE
+ )
port map (
- CLK => CLK,
- RESET => RESET ,
- CLK_EN => CLK_EN,
-
- MED_DATAREADY_IN => MED_DATAREADY_IN,
- MED_DATA_IN => MED_DATA_IN,
- MED_PACKET_NUM_IN => MED_PACKET_NUM_IN,
- MED_READ_OUT => MED_READ_OUT,
-
- MED_DATAREADY_OUT => MED_DATAREADY_OUT,
- MED_DATA_OUT => MED_DATA_OUT,
- MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT,
- MED_READ_IN => MED_READ_IN,
-
- INT_DATAREADY_OUT => m_DATAREADY_IN,
- INT_DATA_OUT =>m_DATA_IN,
- INT_PACKET_NUM_OUT => m_PACKET_NUM_IN,
- INT_READ_IN =>m_READ_OUT,
-
- INT_DATAREADY_IN =>m_DATAREADY_OUT,
- INT_DATA_IN =>m_DATA_OUT,
- INT_PACKET_NUM_IN => m_PACKET_NUM_OUT,
- INT_READ_OUT =>m_READ_IN,
-
- CTRL => MPLEX_CTRL
-
- );
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+ MED_DATAREADY_IN => MED_DATAREADY_IN,
+ MED_DATA_IN => MED_DATA_IN,
+ MED_PACKET_NUM_IN => MED_PACKET_NUM_IN,
+ MED_READ_OUT => MED_READ_OUT,
+ MED_DATAREADY_OUT => MED_DATAREADY_OUT,
+ MED_DATA_OUT => MED_DATA_OUT,
+ MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT,
+ MED_READ_IN => MED_READ_IN,
+ INT_DATAREADY_OUT => m_DATAREADY_IN,
+ INT_DATA_OUT => m_DATA_IN,
+ INT_PACKET_NUM_OUT => m_PACKET_NUM_IN,
+ INT_READ_IN => m_READ_OUT,
+ INT_DATAREADY_IN => m_DATAREADY_OUT,
+ INT_DATA_IN => m_DATA_OUT,
+ INT_PACKET_NUM_IN => m_PACKET_NUM_OUT,
+ INT_READ_OUT => m_READ_IN,
+ CTRL => MPLEX_CTRL
+ );
end architecture;
---------------------------------------
-- termination for active api
---------------------------------------
-
+ genterm: if API_TYPE = 1 generate
TrbNetTerm: trb_net16_term
generic map(
SECURE_MODE => 0
INT_READ_OUT => INT_MASTER_READ_OUT,
APL_RELEASE_TRM => '1',
APL_ERROR_PATTERN_IN => (others => '0')
- );
+ );
+ end generate;
+ gennotterm: if API_TYPE = 0 generate
+ INT_MASTER_READ_OUT <= '1';
+ INT_SLAVE_DATAREADY_OUT <= '0';
+ end generate;
---------------------------------------
-- fifo to internal
APL_DATA_OUT <= reg_APL_DATA_OUT;
APL_PACKET_NUM_OUT <= reg_APL_PACKET_NUM_OUT;
APL_TYP_OUT <= reg_APL_TYP_OUT;
- APL_RUN_OUT <= '0' when ((current_state = IDLE and API_TYPE = 1)
- or (slave_running = '0' and API_TYPE = 0))
- else '1';
+
+ genAPL_RUN_OUT_0: if API_TYPE = 0 generate
+ APL_RUN_OUT <= slave_running;
+ end generate;
+ genAPL_RUN_OUT_1: if API_TYPE = 1 generate
+ APL_RUN_OUT <= '0' when current_state = IDLE else '1';
+ end generate;
+
APL_SEQNR_OUT <= sequence_counter;
REG3 : process(CLK)
din(DATA_WIDTH + NUM_WIDTH -1 downto DATA_WIDTH) <= PACKET_NUM_IN;
DATA_OUT <= dout(DATA_WIDTH - 1 downto 0);
PACKET_NUM_OUT <= dout(DATA_WIDTH + NUM_WIDTH - 1 downto DATA_WIDTH);
- DEPTH_OUT <= depth16 - 2;
+ DEPTH_OUT <= conv_std_logic_vector(DEPTH, 8);
fifo : trb_net_fifo
port map(
-- make STAT_BUFFER
- STAT_BUFFER(3 downto 0) <= (fifo_depth(3 downto 0)-1); --divide by 2, since 2
- --buffers have to be stored
+ STAT_BUFFER(3 downto 0) <= (fifo_depth(3 downto 0));
STAT_BUFFER(7 downto 4) <= current_rec_buffer_size_out;
STAT_BUFFER(8) <= reg_eob_out;
STAT_BUFFER(9) <= reg_ack_internal;
entity trb_net16_io_multiplexer is
generic (
- BUS_WIDTH : integer := 16;
+ DATA_WIDTH : integer := 16;
NUM_WIDTH : integer := 2;
- MULT_WIDTH : integer range 1 to 5 := 3;
- SECURE_MODE : integer range 0 to 1 := 0 --use sbufs or not?
+ MUX_WIDTH : integer range 1 to 5 := 3;
+ MUX_SECURE_MODE : integer range 0 to 1 := 0 --use sbufs or not?
);
port(
-- Media direction port
MED_DATAREADY_IN: in STD_LOGIC;
- MED_DATA_IN: in STD_LOGIC_VECTOR (BUS_WIDTH-1 downto 0);
+ MED_DATA_IN: in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
MED_PACKET_NUM_IN: in STD_LOGIC_VECTOR (1 downto 0);
MED_READ_OUT: out STD_LOGIC;
MED_DATAREADY_OUT: out STD_LOGIC;
- MED_DATA_OUT: out STD_LOGIC_VECTOR (BUS_WIDTH-1 downto 0);
+ MED_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
MED_PACKET_NUM_OUT: out STD_LOGIC_VECTOR (1 downto 0);
MED_READ_IN: in STD_LOGIC;
-- Internal direction port
- INT_DATAREADY_OUT: out STD_LOGIC_VECTOR (2**MULT_WIDTH-1 downto 0);
- INT_DATA_OUT: out STD_LOGIC_VECTOR ((BUS_WIDTH)*(2**MULT_WIDTH)-1 downto 0);
- INT_PACKET_NUM_OUT: out STD_LOGIC_VECTOR (2*(2**MULT_WIDTH)-1 downto 0);
- INT_READ_IN: in STD_LOGIC_VECTOR (2**MULT_WIDTH-1 downto 0);
-
- INT_DATAREADY_IN: in STD_LOGIC_VECTOR (2**MULT_WIDTH-1 downto 0);
- INT_DATA_IN: in STD_LOGIC_VECTOR ((BUS_WIDTH)*(2**MULT_WIDTH)-1 downto 0);
- INT_PACKET_NUM_IN: in STD_LOGIC_VECTOR (2*(2**MULT_WIDTH)-1 downto 0);
- INT_READ_OUT: out STD_LOGIC_VECTOR (2**MULT_WIDTH-1 downto 0);
+ INT_DATAREADY_OUT: out STD_LOGIC_VECTOR (2**MUX_WIDTH-1 downto 0);
+ INT_DATA_OUT: out STD_LOGIC_VECTOR ((DATA_WIDTH)*(2**MUX_WIDTH)-1 downto 0);
+ INT_PACKET_NUM_OUT: out STD_LOGIC_VECTOR (2*(2**MUX_WIDTH)-1 downto 0);
+ INT_READ_IN: in STD_LOGIC_VECTOR (2**MUX_WIDTH-1 downto 0);
+
+ INT_DATAREADY_IN: in STD_LOGIC_VECTOR (2**MUX_WIDTH-1 downto 0);
+ INT_DATA_IN: in STD_LOGIC_VECTOR ((DATA_WIDTH)*(2**MUX_WIDTH)-1 downto 0);
+ INT_PACKET_NUM_IN: in STD_LOGIC_VECTOR (2*(2**MUX_WIDTH)-1 downto 0);
+ INT_READ_OUT: out STD_LOGIC_VECTOR (2**MUX_WIDTH-1 downto 0);
-- Status and control port
CTRL: in STD_LOGIC_VECTOR (31 downto 0);
architecture trb_net16_io_multiplexer_arch of trb_net16_io_multiplexer is
component trb_net_pattern_gen is
- generic (MULT_WIDTH : integer := 1);
+ generic (MULT_WIDTH : integer := 1);
port(
- INPUT_IN : in STD_LOGIC_VECTOR (MULT_WIDTH-1 downto 0);
- RESULT_OUT: out STD_LOGIC_VECTOR (2**MULT_WIDTH-1 downto 0)
+ INPUT_IN : in STD_LOGIC_VECTOR (MUX_WIDTH-1 downto 0);
+ RESULT_OUT: out STD_LOGIC_VECTOR (2**MUX_WIDTH-1 downto 0)
);
end component;
end component;
component trb_net_priority_arbiter is
- generic (WIDTH : integer := 2**MULT_WIDTH);
+ generic (WIDTH : integer := 2**MUX_WIDTH);
port(
-- Misc
CLK : in std_logic;
);
end component;
- signal MUX_SBUF_data_out : std_logic_vector(BUS_WIDTH+1 downto 0);
- signal demux_next_READ, current_demux_READ : STD_LOGIC_VECTOR ((2**MULT_WIDTH)-1 downto 0);
- signal next_demux_dr, next_demux_dr_tmp, demux_dr_tmp: STD_LOGIC_VECTOR ((2**MULT_WIDTH)-1 downto 0);
+ signal MUX_SBUF_data_out : std_logic_vector(DATA_WIDTH+1 downto 0);
+ signal demux_next_READ, current_demux_READ : STD_LOGIC_VECTOR ((2**MUX_WIDTH)-1 downto 0);
+ signal next_demux_dr, next_demux_dr_tmp, demux_dr_tmp: STD_LOGIC_VECTOR ((2**MUX_WIDTH)-1 downto 0);
signal current_MED_READ_OUT, next_MED_READ_OUT: STD_LOGIC;
- signal tmp_INT_READ_OUT, final_INT_READ_OUT: STD_LOGIC_VECTOR ((2**MULT_WIDTH)-1 downto 0);
- --signal tmp_tmp_INT_READ_OUT: STD_LOGIC_VECTOR ((2**MULT_WIDTH)-1 downto 0);
+ signal tmp_INT_READ_OUT, final_INT_READ_OUT: STD_LOGIC_VECTOR ((2**MUX_WIDTH)-1 downto 0);
+ --signal tmp_tmp_INT_READ_OUT: STD_LOGIC_VECTOR ((2**MUX_WIDTH)-1 downto 0);
signal mux_read, mux_enable, mux_next_READ: STD_LOGIC;
- signal current_mux_buffer: STD_LOGIC_VECTOR (BUS_WIDTH+2-1 downto 0);
+ signal current_mux_buffer: STD_LOGIC_VECTOR (DATA_WIDTH+2-1 downto 0);
signal endpoint_locked, next_endpoint_locked: std_logic;
- signal demux_sbuf_data_in : std_logic_vector((BUS_WIDTH+2)-1 downto 0);
- signal demux_sbuf_data_out: std_logic_vector((BUS_WIDTH+2)*(2**MULT_WIDTH)-1 downto 0);
- signal current_INT_READ_OUT : STD_LOGIC_VECTOR ((2**MULT_WIDTH)-1 downto 0);
+ signal demux_sbuf_data_in : std_logic_vector((DATA_WIDTH+2)-1 downto 0);
+ signal demux_sbuf_data_out: std_logic_vector((DATA_WIDTH+2)*(2**MUX_WIDTH)-1 downto 0);
+ signal current_INT_READ_OUT : STD_LOGIC_VECTOR ((2**MUX_WIDTH)-1 downto 0);
signal current_mux_packet_number : std_logic_vector (1 downto 0);
begin
-------------------------------------------------------------------------------
-- DEMUX
------------------------------------------------------------------------------
- G1: for i in 0 to 2**MULT_WIDTH-1 generate
- gensbuf: if SECURE_MODE = 1 generate
+ G1: for i in 0 to 2**MUX_WIDTH-1 generate
+ gensbuf: if MUX_SECURE_MODE = 1 generate
DEMUX_SBUF: trb_net16_sbuf
- generic map (DATA_WIDTH => BUS_WIDTH, NUM_WIDTH => NUM_WIDTH, VERSION => 0)
+ generic map (DATA_WIDTH => DATA_WIDTH, NUM_WIDTH => NUM_WIDTH, VERSION => 0)
port map (
CLK => CLK,
RESET => RESET,
COMB_DATA_IN => MED_DATA_IN,
COMB_PACKET_NUM_IN => MED_PACKET_NUM_IN,
SYN_DATAREADY_OUT => INT_DATAREADY_OUT(i),
- SYN_DATA_OUT => INT_DATA_OUT ((BUS_WIDTH)*(i+1)-1 downto (BUS_WIDTH)*(i)),
+ SYN_DATA_OUT => INT_DATA_OUT ((DATA_WIDTH)*(i+1)-1 downto (DATA_WIDTH)*(i)),
SYN_PACKET_NUM_OUT => INT_PACKET_NUM_OUT(2*(i+1)-1 downto 2*i),
SYN_READ_IN => INT_READ_IN(i)
);
end generate;
- if SECURE_MODE = 0 generate
+ genff: if MUX_SECURE_MODE = 0 generate
process(CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
- INT_DATA_OUT ((BUS_WIDTH)*(i+1)-1 downto (BUS_WIDTH)*(i)) <= (others => '0');
+ INT_DATA_OUT ((DATA_WIDTH)*(i+1)-1 downto (DATA_WIDTH)*(i)) <= (others => '0');
INT_PACKET_NUM_OUT(2*(i+1)-1 downto 2*i) <= (others => '0');
INT_DATAREADY_OUT(i) <= '0';
else
- INT_DATA_OUT ((BUS_WIDTH)*(i+1)-1 downto (BUS_WIDTH)*(i)) <= MED_DATA_IN;
+ INT_DATA_OUT ((DATA_WIDTH)*(i+1)-1 downto (DATA_WIDTH)*(i)) <= MED_DATA_IN;
INT_PACKET_NUM_OUT(2*(i+1)-1 downto 2*i) <= MED_PACKET_NUM_IN;
INT_DATAREADY_OUT(i) <= next_demux_dr(i);
end if;
comb_demux : process (next_demux_dr_tmp, demux_next_READ, INT_READ_IN,
MED_DATAREADY_IN, current_MED_READ_OUT,
- MED_PACKET_NUM_IN, demux_dr_tmp)
+ MED_PACKET_NUM_IN, demux_dr_tmp)
begin
next_demux_dr <= (others => '0');
current_demux_READ <= (others => '0');
-- the output of the pattern generator is only valid for packet number 00!
DEFDR: trb_net_pattern_gen
- generic map (MULT_WIDTH => MULT_WIDTH)
+ generic map (MULT_WIDTH => MUX_WIDTH)
port map (
- INPUT_IN => MED_DATA_IN(3+MULT_WIDTH-1 downto 3),
+ INPUT_IN => MED_DATA_IN(3+MUX_WIDTH-1 downto 3),
RESULT_OUT => next_demux_dr_tmp -- this will have a 1 in ANY case
);
keep_valid_demux : process(CLK)
-- MUX part with arbitration scheme
-------------------------------------------------------------------------------
ARBITER: trb_net_priority_arbiter
- generic map (WIDTH => 2**MULT_WIDTH)
+ generic map (WIDTH => 2**MUX_WIDTH)
port map (
CLK => CLK,
RESET => RESET,
current_INT_READ_OUT <= tmp_INT_READ_OUT when endpoint_locked = '0'
else final_INT_READ_OUT;
- STAT(17 downto 16) <= current_mux_buffer(BUS_WIDTH+1 downto BUS_WIDTH) xor current_mux_packet_number;
+ STAT(17 downto 16) <= current_mux_buffer(DATA_WIDTH+1 downto DATA_WIDTH) xor current_mux_packet_number;
process(CLK)
begin
MUX_SBUF: trb_net16_sbuf
- generic map (DATA_WIDTH => BUS_WIDTH, NUM_WIDTH => NUM_WIDTH, VERSION => 0)
+ generic map (DATA_WIDTH => DATA_WIDTH, NUM_WIDTH => NUM_WIDTH, VERSION => 0)
port map (
CLK => CLK,
RESET => RESET,
COMB_DATAREADY_IN => mux_read,
COMB_next_READ_OUT => mux_next_READ,
COMB_READ_IN => '1',
- COMB_DATA_IN => current_mux_buffer(BUS_WIDTH-1 downto 0),
- COMB_PACKET_NUM_IN => current_mux_buffer(BUS_WIDTH+1 downto BUS_WIDTH),
+ COMB_DATA_IN => current_mux_buffer(DATA_WIDTH-1 downto 0),
+ COMB_PACKET_NUM_IN => current_mux_buffer(DATA_WIDTH+1 downto DATA_WIDTH),
SYN_DATAREADY_OUT => MED_DATAREADY_OUT,
SYN_DATA_OUT => MED_DATA_OUT,
SYN_PACKET_NUM_OUT => MED_PACKET_NUM_OUT,
SYN_READ_IN => MED_READ_IN
);
- genmux : if MULT_WIDTH /= 95 generate
+ genmux : if MUX_WIDTH /= 95 generate
process (current_INT_READ_OUT, INT_DATA_IN, INT_PACKET_NUM_IN)
- variable var_mux_buffer : STD_LOGIC_VECTOR (BUS_WIDTH+2-1 downto 0);
+ variable var_mux_buffer : STD_LOGIC_VECTOR (DATA_WIDTH+2-1 downto 0);
begin
var_mux_buffer := (others => '0');
- for i in 0 to 2**MULT_WIDTH-1 loop
+ for i in 0 to 2**MUX_WIDTH-1 loop
if current_INT_READ_OUT(i) = '1' then
- var_mux_buffer(BUS_WIDTH-1 downto 0)
- := var_mux_buffer(BUS_WIDTH-1 downto 0) or INT_DATA_IN((BUS_WIDTH)*(i+1)-1 downto (BUS_WIDTH)*(i));
- var_mux_buffer(BUS_WIDTH+1 downto BUS_WIDTH)
- := var_mux_buffer(BUS_WIDTH+1 downto BUS_WIDTH) or INT_PACKET_NUM_IN(2*(i+1)-1 downto 2*i);
+ var_mux_buffer(DATA_WIDTH-1 downto 0)
+ := var_mux_buffer(DATA_WIDTH-1 downto 0) or INT_DATA_IN((DATA_WIDTH)*(i+1)-1 downto (DATA_WIDTH)*(i));
+ var_mux_buffer(DATA_WIDTH+1 downto DATA_WIDTH)
+ := var_mux_buffer(DATA_WIDTH+1 downto DATA_WIDTH) or INT_PACKET_NUM_IN(2*(i+1)-1 downto 2*i);
if INT_PACKET_NUM_IN(2*(i+1)-1 downto 2*i) = "00" then
- var_mux_buffer(3+MULT_WIDTH-1 downto 3)
- := conv_std_logic_vector(i, MULT_WIDTH);
+ var_mux_buffer(3+MUX_WIDTH-1 downto 3)
+ := conv_std_logic_vector(i, MUX_WIDTH);
end if;
end if;
end loop;
end process;
end generate;
- genmux3: if MULT_WIDTH = 95 generate
+ genmux3: if MUX_WIDTH = 95 generate
process (current_INT_READ_OUT, INT_DATA_IN, INT_PACKET_NUM_IN)
- variable var_mux_buffer : STD_LOGIC_VECTOR (BUS_WIDTH+2-1 downto 0);
+ variable var_mux_buffer : STD_LOGIC_VECTOR (DATA_WIDTH+2-1 downto 0);
begin
- for i in 0 to BUS_WIDTH-1 loop
- current_mux_buffer(i) <= (INT_DATA_IN((BUS_WIDTH)*(0)+i) and current_INT_READ_OUT(0)) or
- (INT_DATA_IN((BUS_WIDTH)*(1)+i) and current_INT_READ_OUT(1)) or
- (INT_DATA_IN((BUS_WIDTH)*(2)+i) and current_INT_READ_OUT(2)) or
- (INT_DATA_IN((BUS_WIDTH)*(3)+i) and current_INT_READ_OUT(3)) or
- (INT_DATA_IN((BUS_WIDTH)*(4)+i) and current_INT_READ_OUT(4)) or
- (INT_DATA_IN((BUS_WIDTH)*(5)+i) and current_INT_READ_OUT(5)) or
- (INT_DATA_IN((BUS_WIDTH)*(6)+i) and current_INT_READ_OUT(6)) or
- (INT_DATA_IN((BUS_WIDTH)*(7)+i) and current_INT_READ_OUT(7));
+ for i in 0 to DATA_WIDTH-1 loop
+ current_mux_buffer(i) <= (INT_DATA_IN((DATA_WIDTH)*(0)+i) and current_INT_READ_OUT(0)) or
+ (INT_DATA_IN((DATA_WIDTH)*(1)+i) and current_INT_READ_OUT(1)) or
+ (INT_DATA_IN((DATA_WIDTH)*(2)+i) and current_INT_READ_OUT(2)) or
+ (INT_DATA_IN((DATA_WIDTH)*(3)+i) and current_INT_READ_OUT(3)) or
+ (INT_DATA_IN((DATA_WIDTH)*(4)+i) and current_INT_READ_OUT(4)) or
+ (INT_DATA_IN((DATA_WIDTH)*(5)+i) and current_INT_READ_OUT(5)) or
+ (INT_DATA_IN((DATA_WIDTH)*(6)+i) and current_INT_READ_OUT(6)) or
+ (INT_DATA_IN((DATA_WIDTH)*(7)+i) and current_INT_READ_OUT(7));
end loop;
- current_mux_buffer(BUS_WIDTH) <= (INT_PACKET_NUM_IN(0) and current_INT_READ_OUT(0)) or
+ current_mux_buffer(DATA_WIDTH) <= (INT_PACKET_NUM_IN(0) and current_INT_READ_OUT(0)) or
(INT_PACKET_NUM_IN(2) and current_INT_READ_OUT(1)) or
(INT_PACKET_NUM_IN(4) and current_INT_READ_OUT(2)) or
(INT_PACKET_NUM_IN(6) and current_INT_READ_OUT(3)) or
(INT_PACKET_NUM_IN(10) and current_INT_READ_OUT(5)) or
(INT_PACKET_NUM_IN(12) and current_INT_READ_OUT(6)) or
(INT_PACKET_NUM_IN(14) and current_INT_READ_OUT(7));
- current_mux_buffer(BUS_WIDTH+1) <= (INT_PACKET_NUM_IN(1) and current_INT_READ_OUT(0)) or
+ current_mux_buffer(DATA_WIDTH+1) <= (INT_PACKET_NUM_IN(1) and current_INT_READ_OUT(0)) or
(INT_PACKET_NUM_IN(3) and current_INT_READ_OUT(1)) or
(INT_PACKET_NUM_IN(5) and current_INT_READ_OUT(2)) or
(INT_PACKET_NUM_IN(7) and current_INT_READ_OUT(3)) or
-- build the registers according to the wiki page
- STAT_INIT_BUFFER(11 downto 0) <= INITIBUF_stat_buffer(11 downto 0);
+ STAT_INIT_BUFFER(8 downto 0) <= INITIBUF_stat_buffer(8 downto 0);
+ STAT_INIT_BUFFER(11 downto 9) <= INITOBUF_stat_buffer(17 downto 15);
STAT_INIT_BUFFER(15 downto 14) <= INITOBUF_stat_buffer(1 downto 0);
STAT_INIT_BUFFER(31 downto 16) <= INITOBUF_stat_buffer(31 downto 16);
STAT_REPLY_BUFFER(11 downto 0) <= REPLYIBUF_stat_buffer(11 downto 0);
entity trb_net16_obuf is
generic (
- DATA_COUNT_WIDTH : integer := 5
+ DATA_COUNT_WIDTH : integer range 1 to 7 := 5 -- max used buffer size is 2**DATA_COUNT_WIDTH.
);
port(
-- Misc
send_ACK <= SEND_ACK_IN or reg_SEND_ACK_IN;
send_DATA <= not TRANSMITTED_BUFFERS(1);--'1' when (TRANSMITTED_BUFFERS(1) = '0') else '0';
+
+ --only for full obuf
send_EOB <= '1' when (CURRENT_DATA_COUNT = max_DATA_COUNT_minus_one) else '0';
+
-- buffer registers
STAT_BUFFER(1 downto 0) <= TRANSMITTED_BUFFERS;
- STAT_BUFFER(15 downto 2) <= (others => '0');
+ STAT_BUFFER(14 downto 2) <= (others => '0');
+ STAT_BUFFER(15) <= send_DATA;
STAT_BUFFER(20 downto 16) <= CURRENT_DATA_COUNT;
STAT_BUFFER(31 downto 21) <= (others => '0');
SEND_BUFFER_SIZE_IN <= CTRL_BUFFER(3 downto 0);
if rising_edge(CLK) then
if RESET = '1' then
saved_packet_type <= TYPE_ILLEGAL;
- elsif transfer_counter <= "00" and comb_dataready = '1' then
+ elsif transfer_counter = "00" and comb_dataready = '1' then
saved_packet_type <= current_output_data_buffer(2 downto 0);
end if;
end if;
reg_INT_READ_OUT, reg_SEND_ACK_IN, saved_packet_type,
current_DATA_word, send_ACK, send_EOB, sbuf_free,
current_ACK_word, current_EOB_word,
- max_DATA_COUNT_minus_two, next_TRANSMITTED_BUFFERS)
+ next_TRANSMITTED_BUFFERS)
begin
current_output_data_buffer <= current_NOP_word;
if (reg_INT_READ_OUT = '1' and INT_DATAREADY_IN = '1') then
--can only happen if idle or sending_data
- if send_EOB = '0' then
- current_output_data_buffer <= current_DATA_word;
- else
+ if send_EOB = '1' then
current_output_data_buffer <= current_EOB_word;
+ else
+ current_output_data_buffer <= current_DATA_word;
end if;
comb_dataready <= '1'; --I hope sbuf can store
if transfer_counter = "11" then
if saved_packet_type = TYPE_TRM or saved_packet_type = TYPE_EOB then --TRM means EOB
next_DATA_COUNT <= (others => '0');
increase_TRANSMITTED_BUFFERS <= '1';
+ if TRANSMITTED_BUFFERS(0) = '1' then
+ next_INT_READ_OUT <= '0';
+ end if;
else
next_DATA_COUNT <= CURRENT_DATA_COUNT +1;
end if;
end if;
end if;
end if;
- if next_TRANSMITTED_BUFFERS(1) = '1' or sbuf_free = '0' then
+ if sbuf_free = '0' or send_DATA = '0' then
next_INT_READ_OUT <= '0';
end if;
-------------
---old
--- if (reg_INT_READ_OUT = '1' and INT_DATAREADY_IN = '1') then
--- --can only happen if idle or sending_data
--- current_output_data_buffer <= current_DATA_word;
--- comb_dataready <= '1'; --I hope sbuf can store
--- if transfer_counter = "11" then
--- if saved_packet_type = TYPE_TRM then --TRM means EOB
--- next_DATA_COUNT <= (others => '0');
--- increase_TRANSMITTED_BUFFERS <= '1';
--- else
--- next_DATA_COUNT <= CURRENT_DATA_COUNT +1;
--- end if;
--- if (send_ACK = '1' or send_EOB = '1' ) then
--- next_INT_READ_OUT <= '0';
--- end if;
--- end if;
--- if send_ACK = '1' then --BUGBUG: next_SEND_ACK_IN should be a counter (2 may arrive)
--- --no real problem due to same speed of transmission
--- next_SEND_ACK_IN <= '1';
--- end if;
--- elsif (send_ACK = '1') then
--- next_INT_READ_OUT <= '0';
--- current_output_data_buffer <= current_ACK_word;
--- if sbuf_free = '1' then
--- comb_dataready <= '1';
--- if (transfer_counter = "11") then
--- next_SEND_ACK_IN <= '0';
--- end if;
--- end if;
--- elsif send_EOB = '1' then
--- next_INT_READ_OUT <= '0';
--- current_output_data_buffer <= current_EOB_word;
--- if sbuf_free = '1' then
--- comb_dataready <= '1';
--- if (transfer_counter = "11") then
--- next_DATA_COUNT <= (others => '0');
--- increase_TRANSMITTED_BUFFERS <= '1';
--- end if;
--- end if;
--- end if;
--- if --block reading if two buffers have been sent or current buffer runs full
--- ((current_DATA_COUNT(DATA_COUNT_WIDTH-1 downto 0) = (max_DATA_COUNT_minus_two(DATA_COUNT_WIDTH-1 downto 0)))
--- and reg_INT_READ_OUT = '1' and INT_DATAREADY_IN = '1' and transfer_counter = "11")
--- --long version of (next_count = max_count-1)
--- or (next_TRANSMITTED_BUFFERS(1) = '1')
--- or sbuf_free = '0' then
--- next_INT_READ_OUT <= '0';
--- end if;
-
---end old
-----------
+
end process;
end if;
end process;
- next_max_DATA_COUNT_minus_one <= "00011" when REC_BUFFER_SIZE_IN="0001" else
- "00111" when REC_BUFFER_SIZE_IN="0010" else
- "01111" when REC_BUFFER_SIZE_IN="0011" else
- "11111" when REC_BUFFER_SIZE_IN="0100" else
- "00001";
- next_max_DATA_COUNT_minus_two(0) <= '0';
--- next_max_DATA_COUNT_minus_two(DATA_COUNT_WIDTH-1 downto 1)
--- <= next_max_DATA_COUNT_minus_one(DATA_COUNT_WIDTH-1 downto 1);
-
--- next_max_DATA_COUNT_minus_one <= "0000000000000011" when REC_BUFFER_SIZE_IN="0001" else
--- "0000000000000111" when REC_BUFFER_SIZE_IN="0010" else
--- "0000000000001111" when REC_BUFFER_SIZE_IN="0011" else
--- "0000000000011111" when REC_BUFFER_SIZE_IN="0100" else
--- "0000000000000001";
--- next_max_DATA_COUNT_minus_two <= "0000000000000010" when REC_BUFFER_SIZE_IN="0001" else
--- "0000000000000110" when REC_BUFFER_SIZE_IN="0010" else
--- "0000000000001110" when REC_BUFFER_SIZE_IN="0011" else
--- "0000000000011110" when REC_BUFFER_SIZE_IN="0100" else
--- "0000000000000000";
-
- reg_max_DATA_COUNT : process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- max_DATA_COUNT_minus_one(0) <= '1';
- max_DATA_COUNT_minus_one(DATA_COUNT_WIDTH-1 downto 1) <= (others => '0');
--- max_DATA_COUNT_minus_two(DATA_COUNT_WIDTH-1 downto 0) <= (others => '0');
- else
- max_DATA_COUNT_minus_one <= next_max_DATA_COUNT_minus_one(DATA_COUNT_WIDTH-1 downto 0);
--- max_DATA_COUNT_minus_two <= next_max_DATA_COUNT_minus_two(DATA_COUNT_WIDTH-1 downto 0);
+ next_max_DATA_COUNT_minus_one <=
+ conv_std_logic_vector(3, DATA_COUNT_WIDTH) when REC_BUFFER_SIZE_IN="0010" else
+ conv_std_logic_vector(7, DATA_COUNT_WIDTH) when REC_BUFFER_SIZE_IN="0011" else
+ (others => '1') when REC_BUFFER_SIZE_IN(3 downto 1)="011" else --this is bram or infty
+ conv_std_logic_vector(1, DATA_COUNT_WIDTH);
+
+ reg_max_DATA_COUNT : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ max_DATA_COUNT_minus_one(0) <= '1';
+ max_DATA_COUNT_minus_one(DATA_COUNT_WIDTH-1 downto 1) <= (others => '0');
+ else
+ max_DATA_COUNT_minus_one <= next_max_DATA_COUNT_minus_one(DATA_COUNT_WIDTH-1 downto 0);
+ end if;
end if;
- end if;
- end process;
+ end process;
comb_TRANSMITTED_BUFFERS : process (increase_TRANSMITTED_BUFFERS, decrease_TRANSMITTED_BUFFERS, TRANSMITTED_BUFFERS)
begin
--- /dev/null
+-- this is just a terminator, which auto-answers requests. Answer is a TRM only.
+
+-- only to be used on unused channels
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.std_logic_ARITH.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+
+use work.trb_net_std.all;
+
+
+entity trb_net16_term_buf is
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+
+ MED_INIT_DATAREADY_OUT: out std_logic;
+ MED_INIT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word
+ MED_INIT_PACKET_NUM_OUT: out std_logic_vector (1 downto 0);
+ MED_INIT_READ_IN: in std_logic;
+
+ MED_INIT_DATAREADY_IN: in std_logic;
+ MED_INIT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word
+ MED_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
+ MED_INIT_READ_OUT: out std_logic;
+
+ MED_REPLY_DATAREADY_OUT: out std_logic;
+ MED_REPLY_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word
+ MED_REPLY_PACKET_NUM_OUT: out std_logic_vector (1 downto 0);
+ MED_REPLY_READ_IN: in std_logic;
+
+ MED_REPLY_DATAREADY_IN: in std_logic;
+ MED_REPLY_DATA_IN: in std_logic_vector (15 downto 0); -- Data word
+ MED_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
+ MED_REPLY_READ_OUT: out std_logic
+ );
+end entity;
+
+architecture trb_net16_term_buf_arch of trb_net16_term_buf is
+
+ signal INIT_SEQNR, next_INIT_SEQNR : std_logic_vector(7 downto 0);
+ signal INIT_saved_packet_type : std_logic_vector(2 downto 0);
+ signal INIT_transfer_counter : std_logic_vector(1 downto 0);
+ signal buf_MED_INIT_DATAREADY_OUT, next_MED_INIT_DATAREADY_OUT : std_logic;
+ signal buf_MED_INIT_DATA_OUT, next_MED_INIT_DATA_OUT : std_logic_vector(15 downto 0);
+ signal buf_MED_INIT_PACKET_NUM_OUT : std_logic_vector(1 downto 0);
+ signal send_INIT_ack : std_logic;
+ signal next_send_INIT_ack : std_logic;
+ signal sent_INIT_ack : std_logic;
+
+ signal REPLY_saved_packet_type : std_logic_vector(2 downto 0);
+ signal REPLY_transfer_counter : std_logic_vector(1 downto 0);
+ signal buf_MED_REPLY_DATAREADY_OUT, next_MED_REPLY_DATAREADY_OUT : std_logic;
+ signal buf_MED_REPLY_DATA_OUT, next_MED_REPLY_DATA_OUT : std_logic_vector(15 downto 0);
+ signal buf_MED_REPLY_PACKET_NUM_OUT : std_logic_vector(1 downto 0);
+ signal send_REPLY_ack, send_REPLY_trm : std_logic;
+ signal next_send_REPLY_ack, next_send_REPLY_trm : std_logic;
+ signal sent_REPLY_ack, sent_REPLY_trm : std_logic;
+
+ signal sending_REPLY_ACK, next_sending_REPLY_ACK : std_logic;
+begin
+ MED_INIT_READ_OUT <= '1';
+ MED_REPLY_READ_OUT <= '1';
+
+ process(MED_INIT_DATAREADY_IN, MED_INIT_PACKET_NUM_IN, MED_INIT_DATA_IN,
+ MED_REPLY_DATAREADY_IN, MED_REPLY_PACKET_NUM_IN, MED_REPLY_DATA_IN,
+ send_INIT_ack, send_REPLY_ack, send_REPLY_trm, sending_REPLY_ACK,
+ REPLY_transfer_counter, REPLY_saved_packet_type, MED_INIT_READ_IN,
+ INIT_SEQNR, INIT_transfer_counter, INIT_saved_packet_type, MED_REPLY_READ_IN)
+ begin
+ sent_INIT_ack <= '0';
+ sent_REPLY_ack <= '0';
+ sent_REPLY_trm <= '0';
+ next_send_INIT_ack <= send_INIT_ack;
+ next_send_REPLY_ack <= send_REPLY_ack;
+ next_send_REPLY_trm <= send_REPLY_trm;
+ next_sending_REPLY_ACK <= sending_REPLY_ACK;
+ next_MED_INIT_DATA_OUT <= "0000000000000111";
+ next_MED_INIT_DATAREADY_OUT <= '0';
+ next_MED_REPLY_DATA_OUT <= "0000000000000111";
+ next_MED_REPLY_DATAREADY_OUT <= '0';
+
+ next_INIT_SEQNR <= INIT_SEQNR;
+
+ --output INIT data
+ if send_INIT_ack = '1' then
+ next_MED_INIT_DATAREADY_OUT <= '1';
+ --next_MED_DATA_OUT <= ;
+ if INIT_transfer_counter = "00" then
+ next_MED_INIT_DATA_OUT(2 downto 0) <= TYPE_ACK;
+ elsif INIT_transfer_counter = "10" then
+ next_MED_INIT_DATA_OUT(3 downto 0) <= "0111";
+ elsif INIT_transfer_counter = "11" then
+ if MED_INIT_READ_IN = '1' then
+ next_send_REPLY_ack <= '1';
+ end if;
+ end if;
+ end if;
+ --output REPLY data
+ if send_REPLY_ack = '1' or sending_REPLY_ACK = '1' then
+ next_MED_REPLY_DATAREADY_OUT <= '1';
+ next_sending_REPLY_ACK <= '1';
+ if REPLY_transfer_counter = "00" then
+ sent_REPLY_ack <= '1';
+ next_MED_REPLY_DATA_OUT(2 downto 0) <= TYPE_ACK;
+ elsif REPLY_transfer_counter = "10" then
+ next_MED_REPLY_DATA_OUT(3 downto 0) <= "0111";
+ elsif REPLY_transfer_counter = "11" then
+ if MED_REPLY_READ_IN = '1' then
+ next_sending_REPLY_ACK <= '0';
+ end if;
+ end if;
+ elsif send_REPLY_trm = '1' then
+ next_MED_REPLY_DATAREADY_OUT <= '1';
+ next_MED_REPLY_DATA_OUT <= (others => '0');
+ if REPLY_transfer_counter = "00" then
+ next_MED_REPLY_DATA_OUT(2 downto 0) <= TYPE_TRM;
+ elsif REPLY_transfer_counter = "11" then
+ next_MED_REPLY_DATA_OUT(11 downto 4) <= INIT_SEQNR;
+ next_MED_REPLY_DATA_OUT(3 downto 0) <= "0000";
+ sent_REPLY_trm <= '1';
+ end if;
+ end if;
+
+ -- input data
+ if MED_INIT_DATAREADY_IN = '1' then
+ if MED_INIT_PACKET_NUM_IN = "11" then
+ if INIT_saved_packet_type = TYPE_EOB then
+ next_send_INIT_ack <= '1';
+ end if;
+ if INIT_saved_packet_type = TYPE_TRM then
+ next_send_INIT_ack <= '1';
+ next_send_REPLY_trm <= '1';
+ next_INIT_SEQNR <= MED_INIT_DATA_IN(11 downto 4);
+ end if;
+ end if;
+ end if;
+
+ if MED_REPLY_DATAREADY_IN = '1' then
+ if MED_REPLY_PACKET_NUM_IN = "11" then
+ if REPLY_saved_packet_type = TYPE_EOB or REPLY_saved_packet_type = TYPE_TRM then
+ next_send_REPLY_ack <= '1';
+ end if;
+ end if;
+ end if;
+ end process;
+
+ --count packets
+ REG_INIT_TRANSFER_COUNTER : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ INIT_transfer_counter <= (others => '0');
+ elsif buf_MED_INIT_DATAREADY_OUT = '1' and MED_INIT_READ_IN = '1' then
+ INIT_transfer_counter <= INIT_transfer_counter + 1;
+ end if;
+ end if;
+ end process;
+
+ REG_REPLY_TRANSFER_COUNTER : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ REPLY_transfer_counter <= (others => '0');
+ elsif buf_MED_REPLY_DATAREADY_OUT = '1' and MED_REPLY_READ_IN = '1' then
+ REPLY_transfer_counter <= REPLY_transfer_counter + 1;
+ end if;
+ end if;
+ end process;
+
+ MED_REPLY_DATAREADY_OUT <= buf_MED_REPLY_DATAREADY_OUT;
+ MED_REPLY_DATA_OUT <= buf_MED_REPLY_DATA_OUT;
+ MED_REPLY_PACKET_NUM_OUT <= buf_MED_REPLY_PACKET_NUM_OUT;
+ MED_INIT_DATAREADY_OUT <= buf_MED_INIT_DATAREADY_OUT;
+ MED_INIT_DATA_OUT <= buf_MED_INIT_DATA_OUT;
+ MED_INIT_PACKET_NUM_OUT <= buf_MED_INIT_PACKET_NUM_OUT;
+
+ MED_INIT_OUT_REG: process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ buf_MED_INIT_DATA_OUT <= (others => '0');
+ buf_MED_INIT_PACKET_NUM_OUT <= "00";
+ buf_MED_INIT_DATAREADY_OUT <= '0';
+ else
+ buf_MED_INIT_DATA_OUT <= next_MED_INIT_DATA_OUT;
+ buf_MED_INIT_PACKET_NUM_OUT <= INIT_transfer_counter;
+ buf_MED_INIT_DATAREADY_OUT <= next_MED_INIT_DATAREADY_OUT;
+ end if;
+ end if;
+ end process;
+
+ MED_REPLY_OUT_REG: process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ buf_MED_REPLY_DATA_OUT <= (others => '0');
+ buf_MED_REPLY_PACKET_NUM_OUT <= "00";
+ buf_MED_REPLY_DATAREADY_OUT <= '0';
+ else
+ buf_MED_REPLY_DATA_OUT <= next_MED_REPLY_DATA_OUT;
+ buf_MED_REPLY_PACKET_NUM_OUT <= REPLY_transfer_counter;
+ buf_MED_REPLY_DATAREADY_OUT <= next_MED_REPLY_DATAREADY_OUT;
+ end if;
+ end if;
+ end process;
+
+
+ process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ send_REPLY_trm <= '0';
+ send_REPLY_ack <= '0';
+ send_INIT_ack <= '0';
+ sending_REPLY_ACK <= '0';
+ INIT_SEQNR <= (others => '0');
+ else
+ send_REPLY_trm <= next_send_REPLY_trm and not sent_REPLY_trm;
+ send_REPLY_ack <= next_send_REPLY_ack and not sent_REPLY_ack;
+ send_INIT_ack <= next_send_INIT_ack and not sent_INIT_ack;
+ sending_REPLY_ACK <= next_sending_REPLY_ACK;
+ INIT_SEQNR <= next_INIT_SEQNR;
+ end if;
+ end if;
+ end process;
+
+ --this holds the current packet type
+ process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ INIT_saved_packet_type <= "111";
+ elsif MED_INIT_PACKET_NUM_IN = "00" then
+ INIT_saved_packet_type <= MED_INIT_DATA_IN(2 downto 0);
+ end if;
+ end if;
+ end process;
+ process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ REPLY_saved_packet_type <= "111";
+ elsif MED_REPLY_PACKET_NUM_IN = "00" then
+ REPLY_saved_packet_type <= MED_REPLY_DATA_IN(2 downto 0);
+ end if;
+ end if;
+ end process;
+end architecture;
DAT_REPLY_DEPTH : integer range 0 to 7 := 0; --passive api doesn't need a fifo here
DAT_FIFO_TO_INT_DEPTH : integer range 0 to 7 := 1;
DAT_FIFO_TO_APL_DEPTH : integer range 0 to 7 := 1;
- DAT_FIFO_TERM_BUFFER_DEPTH : integer range 0 to 7 := 0;
--SBUF_DATA_VERSION : integer range 0 to 1 := 0;
--Fifo for TRG channel
TRG_INIT_DEPTH : integer range 0 to 7 := 0;
TRG_REPLY_DEPTH : integer range 0 to 7 := 0;
- TRG_FIFO_TERM_BUFFER_DEPTH : integer range 0 to 7 := 0;
TRG_SECURE_MODE : integer range 0 to 1 := 0;
--SBUF_TRG_VERSION : integer range 0 to 1 := 0;
--Multiplexer
- MULT_WIDTH : integer range 1 to 5 := 3;
- TRG_CHANNEL : integer range 0 to 2**(MULT_WIDTH-1) := 0;
- DAT_CHANNEL : integer range 0 to 2**(MULT_WIDTH-1) := 2;
+ MUX_WIDTH : integer range 1 to 5 := 3;
+ MUX_SECURE_MODE : integer range 0 to 1 := 0;
+ TRG_CHANNEL : integer range 0 to 2**(MUX_WIDTH-1) := 0;
+ DAT_CHANNEL : integer range 0 to 2**(MUX_WIDTH-1) := 2;
--General
- BUS_WIDTH : integer range 16 to 16 := 16;
- NUM_WIDTH : integer range 2 to 2 := 2
+ DATA_WIDTH : integer range 16 to 16 := 16;
+ NUM_WIDTH : integer range 2 to 2 := 2
);
port(
end component;
component trb_net16_io_multiplexer is
-
- generic (BUS_WIDTH : integer := 16;
- MULT_WIDTH : integer := 3);
-
+ generic (
+ DATA_WIDTH : integer := 16;
+ NUM_WIDTH : integer := 2;
+ MUX_WIDTH : integer range 1 to 5 := 3;
+ MUX_SECURE_MODE : integer range 0 to 1 := 0 --use sbufs or not?
+ );
port(
-- Misc
- CLK : in std_logic;
- RESET : in std_logic;
+ CLK : in std_logic;
+ RESET : in std_logic;
CLK_EN : in std_logic;
-- Media direction port
MED_DATAREADY_IN: in std_logic;
- MED_DATA_IN: in std_logic_vector (BUS_WIDTH-1 downto 0);
- -- highest bits are mult.
- MED_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
+ MED_DATA_IN: in std_logic_vector (DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_IN: in std_logic_vector (NUM_WIDTH-1 downto 0);
MED_READ_OUT: out std_logic;
-
MED_DATAREADY_OUT: out std_logic;
- MED_DATA_OUT: out std_logic_vector (BUS_WIDTH-1 downto 0);
- MED_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
+ MED_DATA_OUT: out std_logic_vector (DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_OUT:out std_logic_vector (NUM_WIDTH-1 downto 0);
MED_READ_IN: in std_logic;
-
-- Internal direction port
- INT_DATAREADY_OUT: out std_logic_vector (2**MULT_WIDTH-1 downto 0);
- INT_DATA_OUT: out std_logic_vector ((BUS_WIDTH)*(2**MULT_WIDTH)-1 downto 0);
- INT_PACKET_NUM_OUT:out std_logic_vector (2*(2**MULT_WIDTH)-1 downto 0);
- INT_READ_IN: in std_logic_vector (2**MULT_WIDTH-1 downto 0);
-
- INT_DATAREADY_IN: in std_logic_vector (2**MULT_WIDTH-1 downto 0);
- INT_DATA_IN: in std_logic_vector ((BUS_WIDTH)*(2**MULT_WIDTH)-1 downto 0);
- INT_PACKET_NUM_IN: in std_logic_vector (2*(2**MULT_WIDTH)-1 downto 0);
- INT_READ_OUT: out std_logic_vector (2**MULT_WIDTH-1 downto 0);
-
+ INT_DATAREADY_OUT: out std_logic_vector (2**MUX_WIDTH-1 downto 0);
+ INT_DATA_OUT: out std_logic_vector ((DATA_WIDTH)*(2**MUX_WIDTH)-1 downto 0);
+ INT_PACKET_NUM_OUT:out std_logic_vector (2*(2**MUX_WIDTH)-1 downto 0);
+ INT_READ_IN: in std_logic_vector (2**MUX_WIDTH-1 downto 0);
+ INT_DATAREADY_IN: in std_logic_vector (2**MUX_WIDTH-1 downto 0);
+ INT_DATA_IN: in std_logic_vector ((DATA_WIDTH)*(2**MUX_WIDTH)-1 downto 0);
+ INT_PACKET_NUM_IN: in std_logic_vector (2*(2**MUX_WIDTH)-1 downto 0);
+ INT_READ_OUT: out std_logic_vector (2**MUX_WIDTH-1 downto 0);
-- Status and control port
CTRL: in std_logic_vector (31 downto 0);
STAT: out std_logic_vector (31 downto 0)
);
end component;
+ component trb_net16_term_buf is
+ port(
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ MED_INIT_DATAREADY_OUT: out std_logic;
+ MED_INIT_DATA_OUT: out std_logic_vector (15 downto 0);
+ MED_INIT_PACKET_NUM_OUT: out std_logic_vector (1 downto 0);
+ MED_INIT_READ_IN: in std_logic;
+ MED_INIT_DATAREADY_IN: in std_logic;
+ MED_INIT_DATA_IN: in std_logic_vector (15 downto 0);
+ MED_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
+ MED_INIT_READ_OUT: out std_logic;
+ MED_REPLY_DATAREADY_OUT: out std_logic;
+ MED_REPLY_DATA_OUT: out std_logic_vector (15 downto 0);
+ MED_REPLY_PACKET_NUM_OUT: out std_logic_vector (1 downto 0);
+ MED_REPLY_READ_IN: in std_logic;
+ MED_REPLY_DATAREADY_IN: in std_logic;
+ MED_REPLY_DATA_IN: in std_logic_vector (15 downto 0);
+ MED_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
+ MED_REPLY_READ_OUT: out std_logic
+ );
+ end component;
signal apl_to_buf_DAT_INIT_DATAREADY: std_logic;
-signal apl_to_buf_DAT_INIT_DATA : std_logic_vector (BUS_WIDTH-1 downto 0);
+signal apl_to_buf_DAT_INIT_DATA : std_logic_vector (DATA_WIDTH-1 downto 0);
signal apl_to_buf_DAT_INIT_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0);
signal apl_to_buf_DAT_INIT_READ : std_logic;
signal buf_to_apl_DAT_INIT_DATAREADY: std_logic;
-signal buf_to_apl_DAT_INIT_DATA : std_logic_vector (BUS_WIDTH-1 downto 0);
+signal buf_to_apl_DAT_INIT_DATA : std_logic_vector (DATA_WIDTH-1 downto 0);
signal buf_to_apl_DAT_INIT_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0);
signal buf_to_apl_DAT_INIT_READ : std_logic;
signal apl_to_buf_DAT_REPLY_DATAREADY: std_logic;
-signal apl_to_buf_DAT_REPLY_DATA : std_logic_vector (BUS_WIDTH-1 downto 0);
+signal apl_to_buf_DAT_REPLY_DATA : std_logic_vector (DATA_WIDTH-1 downto 0);
signal apl_to_buf_DAT_REPLY_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0);
signal apl_to_buf_DAT_REPLY_READ : std_logic;
signal buf_to_apl_DAT_REPLY_DATAREADY: std_logic;
-signal buf_to_apl_DAT_REPLY_DATA : std_logic_vector (BUS_WIDTH-1 downto 0);
+signal buf_to_apl_DAT_REPLY_DATA : std_logic_vector (DATA_WIDTH-1 downto 0);
signal buf_to_apl_DAT_REPLY_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0);
signal buf_to_apl_DAT_REPLY_READ : std_logic;
signal apl_to_buf_TRG_INIT_DATAREADY: std_logic;
-signal apl_to_buf_TRG_INIT_DATA : std_logic_vector (BUS_WIDTH-1 downto 0);
+signal apl_to_buf_TRG_INIT_DATA : std_logic_vector (DATA_WIDTH-1 downto 0);
signal apl_to_buf_TRG_INIT_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0);
signal apl_to_buf_TRG_INIT_READ : std_logic;
signal buf_to_apl_TRG_INIT_DATAREADY: std_logic;
-signal buf_to_apl_TRG_INIT_DATA : std_logic_vector (BUS_WIDTH-1 downto 0);
+signal buf_to_apl_TRG_INIT_DATA : std_logic_vector (DATA_WIDTH-1 downto 0);
signal buf_to_apl_TRG_INIT_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0);
signal buf_to_apl_TRG_INIT_READ : std_logic;
signal apl_to_buf_TRG_REPLY_DATAREADY: std_logic;
-signal apl_to_buf_TRG_REPLY_DATA : std_logic_vector (BUS_WIDTH-1 downto 0);
+signal apl_to_buf_TRG_REPLY_DATA : std_logic_vector (DATA_WIDTH-1 downto 0);
signal apl_to_buf_TRG_REPLY_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0);
signal apl_to_buf_TRG_REPLY_READ : std_logic;
signal buf_to_apl_TRG_REPLY_DATAREADY: std_logic;
-signal buf_to_apl_TRG_REPLY_DATA : std_logic_vector (BUS_WIDTH-1 downto 0);
+signal buf_to_apl_TRG_REPLY_DATA : std_logic_vector (DATA_WIDTH-1 downto 0);
signal buf_to_apl_TRG_REPLY_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0);
signal buf_to_apl_TRG_REPLY_READ : std_logic;
-- for the connection to the multiplexer
signal MED_DAT_INIT_DATAREADY_OUT : std_logic;
-signal MED_DAT_INIT_DATA_OUT : std_logic_vector (BUS_WIDTH-1 downto 0);
+signal MED_DAT_INIT_DATA_OUT : std_logic_vector (DATA_WIDTH-1 downto 0);
signal MED_DAT_INIT_PACKET_NUM_OUT : std_logic_vector (NUM_WIDTH-1 downto 0);
signal MED_DAT_INIT_READ_IN : std_logic;
signal MED_DAT_INIT_DATAREADY_IN : std_logic;
-signal MED_DAT_INIT_DATA_IN : std_logic_vector (BUS_WIDTH-1 downto 0);
+signal MED_DAT_INIT_DATA_IN : std_logic_vector (DATA_WIDTH-1 downto 0);
signal MED_DAT_INIT_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH-1 downto 0);
signal MED_DAT_INIT_READ_OUT : std_logic;
signal MED_DAT_REPLY_DATAREADY_OUT : std_logic;
-signal MED_DAT_REPLY_DATA_OUT : std_logic_vector (BUS_WIDTH-1 downto 0);
+signal MED_DAT_REPLY_DATA_OUT : std_logic_vector (DATA_WIDTH-1 downto 0);
signal MED_DAT_REPLY_PACKET_NUM_OUT : std_logic_vector (NUM_WIDTH-1 downto 0);
signal MED_DAT_REPLY_READ_IN : std_logic;
signal MED_DAT_REPLY_DATAREADY_IN : std_logic;
-signal MED_DAT_REPLY_DATA_IN : std_logic_vector (BUS_WIDTH-1 downto 0);
+signal MED_DAT_REPLY_DATA_IN : std_logic_vector (DATA_WIDTH-1 downto 0);
signal MED_DAT_REPLY_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH-1 downto 0);
signal MED_DAT_REPLY_READ_OUT : std_logic;
signal MED_TRG_INIT_DATAREADY_OUT : std_logic;
-signal MED_TRG_INIT_DATA_OUT : std_logic_vector (BUS_WIDTH-1 downto 0);
+signal MED_TRG_INIT_DATA_OUT : std_logic_vector (DATA_WIDTH-1 downto 0);
signal MED_TRG_INIT_PACKET_NUM_OUT : std_logic_vector (NUM_WIDTH-1 downto 0);
signal MED_TRG_INIT_READ_IN : std_logic;
signal MED_TRG_INIT_DATAREADY_IN : std_logic;
-signal MED_TRG_INIT_DATA_IN : std_logic_vector (BUS_WIDTH-1 downto 0);
+signal MED_TRG_INIT_DATA_IN : std_logic_vector (DATA_WIDTH-1 downto 0);
signal MED_TRG_INIT_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH-1 downto 0);
signal MED_TRG_INIT_READ_OUT : std_logic;
signal MED_TRG_REPLY_DATAREADY_OUT : std_logic;
-signal MED_TRG_REPLY_DATA_OUT : std_logic_vector (BUS_WIDTH-1 downto 0);
+signal MED_TRG_REPLY_DATA_OUT : std_logic_vector (DATA_WIDTH-1 downto 0);
signal MED_TRG_REPLY_PACKET_NUM_OUT : std_logic_vector (NUM_WIDTH-1 downto 0);
signal MED_TRG_REPLY_READ_IN : std_logic;
signal MED_TRG_REPLY_DATAREADY_IN : std_logic;
-signal MED_TRG_REPLY_DATA_IN : std_logic_vector (BUS_WIDTH-1 downto 0);
+signal MED_TRG_REPLY_DATA_IN : std_logic_vector (DATA_WIDTH-1 downto 0);
signal MED_TRG_REPLY_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH-1 downto 0);
signal MED_TRG_REPLY_READ_OUT : std_logic;
-signal m_DATAREADY_OUT : std_logic_vector (2**MULT_WIDTH-1 downto 0);
-signal m_DATA_OUT : std_logic_vector (BUS_WIDTH*2**MULT_WIDTH-1 downto 0);
-signal m_PACKET_NUM_OUT: std_logic_vector (NUM_WIDTH*2**MULT_WIDTH-1 downto 0);
-signal m_READ_IN : std_logic_vector (2**MULT_WIDTH-1 downto 0);
+signal m_DATAREADY_OUT : std_logic_vector (2**MUX_WIDTH-1 downto 0);
+signal m_DATA_OUT : std_logic_vector (DATA_WIDTH*2**MUX_WIDTH-1 downto 0);
+signal m_PACKET_NUM_OUT: std_logic_vector (NUM_WIDTH*2**MUX_WIDTH-1 downto 0);
+signal m_READ_IN : std_logic_vector (2**MUX_WIDTH-1 downto 0);
-signal m_DATAREADY_IN : std_logic_vector (2**MULT_WIDTH-1 downto 0);
-signal m_DATA_IN : std_logic_vector (BUS_WIDTH**MULT_WIDTH-1 downto 0);
-signal m_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH*2**MULT_WIDTH-1 downto 0);
-signal m_READ_OUT : std_logic_vector (2**MULT_WIDTH-1 downto 0);
+signal m_DATAREADY_IN : std_logic_vector (2**MUX_WIDTH-1 downto 0);
+signal m_DATA_IN : std_logic_vector (DATA_WIDTH**MUX_WIDTH-1 downto 0);
+signal m_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH*2**MUX_WIDTH-1 downto 0);
+signal m_READ_OUT : std_logic_vector (2**MUX_WIDTH-1 downto 0);
begin
--Connections for data and trigger channel
- genmuxcon : for i in 0 to 2**(MULT_WIDTH-1)-1 generate
+ genmuxcon : for i in 0 to 2**(MUX_WIDTH-1)-1 generate
gendat: if i = DAT_CHANNEL generate
m_DATAREADY_OUT(i*2) <= MED_DAT_INIT_DATAREADY_OUT;
m_DATAREADY_OUT(i*2+1) <= MED_DAT_REPLY_DATAREADY_OUT;
- m_DATA_OUT((i*2+1)*BUS_WIDTH-1 downto i*BUS_WIDTH*2) <= MED_DAT_INIT_DATA_OUT;
- m_DATA_OUT((i*2+2)*BUS_WIDTH-1 downto (i*2+1)*BUS_WIDTH) <= MED_DAT_REPLY_DATA_OUT;
+ m_DATA_OUT((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2) <= MED_DAT_INIT_DATA_OUT;
+ m_DATA_OUT((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH) <= MED_DAT_REPLY_DATA_OUT;
m_PACKET_NUM_OUT(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2) <= MED_DAT_INIT_PACKET_NUM_OUT;
m_PACKET_NUM_OUT(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2) <= MED_DAT_REPLY_PACKET_NUM_OUT;
MED_DAT_INIT_READ_IN <= m_READ_IN(i*2);
MED_DAT_REPLY_READ_IN <= m_READ_IN(i*2+1);
MED_DAT_INIT_DATAREADY_IN <= m_DATAREADY_IN(i*2);
MED_DAT_REPLY_DATAREADY_IN <= m_DATAREADY_IN(i*2+1);
- MED_DAT_INIT_DATA_IN <= m_DATA_IN((i*2+1)*BUS_WIDTH-1 downto i*BUS_WIDTH*2);
- MED_DAT_REPLY_DATA_IN <= m_DATA_IN((i*2+2)*BUS_WIDTH-1 downto (i*2+1)*BUS_WIDTH);
+ MED_DAT_INIT_DATA_IN <= m_DATA_IN((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2);
+ MED_DAT_REPLY_DATA_IN <= m_DATA_IN((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH);
MED_DAT_INIT_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2);
MED_DAT_REPLY_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2);
m_READ_OUT(i*2) <= MED_DAT_INIT_READ_OUT;
gentrg: if i = TRG_CHANNEL generate
m_DATAREADY_OUT(i*2) <= MED_TRG_INIT_DATAREADY_OUT;
m_DATAREADY_OUT(i*2+1) <= MED_TRG_REPLY_DATAREADY_OUT;
- m_DATA_OUT((i*2+1)*BUS_WIDTH-1 downto i*BUS_WIDTH*2) <= MED_TRG_INIT_DATA_OUT;
- m_DATA_OUT((i*2+2)*BUS_WIDTH-1 downto (i*2+1)*BUS_WIDTH) <= MED_TRG_REPLY_DATA_OUT;
+ m_DATA_OUT((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2) <= MED_TRG_INIT_DATA_OUT;
+ m_DATA_OUT((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH) <= MED_TRG_REPLY_DATA_OUT;
m_PACKET_NUM_OUT(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2) <= MED_TRG_INIT_PACKET_NUM_OUT;
m_PACKET_NUM_OUT(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2) <= MED_TRG_REPLY_PACKET_NUM_OUT;
MED_TRG_INIT_READ_IN <= m_READ_IN(i*2);
MED_TRG_REPLY_READ_IN <= m_READ_IN(i*2+1);
MED_TRG_INIT_DATAREADY_IN <= m_DATAREADY_IN(i*2);
MED_TRG_REPLY_DATAREADY_IN <= m_DATAREADY_IN(i*2+1);
- MED_TRG_INIT_DATA_IN <= m_DATA_IN((i*2+1)*BUS_WIDTH-1 downto i*BUS_WIDTH*2);
- MED_TRG_REPLY_DATA_IN <= m_DATA_IN((i*2+2)*BUS_WIDTH-1 downto (i*2+1)*BUS_WIDTH);
+ MED_TRG_INIT_DATA_IN <= m_DATA_IN((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2);
+ MED_TRG_REPLY_DATA_IN <= m_DATA_IN((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH);
MED_TRG_INIT_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2);
MED_TRG_REPLY_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2);
m_READ_OUT(i*2) <= MED_TRG_INIT_READ_OUT;
m_READ_OUT(i*2+1) <= MED_TRG_REPLY_READ_OUT;
end generate;
genelse: if i /= DAT_CHANNEL and i /= TRG_CHANNEL generate
- m_DATAREADY_OUT(i*2) <= '0';
- m_DATAREADY_OUT(i*2+1) <= '0';
- m_DATA_OUT((i*2+1)*BUS_WIDTH-1 downto i*BUS_WIDTH*2) <= (others => '0');
- m_DATA_OUT((i*2+2)*BUS_WIDTH-1 downto (i*2+1)*BUS_WIDTH) <= (others => '0');
- m_PACKET_NUM_OUT(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2) <= (others => '0');
- m_PACKET_NUM_OUT(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2) <= (others => '0');
- m_READ_OUT(i*2) <= '0';
- m_READ_OUT(i*2+1) <= '0';
+ termbuf: trb_net16_term_buf
+ port map(
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+ MED_INIT_DATAREADY_OUT => m_DATAREADY_OUT(i*2),
+ MED_INIT_DATA_OUT => m_DATA_OUT((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2),
+ MED_INIT_PACKET_NUM_OUT => m_PACKET_NUM_OUT(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2),
+ MED_INIT_READ_IN => m_READ_IN(i*2),
+ MED_INIT_DATAREADY_IN => m_DATAREADY_IN(i*2),
+ MED_INIT_DATA_IN => m_DATA_IN((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2),
+ MED_INIT_PACKET_NUM_IN => m_PACKET_NUM_IN(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2),
+ MED_INIT_READ_OUT => m_READ_OUT(i*2),
+
+ MED_REPLY_DATAREADY_OUT => m_DATAREADY_OUT(i*2+1),
+ MED_REPLY_DATA_OUT => m_DATA_OUT((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH),
+ MED_REPLY_PACKET_NUM_OUT => m_PACKET_NUM_OUT(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2),
+ MED_REPLY_READ_IN => m_READ_IN(i*2+1),
+ MED_REPLY_DATAREADY_IN => m_DATAREADY_IN(i*2+1),
+ MED_REPLY_DATA_IN => m_DATA_IN((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH),
+ MED_REPLY_PACKET_NUM_IN => m_PACKET_NUM_IN(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2),
+ MED_REPLY_READ_OUT => m_READ_OUT(i*2+1)
+ );
end generate;
end generate;
API_TYPE => 1,
FIFO_TO_INT_DEPTH => DAT_FIFO_TO_INT_DEPTH,
FIFO_TO_APL_DEPTH => DAT_FIFO_TO_APL_DEPTH,
- FIFO_TERM_BUFFER_DEPTH => DAT_FIFO_TERM_BUFFER_DEPTH
+ FIFO_TERM_BUFFER_DEPTH => 0
)
port map (
-- Misc
API_TYPE => 0,
FIFO_TO_INT_DEPTH => DAT_FIFO_TO_INT_DEPTH,
FIFO_TO_APL_DEPTH => DAT_FIFO_TO_APL_DEPTH,
- FIFO_TERM_BUFFER_DEPTH => DAT_FIFO_TERM_BUFFER_DEPTH
+ FIFO_TERM_BUFFER_DEPTH => 0
)
port map (
-- Misc
);
MPLEX: trb_net16_io_multiplexer
-
+ generic map (
+ DATA_WIDTH => DATA_WIDTH,
+ NUM_WIDTH => NUM_WIDTH,
+ MUX_WIDTH => MUX_WIDTH,
+ MUX_SECURE_MODE => MUX_SECURE_MODE
+ )
port map (
CLK => CLK,
RESET => RESET,
TRG_INIT : trb_net16_term
generic map (
- FIFO_TERM_BUFFER_DEPTH => TRG_FIFO_TERM_BUFFER_DEPTH,
+ FIFO_TERM_BUFFER_DEPTH => 0,
SECURE_MODE => TRG_SECURE_MODE
)
port map(
TRG_REPLY : trb_net16_term
generic map (
- FIFO_TERM_BUFFER_DEPTH => TRG_FIFO_TERM_BUFFER_DEPTH,
+ FIFO_TERM_BUFFER_DEPTH => 0,
SECURE_MODE => 0
)
port map(
TRG_INIT_DEPTH : integer := 0; -- Depth of the FIFO, 2^(n+1), if
-- the initibuf
TRG_REPLY_DEPTH : integer := 0; -- or the replyibuf
- TRG_FIFO_TERM_BUFFER_DEPTH : integer range 0 to 7 := 0;
- MULT_WIDTH : integer := 3;
+ MUX_WIDTH : integer := 3;
+ MUX_SECURE_MODE : integer := 0;
TRG_CHANNEL : integer := 0;
- BUS_WIDTH : integer := 16; --not to be changed
+ DATA_WIDTH : integer := 16; --not to be changed
NUM_WIDTH : integer := 2; --not to be changed
TRG_SECURE_MODE : integer := 0 -- if 0, error pattern and dtype must be valid until next
-- trigger comes in. if 1 these can be valid on falling edge of hold_trm only
-- Media direction port
MED_DATAREADY_OUT: out std_logic; --Data word ready to be read out
--by the media (via the TrbNetIOMultiplexer)
- MED_DATA_OUT: out std_logic_vector (BUS_WIDTH-1 downto 0); -- Data word
+ MED_DATA_OUT: out std_logic_vector (DATA_WIDTH-1 downto 0); -- Data word
MED_PACKET_NUM_OUT:out std_logic_vector (NUM_WIDTH-1 downto 0);
MED_READ_IN: in std_logic; -- Media is reading
MED_DATAREADY_IN: in std_logic; -- Data word is offered by the Media
-- (the IOBUF MUST read)
- MED_DATA_IN: in std_logic_vector (BUS_WIDTH-1 downto 0); -- Data word
+ MED_DATA_IN: in std_logic_vector (DATA_WIDTH-1 downto 0); -- Data word
MED_PACKET_NUM_IN: in std_logic_vector (NUM_WIDTH-1 downto 0);
MED_READ_OUT: out std_logic; -- buffer reads a word from media
MED_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits
);
end component;
component trb_net16_io_multiplexer is
- generic (BUS_WIDTH : integer := BUS_WIDTH;
- MULT_WIDTH : integer := MULT_WIDTH);
+ generic (
+ DATA_WIDTH : integer := DATA_WIDTH;
+ NUM_WIDTH : integer := NUM_WIDTH;
+ MUX_WIDTH : integer range 1 to 5 := MUX_WIDTH;
+ MUX_SECURE_MODE : integer range 0 to 1 := MUX_SECURE_MODE --use sbufs or not?
+ );
port(
-- Misc
CLK : in std_logic;
CLK_EN : in std_logic;
-- Media direction port
MED_DATAREADY_IN: in std_logic;
- MED_DATA_IN: in std_logic_vector (BUS_WIDTH-1 downto 0);
+ MED_DATA_IN: in std_logic_vector (DATA_WIDTH-1 downto 0);
-- highest bits are mult.
MED_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
MED_READ_OUT: out std_logic;
MED_DATAREADY_OUT: out std_logic;
- MED_DATA_OUT: out std_logic_vector (BUS_WIDTH-1 downto 0);
+ MED_DATA_OUT: out std_logic_vector (DATA_WIDTH-1 downto 0);
MED_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
MED_READ_IN: in std_logic;
-- Internal direction port
- INT_DATAREADY_OUT: out std_logic_vector (2**MULT_WIDTH-1 downto 0);
- INT_DATA_OUT: out std_logic_vector ((BUS_WIDTH)*(2**MULT_WIDTH)-1 downto 0);
- INT_PACKET_NUM_OUT:out std_logic_vector (2*(2**MULT_WIDTH)-1 downto 0);
- INT_READ_IN: in std_logic_vector (2**MULT_WIDTH-1 downto 0);
- INT_DATAREADY_IN: in std_logic_vector (2**MULT_WIDTH-1 downto 0);
- INT_DATA_IN: in std_logic_vector ((BUS_WIDTH)*(2**MULT_WIDTH)-1 downto 0);
- INT_PACKET_NUM_IN: in std_logic_vector (2*(2**MULT_WIDTH)-1 downto 0);
- INT_READ_OUT: out std_logic_vector (2**MULT_WIDTH-1 downto 0);
+ INT_DATAREADY_OUT: out std_logic_vector (2**MUX_WIDTH-1 downto 0);
+ INT_DATA_OUT: out std_logic_vector ((DATA_WIDTH)*(2**MUX_WIDTH)-1 downto 0);
+ INT_PACKET_NUM_OUT:out std_logic_vector (2*(2**MUX_WIDTH)-1 downto 0);
+ INT_READ_IN: in std_logic_vector (2**MUX_WIDTH-1 downto 0);
+ INT_DATAREADY_IN: in std_logic_vector (2**MUX_WIDTH-1 downto 0);
+ INT_DATA_IN: in std_logic_vector ((DATA_WIDTH)*(2**MUX_WIDTH)-1 downto 0);
+ INT_PACKET_NUM_IN: in std_logic_vector (2*(2**MUX_WIDTH)-1 downto 0);
+ INT_READ_OUT: out std_logic_vector (2**MUX_WIDTH-1 downto 0);
-- Status and control port
CTRL: in std_logic_vector (31 downto 0);
STAT: out std_logic_vector (31 downto 0)
end component;
component trb_net16_term is
generic (
- FIFO_TERM_BUFFER_DEPTH : integer := TRG_FIFO_TERM_BUFFER_DEPTH; -- fifo for auto-answering of
+ FIFO_TERM_BUFFER_DEPTH : integer := 0; -- fifo for auto-answering of
-- the master path, if set to 0
-- no buffer is used at all
SECURE_MODE : integer range 0 to 1 := TRG_SECURE_MODE
-- Status and control port
);
end component;
-
+ component trb_net16_term_buf is
+ port(
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ MED_INIT_DATAREADY_OUT: out std_logic;
+ MED_INIT_DATA_OUT: out std_logic_vector (15 downto 0);
+ MED_INIT_PACKET_NUM_OUT: out std_logic_vector (1 downto 0);
+ MED_INIT_READ_IN: in std_logic;
+ MED_INIT_DATAREADY_IN: in std_logic;
+ MED_INIT_DATA_IN: in std_logic_vector (15 downto 0);
+ MED_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
+ MED_INIT_READ_OUT: out std_logic;
+ MED_REPLY_DATAREADY_OUT: out std_logic;
+ MED_REPLY_DATA_OUT: out std_logic_vector (15 downto 0);
+ MED_REPLY_PACKET_NUM_OUT: out std_logic_vector (1 downto 0);
+ MED_REPLY_READ_IN: in std_logic;
+ MED_REPLY_DATAREADY_IN: in std_logic;
+ MED_REPLY_DATA_IN: in std_logic_vector (15 downto 0);
+ MED_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
+ MED_REPLY_READ_OUT: out std_logic
+ );
+ end component;
signal apl_to_buf_INIT_DATAREADY: std_logic;
signal apl_to_buf_INIT_DATA : std_logic_vector (15 downto 0);
signal MED_REPLY_PACKET_NUM_IN : std_logic_vector (1 downto 0);
signal MED_REPLY_READ_OUT : std_logic;
-signal m_DATAREADY_OUT : std_logic_vector (2**MULT_WIDTH-1 downto 0);
-signal m_DATA_OUT : std_logic_vector (BUS_WIDTH*2**MULT_WIDTH-1 downto 0);
-signal m_PACKET_NUM_OUT: std_logic_vector (NUM_WIDTH*2**MULT_WIDTH-1 downto 0);
-signal m_READ_IN : std_logic_vector (2**MULT_WIDTH-1 downto 0);
+signal m_DATAREADY_OUT : std_logic_vector (2**MUX_WIDTH-1 downto 0);
+signal m_DATA_OUT : std_logic_vector (DATA_WIDTH*2**MUX_WIDTH-1 downto 0);
+signal m_PACKET_NUM_OUT: std_logic_vector (NUM_WIDTH*2**MUX_WIDTH-1 downto 0);
+signal m_READ_IN : std_logic_vector (2**MUX_WIDTH-1 downto 0);
-signal m_DATAREADY_IN : std_logic_vector (2**MULT_WIDTH-1 downto 0);
-signal m_DATA_IN : std_logic_vector (BUS_WIDTH**MULT_WIDTH-1 downto 0);
-signal m_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH*2**MULT_WIDTH-1 downto 0);
-signal m_READ_OUT : std_logic_vector (2**MULT_WIDTH-1 downto 0);
+signal m_DATAREADY_IN : std_logic_vector (2**MUX_WIDTH-1 downto 0);
+signal m_DATA_IN : std_logic_vector (DATA_WIDTH**MUX_WIDTH-1 downto 0);
+signal m_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH*2**MUX_WIDTH-1 downto 0);
+signal m_READ_OUT : std_logic_vector (2**MUX_WIDTH-1 downto 0);
begin
-------------------------------------------------
--Connection between multiplexer and iobuf
-------------------------------------------------
--Connections for data and trigger channel
- genmuxcon : for i in 0 to 2**(MULT_WIDTH-1)-1 generate
+ genmuxcon : for i in 0 to 2**(MUX_WIDTH-1)-1 generate
gentrg: if i = TRG_CHANNEL generate
m_DATAREADY_OUT(i*2) <= MED_INIT_DATAREADY_OUT;
m_DATAREADY_OUT(i*2+1) <= MED_REPLY_DATAREADY_OUT;
- m_DATA_OUT((i*2+1)*BUS_WIDTH-1 downto i*BUS_WIDTH*2) <= MED_INIT_DATA_OUT;
- m_DATA_OUT((i*2+2)*BUS_WIDTH-1 downto (i*2+1)*BUS_WIDTH) <= MED_REPLY_DATA_OUT;
+ m_DATA_OUT((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2) <= MED_INIT_DATA_OUT;
+ m_DATA_OUT((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH) <= MED_REPLY_DATA_OUT;
m_PACKET_NUM_OUT(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2) <= MED_INIT_PACKET_NUM_OUT;
m_PACKET_NUM_OUT(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2) <= MED_REPLY_PACKET_NUM_OUT;
MED_INIT_READ_IN <= m_READ_IN(i*2);
MED_REPLY_READ_IN <= m_READ_IN(i*2+1);
MED_INIT_DATAREADY_IN <= m_DATAREADY_IN(i*2);
MED_REPLY_DATAREADY_IN <= m_DATAREADY_IN(i*2+1);
- MED_INIT_DATA_IN <= m_DATA_IN((i*2+1)*BUS_WIDTH-1 downto i*BUS_WIDTH*2);
- MED_REPLY_DATA_IN <= m_DATA_IN((i*2+2)*BUS_WIDTH-1 downto (i*2+1)*BUS_WIDTH);
+ MED_INIT_DATA_IN <= m_DATA_IN((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2);
+ MED_REPLY_DATA_IN <= m_DATA_IN((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH);
MED_INIT_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2);
MED_REPLY_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2);
m_READ_OUT(i*2) <= MED_INIT_READ_OUT;
m_READ_OUT(i*2+1) <= MED_REPLY_READ_OUT;
end generate;
- genelse: if i /= TRG_CHANNEL generate
- m_DATAREADY_OUT(i*2) <= '0';
- m_DATAREADY_OUT(i*2+1) <= '0';
- m_DATA_OUT((i*2+1)*BUS_WIDTH-1 downto i*BUS_WIDTH*2) <= (others => '0');
- m_DATA_OUT((i*2+2)*BUS_WIDTH-1 downto (i*2+1)*BUS_WIDTH) <= (others => '0');
- m_PACKET_NUM_OUT(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2) <= (others => '0');
- m_PACKET_NUM_OUT(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2) <= (others => '0');
- m_READ_OUT(i*2) <= '0';
- m_READ_OUT(i*2+1) <= '0';
+ genelse: if i /= TRG_CHANNEL generate
+ termbuf: trb_net16_term_buf
+ port map(
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+ MED_INIT_DATAREADY_OUT => m_DATAREADY_OUT(i*2),
+ MED_INIT_DATA_OUT => m_DATA_OUT((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2),
+ MED_INIT_PACKET_NUM_OUT => m_PACKET_NUM_OUT(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2),
+ MED_INIT_READ_IN => m_READ_IN(i*2),
+ MED_INIT_DATAREADY_IN => m_DATAREADY_IN(i*2),
+ MED_INIT_DATA_IN => m_DATA_IN((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2),
+ MED_INIT_PACKET_NUM_IN => m_PACKET_NUM_IN(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2),
+ MED_INIT_READ_OUT => m_READ_OUT(i*2),
+
+ MED_REPLY_DATAREADY_OUT => m_DATAREADY_OUT(i*2+1),
+ MED_REPLY_DATA_OUT => m_DATA_OUT((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH),
+ MED_REPLY_PACKET_NUM_OUT => m_PACKET_NUM_OUT(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2),
+ MED_REPLY_READ_IN => m_READ_IN(i*2+1),
+ MED_REPLY_DATAREADY_IN => m_DATAREADY_IN(i*2+1),
+ MED_REPLY_DATA_IN => m_DATA_IN((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH),
+ MED_REPLY_PACKET_NUM_IN => m_PACKET_NUM_IN(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2),
+ MED_REPLY_READ_OUT => m_READ_OUT(i*2+1)
+ );
end generate;
end generate;
);
MPLEX: trb_net16_io_multiplexer
+ generic map (
+ DATA_WIDTH => DATA_WIDTH,
+ NUM_WIDTH => NUM_WIDTH,
+ MUX_WIDTH => MUX_WIDTH,
+ MUX_SECURE_MODE => MUX_SECURE_MODE
+ )
port map (
CLK => CLK,
RESET => RESET ,
signal pwr: std_logic;
signal last_write_data: std_logic_vector(17 downto 0);
signal not_read_since_emtpy: std_logic;
+ signal last_first_write_allow: std_logic;
component BUFG
port (
end component;
begin
- read_enable <= read_enable_in;
+ read_enable <= read_enable_in or last_first_write_allow;
write_enable <= write_enable_in;
fifo_gsr <= fifo_gsr_in;
write_data <= write_data_in;
- read_data_out <= write_data_in when empty = '1' else
- last_write_data when not_read_since_emtpy = '1' else
+ read_data_out <=
read_data;
+-- write_data_in when empty = '1' else
+-- last_write_data when not_read_since_emtpy = '1' else
full_out <= full;
- -- empty_out <= empty;
+ empty_out <= empty and not fcounter(0);
gnd_bus <= "000000000000000000";
gnd <= '0';
pwr <= '1';
- process(clock_in)
- begin
- if rising_edge(clock_in) then
- if fifo_gsr = '1' then
- empty_out <= '0';
- else
- empty_out <= empty;
- end if;
- end if;
- end process;
+-- process(clock_in)
+-- begin
+-- if rising_edge(clock_in) then
+-- if fifo_gsr = '1' then
+-- empty_out <= '0';
+-- else
+-- empty_out <= emptyg;
+-- end if;
+-- end if;
+-- end process;
process(clock_in)
begin
-- end process proc2;
write_allow <= write_enable AND NOT fullg;
-read_allow <= (read_enable AND NOT empty);
+read_allow <= (read_enable AND (NOT empty or fcounter(0)));
fcnt_allow <= (write_allow XOR read_allow) or (write_enable and empty) ;
+ process(clock_in)
+ begin
+ if rising_edge(clock_in) then
+ if fifo_gsr = '1' then
+ last_first_write_allow <= '0';
+ else
+ last_first_write_allow <= write_enable and empty;
+ end if;
+ end if;
+ end process;
+
---------------------------------------------------------------
-- --
-- Empty flag is set on fifo_gsr (initial), or when on the --
---------------------------------------------------------------
ra_or_fcnt0 <= (read_allow OR NOT fcounter(0));
---fcntandout(0) <= NOT (fcounter(4) OR fcounter(3) OR fcounter(2) OR fcounter(1));
---fcntandout(1) <= NOT (fcounter(8) OR fcounter(7) OR fcounter(6) OR fcounter(5));
-emptyg <= (not or_all(fcounter(9 downto 1)) AND ra_or_fcnt0 AND NOT write_allow);
+
+emptyg <= (not or_all(fcounter(9 downto 0)) AND ra_or_fcnt0); -- AND NOT write_allow
proc3: process (clock, fifo_gsr)
begin
empty_out => EMPTY_OUT,
fifocount_out => fifocount
);
+
DEPTH_OUT <= (others => '1');
end generate;
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