*** empty log message ***

diff --git a/cts_fpga1_test.vhd b/cts_fpga1_test.vhd
index ffda2c95ee3d604ac8a78994c9f34e5b25409f14..0b6a0fe272e1a9c018a7c5d3ff847cef9ab49108 100644 (file)
--- a/cts_fpga1_test.vhd
+++ b/cts_fpga1_test.vhd
@@ -15,7 +15,7 @@ use ieee.std_logic_arith.all;
 
 entity cts_fpga1_test is
   generic(
-    RW_REGISTERS_NUMBER  : integer range 0 to 49  := 46;
+    RW_REGISTERS_NUMBER  : integer range 0 to 26  := 26;
     R_REGISTERS_NUMBER   : integer range 0 to 105 := 2;
     ENABLE_ETRAX_RW_INTERFACE : integer range 0 to 1  :=1;
     SCALERS_NUMBER        : integer range 0 to 127 :=1;
@@ -24,12 +24,8 @@ entity cts_fpga1_test is
   port(
     CLK_200_IN          : in  std_logic;
     FS_PE               : inout std_logic_vector(9 downto 8);
-    TRIG_IN             : out  std_logic_vector(TRIG_BUS_WIDTH-1 downto 0);  --the direction
-                                                               --doesn't
-                                                               --corespond to
-                                                               --the names !
-                                                               --changed in
-                                                               --signal names
+    TRIG_OUT             : out  std_logic_vector(TRIG_BUS_WIDTH-1 downto 0);  
+    --trig_out here correspond to trig_in on the schematics
     LVDS_OUT            : out std_logic_vector(14 downto 0);  
     LVDS_IN             : in  std_logic;  --//--
     PROGRAMN_OUT        : out std_logic
@@ -51,7 +47,7 @@ entity cts_fpga1_test is
 
     attribute syn_useioff : boolean;
 --    attribute syn_useioff of ADO_TTL              : signal is true;
-    attribute syn_useioff of TRIG_IN              : signal is true;
+    attribute syn_useioff of TRIG_OUT              : signal is true;
     attribute syn_useioff of LVDS_OUT             : signal is true;
     attribute syn_useioff of PROGRAMN_OUT         : signal is false;
 --    attribute syn_useioff of LED_GREEN            : signal is false;
@@ -255,33 +251,52 @@ begin
         UP_IN     => '1',
         DOWN_IN   => '0');
 
-  --selection of the frequency
+ 
 
   GENERATE_SIGNALS: for i in 0 to 32 generate
 
+    --registers are organized in a way that there is 8 bits forseen for each cnfiguration
+    --each register has 32 bit
+
+    --C0(7 downto 0) - selection which bit of the hit counter should be used
+    --for the output number 0 (frequency selection)
+    --C0(15 downto 8) - freq. out nr 1
+    --C0(23 downto 16) - freq. out nr 2
+    --C0(31 downto 24) - freq. out nr 3
+    --C1(7 downto 0) - freq. out nr 4 .......
+
+    
+   -- first a short pulses are created out of the selected cntr bit
+      
      MAKE_START_PUSLES: edge_to_pulse
       port map (
         clock     => CLK_200_IN,
         en_clk    => '1',
-        signal_in => hit_cntr(conv_integer(rw_register_i(i/6)(((i mod 6)+1)*5-1 downto (i mod 6)*5))),
+        signal_in => hit_cntr(conv_integer(rw_register_i(i/4)(((i mod 4)+1)*8-1 downto (i mod 4)*8))),
         pulse     => start_pulses(i));    
 
-    start_pulses_in_array(i)(0) <= start_pulses(i);                                
+    start_pulses_in_array(i)(0) <= start_pulses(i);
+
+    --each pulse can be delayed
+    --for output 0 it is address C8(7 downto 0)
+    -- out 1 C8(15 downto 8) ....
     DELAY_START_PULSES: cts_delay_large
       generic map (
         VECTOR_WIDTH => 1)
       port map (
         RESET            => reset_i_100,
         CLK              => CLK_200_IN,
-        DELAY_IN         => rw_register_i(i/4+11)(((i mod 4)+1)*8-1 downto (i mod 4)*8),
+        DELAY_IN         => rw_register_i(i/4+8)(((i mod 4)+1)*8-1 downto (i mod 4)*8),
         DELAY_VECTOR_IN  => start_pulses_in_array(i),
         DELAY_VECTOR_OUT => start_pulses_out_array(i));
-
+    --for each pulse you can set the width
+    --for output 0 it is address D0(7 downto 0)
+    -- out 1 D0(15 downto 8) ....
     START_SET_WIDTH: cts_fpga1_test_set_width
       port map (
         RESET        => reset_i_100,
         CLK          => CLK_200_IN,
-        SIGNAL_WIDTH => rw_register_i(i/4+27)(((i mod 4)+1)*8-1 downto (i mod 4)*8),
+        SIGNAL_WIDTH => rw_register_i(i/4+16)(((i mod 4)+1)*8-1 downto (i mod 4)*8),
         SIGNAL_IN    => start_pulses_out_array(i/4)(0),
         SIGNAL_OUT   => start_out_buf(i));
     
@@ -289,7 +304,7 @@ begin
   end generate GENERATE_SIGNALS ;
   
   trig_out_buf <= not start_out_buf;
-  TRIG_IN <= trig_out_buf(TRIG_BUS_WIDTH-1 downto 0);              
+  TRIG_OUT <= trig_out_buf(TRIG_BUS_WIDTH-1 downto 0);              
 -------------------------------------------------------------------------------
 -- beam start signal
 -------------------------------------------------------------------------------  
@@ -298,7 +313,7 @@ begin
       port map (
         clock     => CLK_200_IN,
         en_clk    => '1',
-        signal_in => hit_cntr(conv_integer(rw_register_i(44)(5 downto 0))),
+        signal_in => hit_cntr(conv_integer(rw_register_i(25)(5 downto 0))),
         pulse     => beam_inhibit_pulse);    
 
   BEAM_INHIBIT_SET_WIDTH: cts_fpga1_test_set_width