slightly better handling of different port number for input logic

diff --git a/base/code/input_statistics.vhd b/base/code/input_statistics.vhd
index c6eb8c794f5c1b39fd85943f7700b11a41e2e1ec..8e872ecbdde9733207d9962d7391bfeb529a5886 100644 (file)
--- a/base/code/input_statistics.vhd
+++ b/base/code/input_statistics.vhd
@@ -33,7 +33,7 @@ signal inp_reg      : std_logic_vector(INPUTS-1 downto 0);
 signal inp_reg_last : std_logic_vector(INPUTS-1 downto 0);
 signal inp_inv      : std_logic_vector(INPUTS-1 downto 0);
 signal inp_stretch  : std_logic_vector(INPUTS-1 downto 0);
-signal inp_reg_95   : std_logic_vector(95 downto 0);
+signal inp_reg_95   : std_logic_vector(95 downto 0) := (others => '0');
 
 signal trigger_fifo, trigger_fifo_buf : std_logic;
 signal trigger_fifo_real, trigger_fifo_external : std_logic := '0';
@@ -51,8 +51,8 @@ signal fifo_read   : std_logic_vector(LAST_FIFO_NUM downto 0);
 signal fifo_wait,fifo_wait2,fifo_wait3   : std_logic;
 signal fifo_empty  : std_logic_vector(LAST_FIFO_NUM downto 0);
 signal fifo_write  : std_logic;
-signal fifo_select : integer range 0 to 95;
-signal fifo_in_sel : integer range 0 to 95;
+signal fifo_select : integer range 0 to INPUTS-1;
+signal fifo_in_sel : integer range 0 to INPUTS-1;
 
 
 type cnt_t is array(0 to INPUTS-1) of unsigned(23 downto 0);

diff --git a/base/code/input_to_trigger_logic_record.vhd b/base/code/input_to_trigger_logic_record.vhd
index 584d91d2db5746426621bcd566f46f7142d264eb..295a8dcb213fdc0c3d2862c8b135d5e4ad6e4257 100644 (file)
--- a/base/code/input_to_trigger_logic_record.vhd
+++ b/base/code/input_to_trigger_logic_record.vhd
@@ -232,7 +232,7 @@ gen_mult : if OUTPUTS >= 2 generate
   begin
     wait until rising_edge(CLK);
     m := 0;
-    for i in 0 to INPUTS-1 loop
+    for i in 0 to 31 loop  --was INPUTS-1 @ 09.17
       if inp_verylong(i) = '1' and multiplicity_enable(i) = '1' then
         m := m + 1;
       end if;