CLK_125 : in std_logic;
CLK_125_RX : out std_logic_vector(3 downto 0);
-- FIFO interface RX
- FIFO_DATA_OUT : out std_logic_vector(4 * 8 - 1 downto 0);
+ FIFO_DATA_OUT : out std_logic_vector(4 * 9 - 1 downto 0);
FIFO_FULL_IN : in std_logic_vector(3 downto 0);
FIFO_WR_OUT : out std_logic_vector(3 downto 0);
FRAME_REQ_IN : in std_logic_vector(3 downto 0);
-- FIFO interface TX
FIFO_FULL_OUT : out std_logic_vector(3 downto 0);
FIFO_WR_IN : in std_logic_vector(3 downto 0);
- FIFO_DATA_IN : in std_logic_vector(4 * 8 - 1 downto 0);
+ FIFO_DATA_IN : in std_logic_vector(4 * 9 - 1 downto 0);
FRAME_START_IN : in std_logic_vector(3 downto 0);
-- SFP Connection
SD_PRSNT_N_IN : in std_logic_vector(3 downto 0) := (others => '0');
-- FIFO interface (TX)
FIFO_FULL_IN => FIFO_FULL_IN(i),
FIFO_WR_OUT => FIFO_WR_OUT(i),
- FIFO_Q_OUT => FIFO_DATA_OUT((i + 1) * 8 - 1 downto i * 8),
+ FIFO_Q_OUT => FIFO_DATA_OUT((i + 1) * 9 - 1 downto i * 9),
FRAME_REQ_IN => FRAME_REQ_IN(i),
FRAME_ACK_OUT => FRAME_ACK_OUT(i),
FRAME_AVAIL_OUT => FRAME_AVAIL_OUT(i),
-- FIFO interface
FIFO_FULL_OUT => FIFO_FULL_OUT(i),
FIFO_WR_IN => FIFO_WR_IN(i),
- FIFO_D_IN => FIFO_DATA_IN((i + 1) * 8 - 1 downto i * 8),
+ FIFO_D_IN => FIFO_DATA_IN((i + 1) * 9 - 1 downto i * 9),
-- Link stuff
FRAME_START_IN => FRAME_START_IN(i),
LINK_ACTIVE_IN => an_complete(i),
CLEAR : in std_logic;\r
RESET : in std_logic;\r
--\r
+ FIFO_FULL_IN : in std_logic_vector(15 downto 0) := (others => '0');\r
+ FIFO_FULL_OUT : out std_logic;\r
FRAME_AVAIL_IN : in std_logic := '0';\r
FRAME_REQ_OUT : out std_logic;\r
FRAME_ACK_IN : in std_logic := '0';\r
\r
begin\r
\r
- CYCLE_DONE_OUT <= '1' when STATE = CLEANUP else '0';
+ CYCLE_DONE_OUT <= '1' when STATE = CLEANUP else '0';\r
\r
FRAME_REQ_OUT <= req_int;\r
\r
+ FIFO_FULL_OUT <= '0' when FIFO_FULL_IN = x"0000" else '1';\r
+ \r
-----------------------------------------------------------\r
-- statemachine: clocked process\r
-----------------------------------------------------------\r