FR_FRAME_VALID_OUT : out std_logic; -- interconnect to gbe_receive_control\r
FR_GET_FRAME_IN : in std_logic; -- interconnect to gbe_receive_control\r
FR_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); -- interconnect to gbe_receive_control\r
- FR_FRAME_PROTO_OUT : out std_logic_vector(15 downto 0); -- interconnect to gbe_receive_control\r
- FR_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); -- interconnect to gbe_receive_control\r
FR_PS_OUT : out std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);\r
--\r
FR_SRC_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0);\r
\r
signal rec_fifo_empty : std_logic;\r
signal rec_fifo_full : std_logic;\r
- signal sizes_fifo_full : std_logic;\r
- signal sizes_fifo_empty : std_logic;\r
+-- signal sizes_fifo_full : std_logic;\r
+-- signal sizes_fifo_empty : std_logic;\r
\r
signal remove_ctr : unsigned(7 downto 0);\r
signal new_frame : std_logic;\r
signal fr_dest_udp : std_logic_vector(15 downto 0);\r
signal fr_src_udp : std_logic_vector(15 downto 0);\r
signal fr_frame_size : std_logic_vector(15 downto 0);\r
- signal fr_frame_proto : std_logic_vector(15 downto 0);\r
signal fr_dest_mac : std_logic_vector(47 downto 0);\r
signal fr_src_mac : std_logic_vector(47 downto 0);\r
- signal fr_ip_proto : std_logic_vector(7 downto 0);\r
signal fr_ps : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);\r
\r
- signal xxx0 : std_logic_vector(7 downto 0);\r
- signal xxx1 : std_logic_vector(7 downto 0);\r
-\r
signal oob_register_0_int : std_logic_vector(31 downto 0);\r
signal oob_register_1_int : std_logic_vector(31 downto 0);\r
signal oob_register_2_int : std_logic_vector(31 downto 0);\r
signal oob_register_3_int : std_logic_vector(31 downto 0);\r
signal oob_write : std_logic;\r
\r
- signal proto_select_x : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);\r
+ signal oob_select_x : std_logic;\r
+ signal oob_select : std_logic;\r
+ \r
signal proto_select : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);\r
\r
signal set_proto_x : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);\r
begin\r
if ( RESET = '1' ) then\r
filter_current_state <= IDLE;\r
+ oob_select <= '0';\r
elsif( rising_edge(CLK) ) then\r
filter_current_state <= filter_next_state;\r
+ oob_select <= oob_select_x;\r
end if;\r
end process PROC_FILTER_FSM;\r
\r
saved_dest_mac, remove_ctr, new_frame, MAC_RX_EOF_IN, frame_type_valid, ALLOW_RX_IN)\r
begin\r
set_proto_x <= (others => '0');\r
+ oob_select_x <= '0';\r
\r
case filter_current_state is\r
\r
set_proto_x(2) <= '1';\r
when others =>\r
filter_next_state <= DROP_FRAME;\r
+ oob_select_x <= '1';\r
end case;\r
else\r
filter_next_state <= REMOVE_UDP;\r
end case;\r
end process PROC_FILTER_TRANSITIONS;\r
\r
- -- determine the protocol handler for later usage\r
- -- ARP\r
- proto_select_x(0) <= '1' when ( (saved_frame_type = x"0806") ) else '0';\r
- -- DHCP\r
- proto_select_x(1) <= '1' when ( (saved_frame_type = x"0800") and (saved_proto = x"11") and (saved_dest_udp = x"0044") ) else '0';\r
- -- SCTRL\r
- proto_select_x(2) <= '1' when ( (saved_frame_type = x"0800") and (saved_proto = x"11") and (saved_dest_udp = x"6590") ) else '0';\r
- -- ???\r
- proto_select_x(3) <= '0';\r
- -- ICMP\r
- proto_select_x(4) <= '1' when ( (saved_frame_type = x"0800") and (saved_proto = x"01") ) else '0';\r
- -- FWD???\r
- proto_select_x(5) <= '0';\r
- -- TO BE INCLUDED INTO FSM!!!\r
-\r
-- protocol selection\r
PROC_PROTO_SEL: process( CLK, RESET )\r
begin\r
end if;\r
end process PROC_KILLER_PING;\r
\r
+ -- BROKEN!!!\r
PROC_SECRET_FRAME: process( CLK )\r
begin\r
if( rising_edge(CLK) ) then\r
- if( (filter_current_state = DELAY) and \r
+ if( (oob_select = '1') and \r
(saved_proto = x"11") and \r
(saved_frame_type = x"0800") and\r
(saved_dest_udp = x"d903") and \r
end if;\r
end process PROC_RX_FIFO_SYNC;\r
\r
- THE_SIZES_FIFO: entity work.fifo_512x32\r
- port map(\r
- Data(15 downto 0) => rx_bytes_ctr,\r
- Data(31 downto 16) => saved_frame_type,\r
- WrClock => CLK,\r
- RdClock => CLK,\r
- WrEn => frame_valid_q,\r
- RdEn => FR_GET_FRAME_IN,\r
- Reset => RESET,\r
- RPReset => RESET,\r
- Q(15 downto 0) => fr_frame_size,\r
- Q(31 downto 16) => fr_frame_proto,\r
- Empty => sizes_fifo_empty,\r
- Full => sizes_fifo_full\r
- );\r
-\r
THE_MACS_FIFO: entity work.fifo_512x72\r
port map(\r
Data(47 downto 0) => saved_src_mac,\r
Data(63 downto 48) => saved_src_udp,\r
- Data(71 downto 64) => (others => '0'),\r
+ Data(71 downto 64) => rx_bytes_ctr(7 downto 0), --(others => '0'),\r
WrClock => CLK,\r
RdClock => CLK,\r
WrEn => frame_valid_q,\r
RPReset => RESET,\r
Q(47 downto 0) => fr_src_mac,\r
Q(63 downto 48) => fr_src_udp,\r
- Q(71 downto 64) => xxx0, --open,\r
+ Q(71 downto 64) => fr_frame_size(7 downto 0), --open,\r
Empty => open,\r
Full => open\r
);\r
port map(\r
Data(47 downto 0) => saved_dest_mac,\r
Data(63 downto 48) => saved_dest_udp,\r
--- Data(71 downto 64) => (others => '0'),\r
Data(69 downto 64) => proto_select,\r
Data(71 downto 70) => (others => '0'),\r
WrClock => CLK,\r
RPReset => RESET,\r
Q(47 downto 0) => fr_dest_mac,\r
Q(63 downto 48) => fr_dest_udp,\r
--- Q(71 downto 64) => xxx1, --open,\r
- Q(69 downto 64) => fr_ps, --open,\r
- Q(71 downto 70) => xxx1(1 downto 0), --open,\r
+ Q(69 downto 64) => fr_ps,\r
+ Q(71 downto 70) => open,\r
Empty => open,\r
Full => open\r
);\r
port map(\r
Data(31 downto 0) => saved_src_ip,\r
Data(63 downto 32) => saved_dest_ip,\r
- Data(71 downto 64) => saved_proto,\r
+ Data(71 downto 64) => rx_bytes_ctr(15 downto 8), --saved_proto,\r
WrClock => CLK,\r
RdClock => CLK,\r
WrEn => frame_valid_q,\r
RPReset => RESET,\r
Q(31 downto 0) => fr_src_ip,\r
Q(63 downto 32) => fr_dest_ip,\r
- Q(71 downto 64) => fr_ip_proto,\r
+ Q(71 downto 64) => fr_frame_size(15 downto 8), --open,\r
Empty => open,\r
Full => open\r
);\r
if( rising_edge(CLK) ) then\r
FR_SRC_IP_ADDRESS_OUT <= fr_src_ip;\r
FR_DEST_IP_ADDRESS_OUT <= fr_dest_ip;\r
- FR_IP_PROTOCOL_OUT <= fr_ip_proto;\r
FR_DEST_UDP_PORT_OUT <= fr_dest_udp;\r
FR_DEST_MAC_ADDRESS_OUT <= fr_dest_mac;\r
FR_SRC_MAC_ADDRESS_OUT <= fr_src_mac;\r
FR_SRC_UDP_PORT_OUT <= fr_src_udp;\r
- FR_FRAME_PROTO_OUT <= fr_frame_proto;\r
FR_FRAME_SIZE_OUT <= fr_frame_size;\r
FR_Q_OUT <= fr_q;\r
FR_PS_OUT <= fr_ps;\r
--\r
delayed_frame_valid <= MAC_RX_EOF_IN;\r
delayed_frame_valid_q <= delayed_frame_valid;\r
--- proto_select <= proto_select_x;\r
end if;\r
end process PROC_SYNC;\r
\r
signal fr_get_frame : std_logic;
signal mc_transmit_done : std_logic;
- signal fr_frame_proto : std_logic_vector(15 downto 0);
+-- signal fr_frame_proto : std_logic_vector(15 downto 0);
signal rc_frame_proto : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
signal mc_type : std_logic_vector(15 downto 0);
signal ft_tx_empty : std_logic;
signal ft_start_of_packet : std_logic;
- signal fr_ip_proto : std_logic_vector(7 downto 0);
+-- signal fr_ip_proto : std_logic_vector(7 downto 0);
signal mc_ip_proto : std_logic_vector(7 downto 0);
signal mc_ident : std_logic_vector(15 downto 0);
signal fr_ps_int : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
-begin
+ signal dbg_main : std_logic_vector(63 downto 0);
+
+ begin
+
+---------------------------------------------------------------------------------------------------
+---------------------------------------------------------------------------------------------------
+-- DEBUG_OUT(31 downto 0) <= (others => '0');
+ -- TX
+ DEBUG_OUT(31 downto 28) <= dbg_main(7 downto 4);
+ DEBUG_OUT(27) <= '0';
+ DEBUG_OUT(26) <= mc_transmit_done;
+ DEBUG_OUT(25) <= mc_transmit_ctrl;
+ DEBUG_OUT(24) <= mc_wr_en;
+ DEBUG_OUT(23 downto 20) <= dbg_main(15 downto 12);
+ DEBUG_OUT(19 downto 16) <= dbg_main(11 downto 8);
+-- DEBUG_OUT(23 downto 16) <= mc_data(7 downto 0);
+ -- RX
+ DEBUG_OUT(15) <= rc_loading_done;
+ DEBUG_OUT(14) <= rc_frame_ready;
+ DEBUG_OUT(13) <= rc_frame_proto(4); -- ICMP
+ DEBUG_OUT(12) <= rc_frame_proto(1); -- DHCP
+ DEBUG_OUT(11) <= rc_frame_proto(0); -- ARP
+ DEBUG_OUT(10) <= fr_get_frame;
+ DEBUG_OUT(9) <= fr_frame_valid;
+ DEBUG_OUT(8) <= fr_rd_en;
+ DEBUG_OUT(7 downto 0) <= rc_q(7 downto 0);
+---------------------------------------------------------------------------------------------------
+---------------------------------------------------------------------------------------------------
fc_ihl_version <= x"45";
fc_tos <= x"10";
FWD_READY_OUT => FWD_READY_OUT,
FWD_FULL_OUT => FWD_FULL_OUT,
--
- DEBUG_OUT(15 downto 0) => DEBUG_OUT(31 downto 16),
- DEBUG_OUT(63 downto 16) => open,
+ DEBUG_OUT => dbg_main,
+-- DEBUG_OUT(15 downto 0) => open,
+-- DEBUG_OUT(63 downto 16) => open,
--
MONITOR_SELECT_GEN_DBG_OUT => dbg_select_gen
);
FR_FRAME_VALID_IN => fr_frame_valid,
FR_GET_FRAME_OUT => fr_get_frame,
FR_FRAME_SIZE_IN => fr_frame_size,
- FR_FRAME_PROTO_IN => fr_frame_proto,
- FR_IP_PROTOCOL_IN => fr_ip_proto,
FR_PS_IN => fr_ps_int,
FR_SRC_MAC_ADDRESS_IN => fr_src_mac,
FR_DEST_MAC_ADDRESS_IN => fr_dest_mac,
FR_FRAME_VALID_OUT => fr_frame_valid,
FR_GET_FRAME_IN => fr_get_frame,
FR_FRAME_SIZE_OUT => fr_frame_size,
- FR_FRAME_PROTO_OUT => fr_frame_proto,
- FR_IP_PROTOCOL_OUT => fr_ip_proto,
FR_PS_OUT => fr_ps_int,
--- FR_ALLOWED_TYPES_IN => (others => '1'), --fr_allowed_types,
--- FR_ALLOWED_IP_IN => (others => '1'), --fr_allowed_ip,
--- FR_ALLOWED_UDP_IN => (others => '1'), --fr_allowed_udp,
--- FR_VLAN_ID_IN => (others => '0'), --vlan_id,
--
FR_SRC_MAC_ADDRESS_OUT => fr_src_mac,
FR_DEST_MAC_ADDRESS_OUT => fr_dest_mac,
MONITOR_RX_FRAMES_OUT => monitor_rx_frames,
MONITOR_DROPPED_OUT => monitor_dropped,
--
- DEBUG_OUT(15 downto 0) => DEBUG_OUT(15 downto 0), --open
+ DEBUG_OUT(15 downto 0) => open,
DEBUG_OUT(31 downto 16) => open
);
signal redirect_current_state, redirect_next_state : redirect_states;
attribute syn_encoding of redirect_current_state : signal is "onehot";
- signal disable_redirect : std_logic;
signal ps_wr_en_q : std_logic;
signal ps_wr_en_qq : std_logic;
attribute syn_preserve : boolean;
attribute syn_keep : boolean;
- attribute syn_keep of link_state, state, redirect_state, dhcp_done : signal is true;
- attribute syn_preserve of link_state, state, redirect_state, dhcp_done : signal is true;
+ attribute syn_keep of link_state, redirect_state, dhcp_done : signal is true;
+ attribute syn_preserve of link_state, redirect_state, dhcp_done : signal is true;
+-- attribute syn_keep of link_state, state, redirect_state, dhcp_done : signal is true;
+-- attribute syn_preserve of link_state, state, redirect_state, dhcp_done : signal is true;
signal mc_busy : std_logic;
signal incl_dhcp : std_logic;
DEBUG_OUT(15 downto 12) <= link_state;
DEBUG_OUT(11 downto 8) <= redirect_state;
- DEBUG_OUT(7) <= '0';
- DEBUG_OUT(6) <= disable_redirect;
- DEBUG_OUT(5 downto 0) <= RC_FRAME_PROTO_IN;
+ DEBUG_OUT(7 downto 4) <= flow_state;
+ DEBUG_OUT(3 downto 0) <= (others => '0');
THE_PROTOCOL_SELECTOR: entity work.gbe_protocol_selector
generic map(
TC_DATA_OUT <= tc_data;
- -- gk 07.11.11
- -- do not select any response constructors when dropping a frame
-- proto_select <= RC_FRAME_PROTO_IN when disable_redirect = '0' else (others => '0');
proto_select <= RC_FRAME_PROTO_IN;
- -- gk 07.11.11
- -- we do not answer at all, unless we are in either ACTIVE or GET_ADDRESS state.
- -- in GET_ADDRESS state, we only answer on DHCP frames.
- PROC_DISABLE_REDIRECT: process( CLK, RESET )
- begin
- if ( RESET = '1' ) then
- disable_redirect <= '0';
- elsif( rising_edge(CLK) ) then
- if( redirect_current_state = CHECK_TYPE ) then
- if ( (link_current_state /= ACTIVE) and (link_current_state /= GET_ADDRESS) ) then
- disable_redirect <= '1';
- elsif( (link_current_state = GET_ADDRESS) and (RC_FRAME_PROTO_IN /= "10") ) then -- (UDP, DHCP)
- disable_redirect <= '1';
- else
- disable_redirect <= '0';
- end if;
- end if;
- end if;
- end process PROC_DISABLE_REDIRECT;
-
-- warning
PROC_SYNC: process( CLK )
begin
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-
-library work;
-use work.trb_net_std.all;
-use work.gbe_protocols.all;
-
-entity gbe_receive_control is
- port (
- CLK : in std_logic; -- system clock
- RESET : in std_logic;
- -- signals to/from frame_receiver
- RC_DATA_IN : in std_logic_vector(8 downto 0);
- FR_RD_EN_OUT : out std_logic;
- FR_FRAME_VALID_IN : in std_logic;
- FR_GET_FRAME_OUT : out std_logic;
- FR_FRAME_SIZE_IN : in std_logic_vector(15 downto 0);
- FR_FRAME_PROTO_IN : in std_logic_vector(15 downto 0);
- FR_IP_PROTOCOL_IN : in std_logic_vector(7 downto 0);
- FR_PS_IN : in std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
- FR_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- FR_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- FR_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- FR_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- FR_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0);
- FR_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0);
- -- signals to/from main controller
- RC_RD_EN_IN : in std_logic;
- RC_Q_OUT : out std_logic_vector(8 downto 0);
- RC_FRAME_WAITING_OUT : out std_logic;
- RC_LOADING_DONE_IN : in std_logic;
- RC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
- RC_FRAME_PROTO_OUT : out std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
- RC_SRC_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0);
- RC_DEST_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0);
- RC_SRC_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0);
- RC_DEST_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0);
- RC_SRC_UDP_PORT_OUT : out std_logic_vector(15 downto 0);
- RC_DEST_UDP_PORT_OUT : out std_logic_vector(15 downto 0);
- -- statistics
- FRAMES_RECEIVED_OUT : out std_logic_vector(31 downto 0);
- BYTES_RECEIVED_OUT : out std_logic_vector(31 downto 0);
- --
- DEBUG_OUT : out std_logic_vector(63 downto 0)
- );
-end gbe_receive_control;
-
-architecture gbe_receive_control_arch of gbe_receive_control is
-
- attribute syn_encoding : string;
-
- type load_states is (IDLE, PREPARE, WAIT_ONE, READY);
- signal load_current_state, load_next_state : load_states;
- attribute syn_encoding of load_current_state : signal is "onehot";
-
- signal frames_received_ctr : unsigned(31 downto 0);
- signal frames_readout_ctr : unsigned(31 downto 0);
- signal bytes_rec_ctr : unsigned(31 downto 0);
-
- signal state : std_logic_vector(3 downto 0);
- signal proto_code : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
- signal reset_prioritizer : std_logic;
-
- -- debug only
- signal saved_proto : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
-
-begin
-
- FR_RD_EN_OUT <= RC_RD_EN_IN;
- RC_Q_OUT <= RC_DATA_IN;
- RC_FRAME_SIZE_OUT <= FR_FRAME_SIZE_IN;
- RC_SRC_MAC_ADDRESS_OUT <= FR_SRC_MAC_ADDRESS_IN;
- RC_DEST_MAC_ADDRESS_OUT <= FR_DEST_MAC_ADDRESS_IN;
- RC_SRC_IP_ADDRESS_OUT <= FR_SRC_IP_ADDRESS_IN;
- RC_DEST_IP_ADDRESS_OUT <= FR_DEST_IP_ADDRESS_IN;
- RC_SRC_UDP_PORT_OUT <= FR_SRC_UDP_PORT_IN;
- RC_DEST_UDP_PORT_OUT <= FR_DEST_UDP_PORT_IN;
-
--- protocol_prioritizer: entity work.gbe_protocol_prioritizer
--- port map(
--- CLK => CLK,
--- RESET => reset_prioritizer,
--- --
--- FRAME_TYPE_IN => FR_FRAME_PROTO_IN,
--- PROTOCOL_CODE_IN => FR_IP_PROTOCOL_IN,
--- UDP_PROTOCOL_IN => FR_DEST_UDP_PORT_IN,
--- --
--- CODE_OUT => proto_code
--- );
---
--- reset_prioritizer <= '1' when load_current_state = IDLE else '0';
---
--- RC_FRAME_PROTO_OUT <= proto_code; -- no more ones as the incorrect value, last slot for Trash
-\r
- RC_FRAME_PROTO_OUT <= FR_PS_IN when (load_current_state /= IDLE) else (others => '0');\r
-
- LOAD_MACHINE_PROC: process( CLK, RESET )
- begin
- if ( RESET = '1' ) then
- load_current_state <= IDLE;
- elsif( rising_edge(CLK) ) then
- load_current_state <= load_next_state;
- end if;
- end process LOAD_MACHINE_PROC;
-
- LOAD_MACHINE: process( load_current_state, frames_readout_ctr, frames_received_ctr, RC_LOADING_DONE_IN )
- begin
- case load_current_state is
-
- when IDLE =>
- state <= x"1";
- if( frames_readout_ctr /= frames_received_ctr ) then -- frame is still waiting in frame_receiver
- load_next_state <= PREPARE;
- else
- load_next_state <= IDLE;
- end if;
-
- when PREPARE => -- prepare frame size
- state <= x"2";
- load_next_state <= WAIT_ONE;
-
- when WAIT_ONE =>
- load_next_state <= READY;
-
- when READY => -- wait for reading out the whole frame
- state <= x"3";
- if( RC_LOADING_DONE_IN = '1' ) then
- load_next_state <= IDLE;
- else
- load_next_state <= READY;
- end if;
-
- end case;
- end process LOAD_MACHINE;
-
- process( CLK )
- begin
- if( rising_edge(CLK) ) then
- if( load_current_state = PREPARE ) then
- FR_GET_FRAME_OUT <= '1';
- else
- FR_GET_FRAME_OUT <= '0';
- end if;
-
- if( (load_current_state = READY) and (RC_LOADING_DONE_IN = '0') ) then
- RC_FRAME_WAITING_OUT <= '1';
- else
- RC_FRAME_WAITING_OUT <= '0';
- end if;
- end if;
- end process;
-
- FRAMES_REC_CTR_PROC: process( CLK, RESET )
- begin
- if ( RESET = '1' ) then
- frames_received_ctr <= (others => '0');
- elsif( rising_edge(CLK) ) then
- if( FR_FRAME_VALID_IN = '1' ) then
- frames_received_ctr <= frames_received_ctr + 1;
- end if;
- end if;
- end process FRAMES_REC_CTR_PROC;
-
- FRAMES_READOUT_CTR_PROC: process( CLK, RESET )
- begin
- if ( RESET = '1' ) then
- frames_readout_ctr <= (others => '0');
- elsif( rising_edge(CLK) ) then
- if( RC_LOADING_DONE_IN = '1' ) then
- frames_readout_ctr <= frames_readout_ctr + 1;
- end if;
- end if;
- end process FRAMES_READOUT_CTR_PROC;
-
- -- debug only
- BYTES_REC_CTR_PROC : process( CLK )
- begin
- if ( RESET = '1' ) then
- bytes_rec_ctr <= (others => '0');
- elsif( rising_edge(CLK) ) then
- if( FR_FRAME_VALID_IN = '1' ) then
- bytes_rec_ctr <= bytes_rec_ctr + unsigned(FR_FRAME_SIZE_IN);
- end if;
- end if;
- end process BYTES_REC_CTR_PROC;
-
- SAVED_PROTO_PROC : process( CLK )
- begin
- if( rising_edge(CLK) ) then
- if( load_current_state = READY ) then
- if( and_all(proto_code) = '0' ) then
- saved_proto <= proto_code;
- else
- saved_proto <= (others => '0');
- end if;
- else
- saved_proto <= saved_proto;
- end if;
- end if;
- end process SAVED_PROTO_PROC;
-
-end gbe_receive_control_arch;
+LIBRARY IEEE;\r
+USE IEEE.std_logic_1164.ALL;\r
+USE IEEE.numeric_std.ALL;\r
+USE IEEE.std_logic_UNSIGNED.ALL;\r
+\r
+library work;\r
+use work.trb_net_std.all;\r
+use work.gbe_protocols.all;\r
+\r
+entity gbe_receive_control is\r
+ port (\r
+ CLK : in std_logic; -- system clock\r
+ RESET : in std_logic;\r
+ -- signals to/from frame_receiver\r
+ RC_DATA_IN : in std_logic_vector(8 downto 0);\r
+ FR_RD_EN_OUT : out std_logic;\r
+ FR_FRAME_VALID_IN : in std_logic;\r
+ FR_GET_FRAME_OUT : out std_logic;\r
+ FR_FRAME_SIZE_IN : in std_logic_vector(15 downto 0);\r
+ FR_PS_IN : in std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);\r
+ FR_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);\r
+ FR_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);\r
+ FR_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);\r
+ FR_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);\r
+ FR_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0);\r
+ FR_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0);\r
+ -- signals to/from main controller\r
+ RC_RD_EN_IN : in std_logic;\r
+ RC_Q_OUT : out std_logic_vector(8 downto 0);\r
+ RC_FRAME_WAITING_OUT : out std_logic;\r
+ RC_LOADING_DONE_IN : in std_logic;\r
+ RC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);\r
+ RC_FRAME_PROTO_OUT : out std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);\r
+ RC_SRC_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0);\r
+ RC_DEST_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0);\r
+ RC_SRC_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0);\r
+ RC_DEST_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0);\r
+ RC_SRC_UDP_PORT_OUT : out std_logic_vector(15 downto 0);\r
+ RC_DEST_UDP_PORT_OUT : out std_logic_vector(15 downto 0);\r
+ -- statistics\r
+ FRAMES_RECEIVED_OUT : out std_logic_vector(31 downto 0);\r
+ BYTES_RECEIVED_OUT : out std_logic_vector(31 downto 0);\r
+ --\r
+ DEBUG_OUT : out std_logic_vector(63 downto 0)\r
+ );\r
+end gbe_receive_control;\r
+\r
+architecture gbe_receive_control_arch of gbe_receive_control is\r
+\r
+ attribute syn_encoding : string;\r
+\r
+ type load_states is (IDLE, PREPARE, WAIT_ONE, READY);\r
+ signal load_current_state, load_next_state : load_states;\r
+ attribute syn_encoding of load_current_state : signal is "onehot";\r
+\r
+ signal frames_received_ctr : unsigned(31 downto 0);\r
+ signal frames_readout_ctr : unsigned(31 downto 0);\r
+ signal bytes_rec_ctr : unsigned(31 downto 0);\r
+\r
+ signal state : std_logic_vector(3 downto 0);\r
+ signal proto_code : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);\r
+ signal reset_prioritizer : std_logic;\r
+\r
+ -- debug only\r
+ signal saved_proto : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);\r
+\r
+begin\r
+\r
+ FR_RD_EN_OUT <= RC_RD_EN_IN;\r
+ RC_Q_OUT <= RC_DATA_IN;\r
+ RC_FRAME_SIZE_OUT <= FR_FRAME_SIZE_IN;\r
+ RC_SRC_MAC_ADDRESS_OUT <= FR_SRC_MAC_ADDRESS_IN;\r
+ RC_DEST_MAC_ADDRESS_OUT <= FR_DEST_MAC_ADDRESS_IN;\r
+ RC_SRC_IP_ADDRESS_OUT <= FR_SRC_IP_ADDRESS_IN;\r
+ RC_DEST_IP_ADDRESS_OUT <= FR_DEST_IP_ADDRESS_IN;\r
+ RC_SRC_UDP_PORT_OUT <= FR_SRC_UDP_PORT_IN;\r
+ RC_DEST_UDP_PORT_OUT <= FR_DEST_UDP_PORT_IN;\r
+ RC_FRAME_PROTO_OUT <= FR_PS_IN when (load_current_state /= IDLE) else (others => '0');\r
+\r
+ LOAD_MACHINE_PROC: process( CLK, RESET )\r
+ begin\r
+ if ( RESET = '1' ) then\r
+ load_current_state <= IDLE;\r
+ elsif( rising_edge(CLK) ) then\r
+ load_current_state <= load_next_state;\r
+ end if;\r
+ end process LOAD_MACHINE_PROC;\r
+\r
+ LOAD_MACHINE: process( load_current_state, frames_readout_ctr, frames_received_ctr, RC_LOADING_DONE_IN )\r
+ begin\r
+ case load_current_state is\r
+\r
+ when IDLE =>\r
+ state <= x"1";\r
+ if( frames_readout_ctr /= frames_received_ctr ) then -- frame is still waiting in frame_receiver\r
+ load_next_state <= PREPARE;\r
+ else\r
+ load_next_state <= IDLE;\r
+ end if;\r
+\r
+ when PREPARE => -- prepare frame size\r
+ state <= x"2";\r
+ load_next_state <= WAIT_ONE;\r
+ \r
+ when WAIT_ONE =>\r
+ load_next_state <= READY;\r
+\r
+ when READY => -- wait for reading out the whole frame\r
+ state <= x"3";\r
+ if( RC_LOADING_DONE_IN = '1' ) then\r
+ load_next_state <= IDLE;\r
+ else\r
+ load_next_state <= READY;\r
+ end if;\r
+\r
+ end case;\r
+ end process LOAD_MACHINE;\r
+\r
+ process( CLK )\r
+ begin\r
+ if( rising_edge(CLK) ) then\r
+ if( load_current_state = PREPARE ) then\r
+ FR_GET_FRAME_OUT <= '1';\r
+ else\r
+ FR_GET_FRAME_OUT <= '0';\r
+ end if;\r
+\r
+ if( (load_current_state = READY) and (RC_LOADING_DONE_IN = '0') ) then\r
+ RC_FRAME_WAITING_OUT <= '1';\r
+ else\r
+ RC_FRAME_WAITING_OUT <= '0';\r
+ end if;\r
+ end if;\r
+ end process;\r
+\r
+ FRAMES_REC_CTR_PROC: process( CLK, RESET )\r
+ begin\r
+ if ( RESET = '1' ) then\r
+ frames_received_ctr <= (others => '0');\r
+ elsif( rising_edge(CLK) ) then\r
+ if( FR_FRAME_VALID_IN = '1' ) then\r
+ frames_received_ctr <= frames_received_ctr + 1;\r
+ end if;\r
+ end if;\r
+ end process FRAMES_REC_CTR_PROC;\r
+\r
+ FRAMES_READOUT_CTR_PROC: process( CLK, RESET )\r
+ begin\r
+ if ( RESET = '1' ) then\r
+ frames_readout_ctr <= (others => '0');\r
+ elsif( rising_edge(CLK) ) then\r
+ if( RC_LOADING_DONE_IN = '1' ) then\r
+ frames_readout_ctr <= frames_readout_ctr + 1;\r
+ end if; \r
+ end if;\r
+ end process FRAMES_READOUT_CTR_PROC;\r
+\r
+ -- debug only\r
+ BYTES_REC_CTR_PROC : process( CLK )\r
+ begin\r
+ if ( RESET = '1' ) then\r
+ bytes_rec_ctr <= (others => '0');\r
+ elsif( rising_edge(CLK) ) then\r
+ if( FR_FRAME_VALID_IN = '1' ) then\r
+ bytes_rec_ctr <= bytes_rec_ctr + unsigned(FR_FRAME_SIZE_IN); \r
+ end if;\r
+ end if;\r
+ end process BYTES_REC_CTR_PROC;\r
+\r
+ SAVED_PROTO_PROC : process( CLK )\r
+ begin\r
+ if( rising_edge(CLK) ) then\r
+ if( load_current_state = READY ) then\r
+ if( and_all(proto_code) = '0' ) then\r
+ saved_proto <= proto_code;\r
+ else\r
+ saved_proto <= (others => '0');\r
+ end if;\r
+ else\r
+ saved_proto <= saved_proto;\r
+ end if;\r
+ end if;\r
+ end process SAVED_PROTO_PROC;\r
+\r
+end gbe_receive_control_arch;\r
PROC_DATA_CTR: process( CLK, RESET )
begin
if ( RESET = '1' ) then
- data_ctr <= 1;
+ data_ctr <= 0;
+-- data_ctr <= 1;
elsif( rising_edge(CLK) ) then
if ( (dissect_current_state = IDLE) and (PS_WR_EN_IN = '0') ) then
- data_ctr <= 1;
+ data_ctr <= 0;
+-- data_ctr <= 1;
elsif( dissect_current_state = WAIT_FOR_LOAD ) then
data_ctr <= 1;
elsif( dissect_current_state = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1' ) then
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