--- /dev/null
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+\r
+library work;\r
+use work.nxyter_components.all;\r
+\r
+entity debug_multiplexer is\r
+ generic (\r
+ NUM_PORTS : integer range 1 to 32 := 1\r
+ );\r
+ port(\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+\r
+ DEBUG_LINE_IN : in debug_array_t(0 to NUM_PORTS-1);\r
+ DEBUG_LINE_OUT : out std_logic_vector(15 downto 0);\r
+\r
+ -- Slave bus \r
+ SLV_READ_IN : in std_logic;\r
+ SLV_WRITE_IN : in std_logic;\r
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
+ SLV_ADDR_IN : in std_logic_vector(15 downto 0);\r
+ SLV_ACK_OUT : out std_logic;\r
+ SLV_NO_MORE_DATA_OUT : out std_logic;\r
+ SLV_UNKNOWN_ADDR_OUT : out std_logic\r
+\r
+ );\r
+end entity;\r
+\r
+architecture Behavioral of debug_multiplexer is\r
+\r
+ signal port_select : std_logic_vector(7 downto 0);\r
+ signal debug_line_o : std_logic_vector(15 downto 0);\r
+ \r
+ signal slv_data_out_o : std_logic_vector(31 downto 0);\r
+ signal slv_no_more_data_o : std_logic;\r
+ signal slv_unknown_addr_o : std_logic;\r
+ signal slv_ack_o : std_logic;\r
+ \r
+begin\r
+ \r
+ PROC_MULTIPLEXER: process(port_select,\r
+ DEBUG_LINE_IN)\r
+ begin\r
+ if (unsigned(port_select) < NUM_PORTS) then\r
+ debug_line_o <= DEBUG_LINE_IN(to_integer(unsigned(port_select)));\r
+ else\r
+ debug_line_o <= (others => '1');\r
+ end if;\r
+ end process PROC_MULTIPLEXER;\r
+\r
+ PROC_SLAVE_BUS: process(CLK_IN)\r
+ begin\r
+ if( rising_edge(CLK_IN) ) then\r
+ if( RESET_IN = '1' ) then\r
+ slv_data_out_o <= (others => '0');\r
+ slv_no_more_data_o <= '0';\r
+ slv_unknown_addr_o <= '0';\r
+ slv_ack_o <= '0';\r
+ port_select <= (others => '0');\r
+ else\r
+ slv_ack_o <= '1';\r
+ slv_unknown_addr_o <= '0';\r
+ slv_no_more_data_o <= '0';\r
+ slv_data_out_o <= (others => '0'); \r
+ \r
+ if (SLV_WRITE_IN = '1') then\r
+ case SLV_ADDR_IN is\r
+ when x"0000" =>\r
+ if (unsigned(SLV_DATA_IN(7 downto 0)) < NUM_PORTS) then\r
+ port_select <= SLV_DATA_IN(7 downto 0);\r
+ end if;\r
+ slv_ack_o <= '1';\r
+\r
+ when others => \r
+ slv_unknown_addr_o <= '1';\r
+ slv_ack_o <= '0';\r
+ end case;\r
+ \r
+ elsif (SLV_READ_IN = '1') then\r
+ case SLV_ADDR_IN is\r
+ when x"0000" =>\r
+ slv_data_out_o(7 downto 0) <= port_select;\r
+ slv_data_out_o(31 downto 8) <= (others => '0');\r
+\r
+ when others =>\r
+ slv_unknown_addr_o <= '1';\r
+ slv_ack_o <= '0';\r
+ end case;\r
+\r
+ else\r
+ slv_ack_o <= '0';\r
+ end if;\r
+ end if;\r
+ end if; \r
+ end process PROC_SLAVE_BUS;\r
+ \r
+ -----------------------------------------------------------------------------\r
+ -- Output Signals\r
+ -----------------------------------------------------------------------------\r
+\r
+ SLV_DATA_OUT <= slv_data_out_o; \r
+ SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o; \r
+ SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o;\r
+ SLV_ACK_OUT <= slv_ack_o;\r
+ \r
+ DEBUG_LINE_OUT <= debug_line_o;\r
+\r
+end Behavioral;\r
signal adc_reset : std_logic;\r
\r
signal adc_data : std_logic_vector(11 downto 0);\r
+ signal test_adc_data : std_logic_vector(11 downto 0);\r
signal adc_data_valid : std_logic;\r
\r
signal adc_data_t : std_logic_vector(11 downto 0);\r
\r
DEBUG_OUT(0) <= CLK_IN;\r
DEBUG_OUT(2 downto 1) <= STATE_d;\r
- DEBUG_OUT(3) <= nx_new_timestamp;\r
- DEBUG_OUT(4) <= adc_new_data;\r
- DEBUG_OUT(5) <= new_data_o;\r
- DEBUG_OUT(6) <= nx_fifo_data_valid;\r
- DEBUG_OUT(7) <= valid_data_d;--(others => '0');\r
- DEBUG_OUT(15 downto 8) <= nx_timestamp_reg;\r
+ DEBUG_OUT(3) <= adc_data_valid; -- nx_new_timestamp;\r
+ --DEBUG_OUT(4) <= adc_new_data;\r
+ --DEBUG_OUT(5) <= new_data_o;\r
+ --DEBUG_OUT(6) <= nx_fifo_data_valid;\r
+ --DEBUG_OUT(7) <= valid_data_d;--(others => '0');\r
+ --DEBUG_OUT(15 downto 8) <= nx_timestamp_reg;\r
--DEBUG_OUT(15 downto 8) <= (others => '0');\r
-\r
+ DEBUG_OUT(15 downto 4) <= test_adc_data;\r
+ \r
PROC_DEBUG: process(NX_TIMESTAMP_CLK_IN)\r
begin\r
if( rising_edge(NX_TIMESTAMP_CLK_IN) ) then\r
ADCCLK_OUT => ADC_SAMPLE_CLK_OUT,\r
\r
ADC_DATA(0) => ADC_NX_IN(0), \r
- ADC_DATA(1) => ADC_A_IN(0),\r
- ADC_DATA(2) => ADC_B_IN(0), \r
+ ADC_DATA(1) => ADC_B_IN(0),\r
+ ADC_DATA(2) => ADC_A_IN(0), \r
ADC_DATA(3) => ADC_D_IN(0), \r
\r
ADC_DATA(4) => ADC_NX_IN(1), \r
ADC_FCO => ADC_FCLK_IN,\r
\r
DATA_OUT(11 downto 0) => adc_data,\r
- DATA_OUT(95 downto 12) => open,\r
+ DATA_OUT(23 downto 12) => test_adc_data,\r
+ DATA_OUT(95 downto 24) => open,\r
\r
FCO_OUT => open,\r
DATA_VALID_OUT(0) => adc_data_valid,\r
\r
if (new_timestamp = '1') then\r
case valid_frame_bits is\r
-\r
+ \r
-- Data Frame\r
when "1000" =>\r
---- Check Overflow\r
signal fifo_write_enable : std_logic;
-- NOMORE_DATA RS FlipFlop
- signal flush_end : std_logic;
+ signal flush_end_enable_set : std_logic;
+ signal flush_end_enable : std_logic;
-- FIFO Read Handler
signal fifo_o : std_logic_vector(31 downto 0);
signal R_STATE : R_STATES;
-- Event Buffer Output Handler
- signal evt_data_clk : std_logic;
- signal evt_data_flushed : std_logic;
-
- signal fifo_read_enable_f : std_logic;
- signal fifo_read_enable_f2 : std_logic;
- signal fifo_flush_ctr : unsigned(10 downto 0);
-
- signal evt_data_flushed_x : std_logic;
- signal fifo_flush_ctr_x : unsigned(10 downto 0);
- signal flush_end_reset : std_logic;
- signal flush_end_reset_x : std_logic;
+ signal evt_data_clk : std_logic;
+ signal evt_data_flushed : std_logic;
+
+ signal fifo_read_enable_f : std_logic;
+ signal fifo_read_enable_f2 : std_logic;
+ signal fifo_flush_ctr : unsigned(10 downto 0);
+
+ signal evt_data_flushed_x : std_logic;
+ signal fifo_flush_ctr_x : unsigned(10 downto 0);
+ signal flush_end_enable_reset_x : std_logic;
type F_STATES is (F_IDLE,
F_FLUSH,
signal data_wait : std_logic;
- signal evt_data_flush_r : std_logic;
-
begin
DEBUG_OUT(0) <= CLK_IN;
- --DEBUG_OUT(1) <= evt_data_flush_r;
+ DEBUG_OUT(1) <= '0';
DEBUG_OUT(2) <= evt_data_clk;
DEBUG_OUT(3) <= fifo_empty;
DEBUG_OUT(4) <= fifo_read_enable;
--DEBUG_OUT(15 downto 8) <= evt_data_o(31 downto 24);
DEBUG_OUT(8) <= LVL2_TRIGGER_IN;
- DEBUG_OUT(11 downto 9) <= (others => '0');
+ DEBUG_OUT(9) <= evt_data_flushed;
+ DEBUG_OUT(10) <= FAST_CLEAR_IN;
+ DEBUG_OUT(12) <= flush_end_enable;
DEBUG_OUT(13) <= fee_data_write_o;
DEBUG_OUT(14) <= fee_data_finished_o;
DEBUG_OUT(15) <= FEE_DATA_ALMOST_FULL_IN;
begin
if( rising_edge(CLK_IN) ) then
if( RESET_IN = '1' ) then
+ evt_data_flush <= '0';
fee_data_finished_o <= '0';
trigger_busy_o <= '0';
STATE <= S_IDLE;
else
+ evt_data_flush <= '0';
fee_data_finished_o <= '0';
trigger_busy_o <= '1';
-
- case STATE is
- when S_IDLE =>
- if (NXYTER_OFFLINE_IN = '1') then
- fee_data_finished_o <= '1';
- trigger_busy_o <= '0';
- STATE <= S_IDLE;
- elsif (LVL2_TRIGGER_IN = '1') then
- evt_data_flush <= '1';
- STATE <= S_FLUSH_BUFFER_WAIT;
- else
- trigger_busy_o <= '0';
- STATE <= S_IDLE;
- end if;
-
- when S_FLUSH_BUFFER_WAIT =>
- if (evt_data_flushed = '0') then
- STATE <= S_FLUSH_BUFFER_WAIT;
- else
- fee_data_finished_o <= '1';
- STATE <= S_IDLE;
- end if;
-
- end case;
+ DEBUG_OUT(11) <= '0';
+
+ if (FAST_CLEAR_IN = '1') then
+ fee_data_finished_o <= '1';
+ STATE <= S_IDLE;
+ else
+ case STATE is
+ when S_IDLE =>
+ if (NXYTER_OFFLINE_IN = '1') then
+ fee_data_finished_o <= '1';
+ trigger_busy_o <= '0';
+ STATE <= S_IDLE;
+ elsif (LVL2_TRIGGER_IN = '1') then
+ evt_data_flush <= '1';
+ STATE <= S_FLUSH_BUFFER_WAIT;
+ else
+ trigger_busy_o <= '0';
+ STATE <= S_IDLE;
+ end if;
+
+ when S_FLUSH_BUFFER_WAIT =>
+ DEBUG_OUT(11) <= '1';
+ if (evt_data_flushed = '0') then
+ STATE <= S_FLUSH_BUFFER_WAIT;
+ else
+ fee_data_finished_o <= '1';
+ STATE <= S_IDLE;
+ end if;
+
+ end case;
+ end if;
end if;
end if;
-
end process PROC_DATA_HANDLER;
-----------------------------------------------------------------------------
end if;
end process PROC_FIFO_WRITE_HANDLER;
- PROC_FLUSH_END_RS: process(CLK_IN)
+ PROC_FLUSH_END_RS_FF: process(CLK_IN)
begin
if( rising_edge(CLK_IN) ) then
- if( RESET_IN = '1' or flush_end_reset = '1') then
- flush_end <= '0';
+ if( RESET_IN = '1' or flush_end_enable_reset_x = '1') then
+ flush_end_enable <= '0';
else
- if (EVT_NOMORE_DATA_IN = '1') then
- flush_end <= '1';
+ if (flush_end_enable_set = '1') then
+ flush_end_enable <= '1';
end if;
end if;
end if;
- end process PROC_FLUSH_END_RS;
-
+ end process PROC_FLUSH_END_RS_FF;
+
+ flush_end_enable_set <= EVT_NOMORE_DATA_IN;
+
PROC_FLUSH_BUFFER_TRANSFER: process(CLK_IN)
begin
if( rising_edge(CLK_IN) ) then
if( RESET_IN = '1' ) then
- evt_data_clk <= '0';
- evt_data_flushed <= '0';
- fifo_flush_ctr <= (others => '0');
- fifo_read_enable_f2 <= '0';
- flush_end_reset <= '0';
- F_STATE <= F_IDLE;
+ evt_data_clk <= '0';
+ evt_data_flushed <= '0';
+ fifo_flush_ctr <= (others => '0');
+ fifo_read_enable_f2 <= '0';
+ F_STATE <= F_IDLE;
else
- evt_data_flushed <= evt_data_flushed_x;
- fifo_flush_ctr <= fifo_flush_ctr_x;
- flush_end_reset <= flush_end_reset_x;
- F_STATE <= F_NEXT_STATE;
+ evt_data_flushed <= evt_data_flushed_x;
+ fifo_flush_ctr <= fifo_flush_ctr_x;
+ F_STATE <= F_NEXT_STATE;
- fifo_read_enable_f2 <= fifo_read_enable_f;
- evt_data_clk <= fifo_read_enable_f2;
+ fifo_read_enable_f2 <= fifo_read_enable_f;
+ evt_data_clk <= fifo_read_enable_f2;
end if;
end if;
end process PROC_FLUSH_BUFFER_TRANSFER;
evt_data_flush,
fifo_empty,
evt_data_clk,
- flush_end
+ flush_end_enable
)
begin
-- Defaults
- fifo_read_enable_f <= '0';
- fifo_flush_ctr_x <= fifo_flush_ctr;
- evt_data_flushed_x <= '0';
- flush_end_reset_x <= '0';
+ fifo_read_enable_f <= '0';
+ fifo_flush_ctr_x <= fifo_flush_ctr;
+ evt_data_flushed_x <= '0';
+ flush_end_enable_reset_x <= '0';
-- Multiplexer fee_data_o
if (evt_data_clk = '1') then
- fee_data_o <= fifo_o;
- fee_data_write_o <= '1';
+ fee_data_o <= fifo_o;
+ fee_data_write_o <= '1';
else
- fee_data_o <= (others => '1');
- fee_data_write_o <= '0';
+ fee_data_o <= (others => '1');
+ fee_data_write_o <= '0';
end if;
-- FIFO Read Handler
case F_STATE is
when F_IDLE =>
if (evt_data_flush = '1') then
- fifo_flush_ctr_x <= (others => '0');
- flush_end_reset_x <= '1';
- F_NEXT_STATE <= F_FLUSH;
+ fifo_flush_ctr_x <= (others => '0');
+ flush_end_enable_reset_x <= '1';
+ F_NEXT_STATE <= F_FLUSH;
else
- F_NEXT_STATE <= F_IDLE;
+ F_NEXT_STATE <= F_IDLE;
end if;
when F_FLUSH =>
if (fifo_empty = '0') then
- fifo_read_enable_f <= '1';
- fifo_flush_ctr_x <= fifo_flush_ctr + 1;
- F_NEXT_STATE <= F_FLUSH;
+ fifo_read_enable_f <= '1';
+ fifo_flush_ctr_x <= fifo_flush_ctr + 1;
+ F_NEXT_STATE <= F_FLUSH;
else
- if (flush_end = '0') then
- F_NEXT_STATE <= F_FLUSH;
+ if (flush_end_enable = '0') then
+ F_NEXT_STATE <= F_FLUSH;
else
- F_NEXT_STATE <= F_END;
+ F_NEXT_STATE <= F_END;
end if;
end if;
when F_END =>
- evt_data_flushed_x <= '1';
- F_NEXT_STATE <= F_IDLE;
+ evt_data_flushed_x <= '1';
+ F_NEXT_STATE <= F_IDLE;
end case;
end process PROC_FLUSH_BUFFER;
fifo_read_start <= '0';
data_wait <= '0';
- evt_data_flush_r <= '0';
else
slv_data_out_o <= (others => '0');
slv_ack_o <= '0';
fifo_read_start <= '0';
data_wait <= '0';
- evt_data_flush_r <= '0';
if (data_wait = '1') then
if (fifo_read_done = '0') then
elsif (SLV_WRITE_IN = '1') then
case SLV_ADDR_IN is
-
- when x"0000" =>
- evt_data_flush_r <= '1';
- slv_ack_o <= '1';
-
when others =>
slv_unknown_addr_o <= '1';
slv_ack_o <= '0';
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
+library work;
+use work.nxyter_components.all;
+
entity nx_histograms is
generic (
- NUM_BINS : integer := 7
+ BUS_WIDTH : integer := 7;
+ ENABLE : integer := 1
);
port (
CLK_IN : in std_logic;
RESET_HISTS_IN : in std_logic;
CHANNEL_STAT_FILL_IN : in std_logic;
- CHANNEL_ID_IN : in std_logic_vector(NUM_BINS - 1 downto 0);
+ CHANNEL_ID_IN : in std_logic_vector(BUS_WIDTH - 1 downto 0);
-- Slave bus
SLV_READ_IN : in std_logic;
architecture nx_histograms of nx_histograms is
- type histogram_t is array(0 to 127) of unsigned(31 downto 0);
+ type histogram_t is array(0 to 2**BUS_WIDTH - 1) of unsigned(23 downto 0);
+
+ -- PROC_CHANNEL_HIST
signal hist_channel_stat : histogram_t;
+ signal hist_channel_freq : histogram_t;
+ signal wait_timer_init : unsigned(27 downto 0);
+ signal wait_timer_done : std_logic;
-- Slave Bus
signal slv_data_out_o : std_logic_vector(31 downto 0);
signal reset_hists_r : std_logic;
begin
+
+hist_enable_1: if ENABLE = 1 generate
+ DEBUG_OUT(0) <= CLK_IN;
+ DEBUG_OUT(1) <= RESET_IN;
+ DEBUG_OUT(2) <= RESET_HISTS_IN;
+ DEBUG_OUT(3) <= reset_hists_r;
+ DEBUG_OUT(4) <= slv_ack_o;
+ DEBUG_OUT(5) <= SLV_READ_IN;
+ DEBUG_OUT(6) <= SLV_WRITE_IN;
+ DEBUG_OUT(7) <= wait_timer_done;
+ DEBUG_OUT(15 downto 8) <= (others => '0');
+
+ -----------------------------------------------------------------------------
PROC_CHANNEL_HIST : process (CLK_IN)
begin
if( rising_edge(CLK_IN) ) then
if (RESET_IN = '1' or reset_hists_r = '1' or RESET_HISTS_IN = '1') then
- for I in (NUM_BINS - 1) downto 0 loop
+ for I in 0 to (2**BUS_WIDTH - 1) loop
hist_channel_stat(I) <= (others => '0');
+ hist_channel_freq(I) <= (others => '0');
end loop;
+ wait_timer_init <= x"000_0001";
else
- if (CHANNEL_STAT_FILL_IN = '1') then
- hist_channel_stat(to_integer(unsigned(CHANNEL_ID_IN))) <=
- hist_channel_stat(to_integer(unsigned(CHANNEL_ID_IN))) + 1;
+ wait_timer_init <= (others => '0');
+ if (wait_timer_done = '1') then
+ for I in 0 to (2**BUS_WIDTH - 1) loop
+ hist_channel_stat(I) <= (others => '0');
+ hist_channel_freq(I) <=
+ (hist_channel_freq(I) + hist_channel_stat(I)) / 2;
+ end loop;
+ wait_timer_init <= x"5f5_e100";
+ else
+ if (CHANNEL_STAT_FILL_IN = '1') then
+ hist_channel_stat(to_integer(unsigned(CHANNEL_ID_IN))) <=
+ hist_channel_stat(to_integer(unsigned(CHANNEL_ID_IN))) + 1;
+ end if;
end if;
end if;
end if;
end process PROC_CHANNEL_HIST;
+ -- Timer
+ nx_timer_1: nx_timer
+ generic map (
+ CTR_WIDTH => 28
+ )
+ port map (
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+ TIMER_START_IN => wait_timer_init,
+ TIMER_DONE_OUT => wait_timer_done
+ );
-----------------------------------------------------------------------------
-- TRBNet Slave Bus
-----------------------------------------------------------------------------
- -- Give status info to the TRB Slow Control Channel
+
+ -- Give status info to the TRB Slow Control Channel
PROC_HISTOGRAMS_READ: process(CLK_IN)
begin
if( rising_edge(CLK_IN) ) then
slv_data_out_o <= (others => '0');
slv_unknown_addr_o <= '0';
slv_no_more_data_o <= '0';
- slv_ack_o <= '0';
reset_hists_r <= '0';
if (SLV_READ_IN = '1') then
if (unsigned(SLV_ADDR_IN) >= x"0000" and
- unsigned(SLV_ADDR_IN) < x"0080") then
- slv_data_out_o <= std_logic_vector(
+ unsigned(SLV_ADDR_IN) <= x"007f") then
+ slv_data_out_o(23 downto 0) <= std_logic_vector(
hist_channel_stat(to_integer(unsigned(SLV_ADDR_IN(7 downto 0))))
);
- slv_ack_o <= '1';
+ slv_data_out_o(31 downto 24) <= (others => '0');
+ slv_ack_o <= '1';
+ elsif (unsigned(SLV_ADDR_IN) >= x"0080" and
+ unsigned(SLV_ADDR_IN) <= x"00ff") then
+ slv_data_out_o(23 downto 0) <= std_logic_vector(
+ hist_channel_freq(to_integer(unsigned(SLV_ADDR_IN(7 downto 0))))
+ );
+ slv_data_out_o(31 downto 24) <= (others => '0');
+ slv_ack_o <= '1';
else
- slv_unknown_addr_o <= '1';
- end if;
-
+ slv_ack_o <= '0';
+ end if;
+
elsif (SLV_WRITE_IN = '1') then
case SLV_ADDR_IN is
when others =>
slv_unknown_addr_o <= '1';
-
+ slv_ack_o <= '0';
end case;
+ else
+ slv_ack_o <= '0';
end if;
end if;
end if;
end process PROC_HISTOGRAMS_READ;
-
+
+end generate hist_enable_1;
-----------------------------------------------------------------------------
-- Output Signals
-----------------------------------------------------------------------------
\r
architecture Behavioral of nx_i2c_master is\r
\r
+ signal sda_o : std_logic;\r
+ signal scl_o : std_logic;\r
+ \r
signal sda_i : std_logic;\r
signal sda_x : std_logic;\r
signal sda : std_logic;\r
signal command_busy_o : std_logic;\r
\r
-- I2C Master \r
- signal sda_o : std_logic;\r
- signal scl_o : std_logic;\r
+ signal sda_master : std_logic;\r
+ signal scl_master : std_logic;\r
signal i2c_start : std_logic;\r
-\r
signal i2c_busy : std_logic;\r
signal startstop_select : std_logic;\r
signal startstop_seq_start : std_logic;\r
-- Debug\r
DEBUG_OUT(0) <= CLK_IN;\r
DEBUG_OUT(8 downto 1) <= i2c_data(7 downto 0);\r
- DEBUG_OUT(12 downto 9) <= i2c_data(31 downto 28);\r
- DEBUG_OUT(13) <= i2c_busy;\r
- DEBUG_OUT(14) <= internal_command;\r
- DEBUG_OUT(15) <= internal_command_d;\r
-\r
+ DEBUG_OUT(10 downto 9) <= i2c_data(31 downto 30);\r
+ DEBUG_OUT(11) <= i2c_busy;\r
+ DEBUG_OUT(12) <= sda_o;\r
+ DEBUG_OUT(13) <= scl_o;\r
+ DEBUG_OUT(14) <= sda;\r
+ DEBUG_OUT(15) <= scl;\r
+ --DEBUG_OUT(12 downto 9) <= i2c_data(31 downto 28);\r
+ \r
-- Start / Stop Sequence\r
nx_i2c_startstop_1: nx_i2c_startstop\r
generic map (\r
SDA_OUT => sda_sendbyte,\r
SCL_OUT => scl_sendbyte,\r
SDA_IN => sda,\r
+ SCL_IN => scl,\r
ACK_OUT => sendbyte_ack\r
);\r
\r
\r
begin\r
-- Defaults\r
- sda_o <= '1';\r
- scl_o <= '1';\r
- i2c_busy_x <= '1';\r
- startstop_select_x <= '0';\r
- startstop_seq_start_x <= '0';\r
- sendbyte_seq_start_x <= '0';\r
- sendbyte_byte_x <= (others => '0');\r
- readbyte_seq_start_x <= '0';\r
- i2c_data_x <= i2c_data;\r
- read_seq_ctr_x <= read_seq_ctr;\r
+ sda_master <= '1';\r
+ scl_master <= '1';\r
+ i2c_busy_x <= '1';\r
+ startstop_select_x <= '0';\r
+ startstop_seq_start_x <= '0';\r
+ sendbyte_seq_start_x <= '0';\r
+ sendbyte_byte_x <= (others => '0');\r
+ readbyte_seq_start_x <= '0';\r
+ i2c_data_x <= i2c_data;\r
+ read_seq_ctr_x <= read_seq_ctr;\r
\r
case STATE is\r
\r
when S_RESET =>\r
- i2c_data_x <= (others => '0');\r
- NEXT_STATE <= S_IDLE;\r
+ i2c_data_x <= (others => '0');\r
+ NEXT_STATE <= S_IDLE;\r
\r
when S_IDLE =>\r
if (i2c_start = '1') then\r
- i2c_data_x <= x"8000_0000"; -- Set Running, clear all other bits \r
- NEXT_STATE <= S_START;\r
+ i2c_data_x <= x"8000_0000"; -- Set Running, clear all\r
+ -- other bits \r
+ NEXT_STATE <= S_START;\r
else\r
- i2c_busy_x <= '0';\r
- i2c_data_x <= i2c_data and x"7fff_ffff"; -- clear running bit;\r
- read_seq_ctr_x <= '0';\r
- NEXT_STATE <= S_IDLE;\r
+ i2c_busy_x <= '0';\r
+ i2c_data_x <= i2c_data and x"7fff_ffff"; -- clear running\r
+ -- bit;\r
+ read_seq_ctr_x <= '0';\r
+ NEXT_STATE <= S_IDLE;\r
end if;\r
\r
-- I2C START Sequence \r
when S_START =>\r
- startstop_select_x <= '1';\r
- startstop_seq_start_x <= '1';\r
- NEXT_STATE <= S_START_WAIT;\r
+ startstop_select_x <= '1';\r
+ startstop_seq_start_x <= '1';\r
+ NEXT_STATE <= S_START_WAIT;\r
\r
when S_START_WAIT =>\r
if (startstop_done = '0') then\r
- NEXT_STATE <= S_START_WAIT;\r
+ NEXT_STATE <= S_START_WAIT;\r
else\r
- sda_o <= '0';\r
- scl_o <= '0';\r
- NEXT_STATE <= S_SEND_CHIP_ID;\r
+ sda_master <= '0';\r
+ scl_master <= '0';\r
+ NEXT_STATE <= S_SEND_CHIP_ID;\r
end if;\r
\r
-- I2C SEND ChipId Sequence\r
when S_SEND_CHIP_ID =>\r
- scl_o <= '0';\r
+ scl_master <= '0';\r
sendbyte_byte_x(7 downto 1) <= i2c_chipid;\r
if (read_seq_ctr = '0') then\r
- sendbyte_byte_x(0) <= '0';\r
+ sendbyte_byte_x(0) <= '0';\r
else\r
- sendbyte_byte_x(0) <= '1';\r
+ sendbyte_byte_x(0) <= '1';\r
end if;\r
- sendbyte_seq_start_x <= '1';\r
- NEXT_STATE <= S_SEND_CHIP_ID_WAIT;\r
+ sendbyte_seq_start_x <= '1';\r
+ NEXT_STATE <= S_SEND_CHIP_ID_WAIT;\r
\r
when S_SEND_CHIP_ID_WAIT =>\r
if (sendbyte_done = '0') then\r
- NEXT_STATE <= S_SEND_CHIP_ID_WAIT;\r
+ NEXT_STATE <= S_SEND_CHIP_ID_WAIT;\r
else\r
- scl_o <= '0';\r
+ scl_master <= '0';\r
if (sendbyte_ack = '0') then\r
- i2c_data_x <= i2c_data or x"0100_0000";\r
- NEXT_STATE <= S_STOP;\r
+ i2c_data_x <= i2c_data or x"0100_0000";\r
+ NEXT_STATE <= S_STOP;\r
else\r
if (read_seq_ctr = '0') then\r
- read_seq_ctr_x <= '1';\r
- NEXT_STATE <= S_SEND_REGISTER;\r
+ read_seq_ctr_x <= '1';\r
+ NEXT_STATE <= S_SEND_REGISTER;\r
else\r
- NEXT_STATE <= S_GET_DATA;\r
+ NEXT_STATE <= S_GET_DATA;\r
end if;\r
end if;\r
end if;\r
\r
-- I2C SEND RegisterId\r
when S_SEND_REGISTER =>\r
- scl_o <= '0';\r
- sendbyte_byte_x <= i2c_registerid; \r
- sendbyte_seq_start_x <= '1';\r
- NEXT_STATE <= S_SEND_REGISTER_WAIT;\r
+ scl_master <= '0';\r
+ sendbyte_byte_x <= i2c_registerid; \r
+ sendbyte_seq_start_x <= '1';\r
+ NEXT_STATE <= S_SEND_REGISTER_WAIT;\r
\r
when S_SEND_REGISTER_WAIT =>\r
if (sendbyte_done = '0') then\r
- NEXT_STATE <= S_SEND_REGISTER_WAIT;\r
+ NEXT_STATE <= S_SEND_REGISTER_WAIT;\r
else\r
- scl_o <= '0';\r
+ scl_master <= '0';\r
if (sendbyte_ack = '0') then\r
- i2c_data_x <= i2c_data or x"0200_0000";\r
- NEXT_STATE <= S_STOP;\r
+ i2c_data_x <= i2c_data or x"0200_0000";\r
+ NEXT_STATE <= S_STOP;\r
else\r
if (i2c_rw_bit = '0') then\r
- NEXT_STATE <= S_SEND_DATA;\r
+ NEXT_STATE <= S_SEND_DATA;\r
else\r
- NEXT_STATE <= S_START;\r
+ NEXT_STATE <= S_START;\r
end if;\r
end if;\r
end if;\r
\r
-- I2C SEND DataWord\r
when S_SEND_DATA =>\r
- scl_o <= '0';\r
- sendbyte_byte_x <= i2c_register_data;\r
- sendbyte_seq_start_x <= '1';\r
- NEXT_STATE <= S_SEND_DATA_WAIT;\r
+ scl_master <= '0';\r
+ sendbyte_byte_x <= i2c_register_data;\r
+ sendbyte_seq_start_x <= '1';\r
+ NEXT_STATE <= S_SEND_DATA_WAIT;\r
\r
when S_SEND_DATA_WAIT =>\r
if (sendbyte_done = '0') then\r
- NEXT_STATE <= S_SEND_DATA_WAIT;\r
+ NEXT_STATE <= S_SEND_DATA_WAIT;\r
else\r
- scl_o <= '0';\r
+ scl_master <= '0';\r
if (sendbyte_ack = '0') then\r
- i2c_data_x <= i2c_data or x"0400_0000";\r
+ i2c_data_x <= i2c_data or x"0400_0000";\r
end if;\r
- NEXT_STATE <= S_STOP;\r
+ NEXT_STATE <= S_STOP;\r
end if;\r
\r
-- I2C GET DataWord\r
when S_GET_DATA =>\r
- scl_o <= '0';\r
- readbyte_seq_start_x <= '1';\r
- NEXT_STATE <= S_GET_DATA_WAIT;\r
+ scl_master <= '0';\r
+ readbyte_seq_start_x <= '1';\r
+ NEXT_STATE <= S_GET_DATA_WAIT;\r
\r
when S_GET_DATA_WAIT =>\r
if (readbyte_done = '0') then\r
- NEXT_STATE <= S_GET_DATA_WAIT;\r
+ NEXT_STATE <= S_GET_DATA_WAIT;\r
else\r
- scl_o <= '0';\r
- i2c_data_x(7 downto 0) <= readbyte_byte; \r
- NEXT_STATE <= S_STOP;\r
+ scl_master <= '0';\r
+ i2c_data_x(7 downto 0)<= readbyte_byte; \r
+ NEXT_STATE <= S_STOP;\r
end if;\r
\r
-- I2C STOP Sequence \r
when S_STOP =>\r
- sda_o <= '0';\r
- scl_o <= '0';\r
- startstop_select_x <= '0';\r
- startstop_seq_start_x <= '1';\r
- NEXT_STATE <= S_STOP_WAIT;\r
+ sda_master <= '0';\r
+ scl_master <= '0';\r
+ startstop_select_x <= '0';\r
+ startstop_seq_start_x <= '1';\r
+ NEXT_STATE <= S_STOP_WAIT;\r
\r
when S_STOP_WAIT =>\r
if (startstop_done = '0') then\r
- NEXT_STATE <= S_STOP_WAIT;\r
+ NEXT_STATE <= S_STOP_WAIT;\r
else\r
- i2c_data_x <= i2c_data or x"4000_0000"; -- Set DONE Bit\r
- NEXT_STATE <= S_IDLE;\r
+ i2c_data_x <= i2c_data or x"4000_0000"; -- Set DONE Bit\r
+ NEXT_STATE <= S_IDLE;\r
end if;\r
\r
end case;\r
begin \r
if( rising_edge(CLK_IN) ) then\r
if( RESET_IN = '1' ) then\r
- i2c_data_internal_o <= (others => '0');\r
- i2c_data_slave <= (others => '0');\r
- command_busy_o <= '0';\r
+ i2c_data_internal_o <= (others => '0');\r
+ i2c_data_slave <= (others => '0');\r
+ command_busy_o <= '0';\r
else\r
if (internal_command = '0' and internal_command_d = '0') then \r
- i2c_data_slave <= i2c_data;\r
+ i2c_data_slave <= i2c_data;\r
else\r
- i2c_data_internal_o <= i2c_data;\r
+ i2c_data_internal_o <= i2c_data;\r
end if;\r
end if;\r
- command_busy_o <= i2c_busy;\r
+ command_busy_o <= i2c_busy;\r
end if;\r
end process PROC_I2C_DATA_MULTIPLEXER;\r
\r
-----------------------------------------------------------------------------\r
\r
-- I2C Outputs\r
- SDA_INOUT <= '0' when (sda_o = '0' or\r
- sda_startstop = '0' or\r
- sda_sendbyte = '0' or\r
- sda_readbyte = '0')\r
- else 'Z';\r
- \r
- SCL_INOUT <= '0' when (scl_o = '0' or\r
- scl_startstop = '0' or\r
- scl_sendbyte = '0' or\r
- scl_readbyte = '0')\r
- else 'Z';\r
-\r
- COMMAND_BUSY_OUT <= command_busy_o;\r
- I2C_DATA_OUT <= i2c_data_internal_o;\r
+ sda_o <= (sda_master and\r
+ sda_startstop and\r
+ sda_sendbyte and\r
+ sda_readbyte\r
+ );\r
+ SDA_INOUT <= '0' when (sda_o = '0') else 'Z';\r
+ \r
+ scl_o <= (scl_master and\r
+ scl_startstop and\r
+ scl_sendbyte and\r
+ scl_readbyte\r
+ );\r
+ SCL_INOUT <= '0' when (scl_o = '0') else 'Z';\r
+ \r
+ COMMAND_BUSY_OUT <= command_busy_o;\r
+ I2C_DATA_OUT <= i2c_data_internal_o;\r
\r
-- Slave Bus\r
SLV_DATA_OUT <= slv_data_out_o; \r
S_UNSET_SCL2,\r
S_NEXT_BIT,\r
\r
- S_SET_ACK,\r
- S_ACK_SET_SCL,\r
- S_ACK_UNSET_SCL\r
+ S_NACK_SET,\r
+ S_NACK_SET_SCL,\r
+ S_NACK_UNSET_SCL\r
);\r
signal STATE, NEXT_STATE : STATES;\r
\r
NEXT_STATE <= S_UNSET_SCL1;\r
else\r
wait_timer_init_x <= I2C_SPEED srl 2;\r
- NEXT_STATE <= S_SET_ACK;\r
+ NEXT_STATE <= S_NACK_SET;\r
end if;\r
\r
- -- I2C Send ACK Sequence (doesn't work, so just send a clock)\r
- when S_SET_ACK =>\r
- --sda_o <= '0';\r
+ -- I2C Send NOT_ACK (NACK) Sequence to tell client to release the bus\r
+ when S_NACK_SET =>\r
scl_o <= '0';\r
if (wait_timer_done = '0') then\r
- NEXT_STATE <= S_SET_ACK;\r
+ NEXT_STATE <= S_NACK_SET;\r
else\r
wait_timer_init_x <= I2C_SPEED srl 1;\r
- NEXT_STATE <= S_ACK_SET_SCL;\r
+ NEXT_STATE <= S_NACK_SET_SCL;\r
end if;\r
\r
- when S_ACK_SET_SCL =>\r
- -- sda_o <= '0';\r
+ when S_NACK_SET_SCL =>\r
if (wait_timer_done = '0') then\r
- NEXT_STATE <= S_ACK_SET_SCL;\r
+ NEXT_STATE <= S_NACK_SET_SCL;\r
else\r
wait_timer_init_x <= I2C_SPEED srl 2;\r
- NEXT_STATE <= S_ACK_UNSET_SCL;\r
+ NEXT_STATE <= S_NACK_UNSET_SCL;\r
end if; \r
\r
- when S_ACK_UNSET_SCL =>\r
- --sda_o <= '0';\r
+ when S_NACK_UNSET_SCL =>\r
scl_o <= '0';\r
if (wait_timer_done = '0') then\r
- NEXT_STATE <= S_ACK_UNSET_SCL;\r
+ NEXT_STATE <= S_NACK_UNSET_SCL;\r
else\r
sequence_done_o_x <= '1';\r
NEXT_STATE <= S_IDLE;\r
SDA_OUT : out std_logic;\r
SCL_OUT : out std_logic;\r
SDA_IN : in std_logic;\r
+ SCL_IN : in std_logic;\r
ACK_OUT : out std_logic\r
);\r
end entity;\r
signal bit_ctr : unsigned(3 downto 0);\r
signal i2c_ack_o : std_logic;\r
signal wait_timer_init : unsigned(11 downto 0);\r
-\r
+ signal stretch_timeout : unsigned(19 downto 0);\r
+ \r
signal sequence_done_o_x : std_logic;\r
signal i2c_byte_x : unsigned(7 downto 0);\r
signal bit_ctr_x : unsigned(3 downto 0);\r
signal i2c_ack_o_x : std_logic;\r
signal wait_timer_init_x : unsigned(11 downto 0);\r
+ signal stretch_timeout_x : unsigned(19 downto 0);\r
\r
type STATES is (S_IDLE,\r
S_INIT,\r
S_SET_SCL,\r
S_UNSET_SCL,\r
S_NEXT_BIT,\r
-\r
- S_GET_ACK,\r
+ \r
+ S_ACK_UNSET_SCL,\r
S_ACK_SET_SCL,\r
- S_STORE_ACK,\r
- S_ACK_UNSET_SCL\r
+ S_STRETCH_CHECK_SCL,\r
+ S_STRETCH_WAIT_SCL,\r
+ S_STRETCH_PAUSE,\r
+ S_ACK_STORE,\r
+ S_ACK_UNSET_SCL2\r
);\r
signal STATE, NEXT_STATE : STATES;\r
\r
bit_ctr <= (others => '0');\r
i2c_ack_o <= '0';\r
wait_timer_init <= (others => '0');\r
+ stretch_timeout <= (others => '0');\r
STATE <= S_IDLE;\r
else\r
sequence_done_o <= sequence_done_o_x;\r
bit_ctr <= bit_ctr_x;\r
i2c_ack_o <= i2c_ack_o_x;\r
wait_timer_init <= wait_timer_init_x;\r
+ stretch_timeout <= stretch_timeout_x;\r
STATE <= NEXT_STATE;\r
end if;\r
end if;\r
bit_ctr_x <= bit_ctr; \r
i2c_ack_o_x <= i2c_ack_o;\r
wait_timer_init_x <= (others => '0');\r
+ stretch_timeout_x <= stretch_timeout;\r
\r
case STATE is\r
when S_IDLE =>\r
if (START_IN = '1') then\r
- sda_o <= '0';\r
- scl_o <= '0';\r
- i2c_byte_x <= BYTE_IN;\r
- NEXT_STATE <= S_INIT;\r
+ sda_o <= '0';\r
+ scl_o <= '0';\r
+ i2c_byte_x <= BYTE_IN;\r
+ NEXT_STATE <= S_INIT;\r
else\r
- NEXT_STATE <= S_IDLE;\r
+ NEXT_STATE <= S_IDLE;\r
end if;\r
\r
-- INIT\r
when S_INIT =>\r
- sda_o <= '0';\r
- scl_o <= '0';\r
- wait_timer_init_x <= I2C_SPEED srl 1;\r
- NEXT_STATE <= S_INIT_WAIT;\r
+ sda_o <= '0';\r
+ scl_o <= '0';\r
+ wait_timer_init_x <= I2C_SPEED srl 1;\r
+ NEXT_STATE <= S_INIT_WAIT;\r
\r
when S_INIT_WAIT =>\r
- sda_o <= '0';\r
- scl_o <= '0';\r
+ sda_o <= '0';\r
+ scl_o <= '0';\r
if (wait_timer_done = '0') then\r
- NEXT_STATE <= S_INIT_WAIT;\r
+ NEXT_STATE <= S_INIT_WAIT;\r
else\r
- NEXT_STATE <= S_SEND_BYTE;\r
+ NEXT_STATE <= S_SEND_BYTE;\r
end if;\r
\r
-- I2C Send byte\r
when S_SEND_BYTE =>\r
- sda_o <= '0';\r
- scl_o <= '0';\r
- bit_ctr_x <= x"7";\r
- wait_timer_init_x <= I2C_SPEED srl 2;\r
- NEXT_STATE <= S_SET_SDA;\r
+ sda_o <= '0';\r
+ scl_o <= '0';\r
+ bit_ctr_x <= x"7";\r
+ wait_timer_init_x <= I2C_SPEED srl 2;\r
+ NEXT_STATE <= S_SET_SDA;\r
\r
when S_SET_SDA =>\r
- sda_o <= i2c_byte(7);\r
- scl_o <= '0';\r
+ sda_o <= i2c_byte(7);\r
+ scl_o <= '0';\r
if (wait_timer_done = '0') then\r
- NEXT_STATE <= S_SET_SDA;\r
+ NEXT_STATE <= S_SET_SDA;\r
else\r
- wait_timer_init_x <= I2C_SPEED srl 1;\r
- NEXT_STATE <= S_SET_SCL;\r
+ wait_timer_init_x <= I2C_SPEED srl 1;\r
+ NEXT_STATE <= S_SET_SCL;\r
end if;\r
\r
when S_SET_SCL =>\r
- sda_o <= i2c_byte(7);\r
+ sda_o <= i2c_byte(7);\r
if (wait_timer_done = '0') then\r
- NEXT_STATE <= S_SET_SCL;\r
+ NEXT_STATE <= S_SET_SCL;\r
else\r
- wait_timer_init_x <= I2C_SPEED srl 2;\r
- NEXT_STATE <= S_UNSET_SCL;\r
+ wait_timer_init_x <= I2C_SPEED srl 2;\r
+ NEXT_STATE <= S_UNSET_SCL;\r
end if;\r
\r
when S_UNSET_SCL =>\r
- sda_o <= i2c_byte(7);\r
- scl_o <= '0';\r
+ sda_o <= i2c_byte(7);\r
+ scl_o <= '0';\r
if (wait_timer_done = '0') then\r
- NEXT_STATE <= S_UNSET_SCL;\r
+ NEXT_STATE <= S_UNSET_SCL;\r
else\r
- NEXT_STATE <= S_NEXT_BIT;\r
+ NEXT_STATE <= S_NEXT_BIT;\r
end if;\r
\r
when S_NEXT_BIT =>\r
- sda_o <= i2c_byte(7);\r
- scl_o <= '0';\r
+ sda_o <= i2c_byte(7);\r
+ scl_o <= '0';\r
if (bit_ctr > 0) then\r
- bit_ctr_x <= bit_ctr - 1;\r
- i2c_byte_x <= i2c_byte sll 1;\r
- wait_timer_init_x <= I2C_SPEED srl 2;\r
- NEXT_STATE <= S_SET_SDA;\r
+ bit_ctr_x <= bit_ctr - 1;\r
+ i2c_byte_x <= i2c_byte sll 1;\r
+ wait_timer_init_x <= I2C_SPEED srl 2;\r
+ NEXT_STATE <= S_SET_SDA;\r
else\r
- wait_timer_init_x <= I2C_SPEED srl 2;\r
- NEXT_STATE <= S_GET_ACK;\r
+ wait_timer_init_x <= I2C_SPEED srl 2;\r
+ NEXT_STATE <= S_ACK_UNSET_SCL;\r
end if;\r
\r
- -- I2C Check ACK Sequence\r
- when S_GET_ACK =>\r
- scl_o <= '0';\r
+ -- Get Slave ACK bit\r
+ when S_ACK_UNSET_SCL =>\r
+ scl_o <= '0';\r
if (wait_timer_done = '0') then\r
- NEXT_STATE <= S_GET_ACK;\r
+ NEXT_STATE <= S_ACK_UNSET_SCL;\r
else\r
- wait_timer_init_x <= I2C_SPEED srl 2;\r
- NEXT_STATE <= S_ACK_SET_SCL;\r
+ wait_timer_init_x <= I2C_SPEED srl 2;\r
+ NEXT_STATE <= S_ACK_SET_SCL;\r
end if;\r
\r
when S_ACK_SET_SCL =>\r
if (wait_timer_done = '0') then\r
- NEXT_STATE <= S_ACK_SET_SCL;\r
+ NEXT_STATE <= S_ACK_SET_SCL;\r
else\r
- wait_timer_init_x <= I2C_SPEED srl 2;\r
- NEXT_STATE <= S_STORE_ACK;\r
- end if; \r
+ NEXT_STATE <= S_STRETCH_CHECK_SCL;\r
+ end if;\r
\r
- when S_STORE_ACK =>\r
+ -- Check for Clock Stretching\r
+ when S_STRETCH_CHECK_SCL =>\r
+ if (SCL_IN = '1') then\r
+ wait_timer_init_x <= I2C_SPEED srl 2;\r
+ NEXT_STATE <= S_ACK_STORE;\r
+ else\r
+ stretch_timeout_x <= (others => '0');\r
+ NEXT_STATE <= S_STRETCH_WAIT_SCL;\r
+ end if;\r
+ \r
+ when S_STRETCH_WAIT_SCL =>\r
+ if (SCL_IN = '0') then\r
+ if (stretch_timeout < x"30d40") then\r
+ stretch_timeout_x <= stretch_timeout + 1;\r
+ NEXT_STATE <= S_STRETCH_WAIT_SCL;\r
+ else\r
+ i2c_ack_o_x <= '0';\r
+ wait_timer_init_x <= I2C_SPEED srl 2;\r
+ NEXT_STATE <= S_ACK_UNSET_SCL;\r
+ end if;\r
+ else\r
+ wait_timer_init_x <= I2C_SPEED srl 2;\r
+ NEXT_STATE <= S_STRETCH_PAUSE;\r
+ end if;\r
+ \r
+ when S_STRETCH_PAUSE =>\r
if (wait_timer_done = '0') then\r
- NEXT_STATE <= S_STORE_ACK;\r
+ NEXT_STATE <= S_STRETCH_PAUSE;\r
else\r
- i2c_ack_o_x <= not SDA_IN;\r
- wait_timer_init_x <= I2C_SPEED srl 2;\r
- NEXT_STATE <= S_ACK_UNSET_SCL;\r
+ wait_timer_init_x <= I2C_SPEED srl 2;\r
+ NEXT_STATE <= S_ACK_STORE;\r
end if;\r
\r
- when S_ACK_UNSET_SCL =>\r
- scl_o <= '0';\r
+ -- Read ACK Bit\r
+ when S_ACK_STORE =>\r
+ if (wait_timer_done = '0') then\r
+ NEXT_STATE <= S_ACK_STORE;\r
+ else\r
+ i2c_ack_o_x <= not SDA_IN;\r
+ wait_timer_init_x <= I2C_SPEED srl 2;\r
+ NEXT_STATE <= S_ACK_UNSET_SCL2;\r
+ end if;\r
+ \r
+ when S_ACK_UNSET_SCL2 =>\r
+ scl_o <= '0';\r
if (wait_timer_done = '0') then\r
- NEXT_STATE <= S_ACK_UNSET_SCL;\r
+ NEXT_STATE <= S_ACK_UNSET_SCL2;\r
else\r
- sequence_done_o_x <= '1';\r
- NEXT_STATE <= S_IDLE;\r
+ sequence_done_o_x <= '1';\r
+ NEXT_STATE <= S_IDLE;\r
end if;\r
\r
end case;\r
library work;\r
use work.trb_net_std.all;\r
use work.trb_net_components.all;\r
-use work.trb3_components.all;\r
\r
entity nx_setup is\r
port(\r
-- Write I2C Registers\r
type W_STATES is (W_IDLE,\r
W_NEXT_REGISTER,\r
- W_NOP,\r
W_REGISTER,\r
W_WAIT_DONE\r
);\r
\r
signal W_STATE, W_STATE_RETURN : W_STATES;\r
\r
- signal write_defaults_start : std_logic;\r
- signal write_i2c_command : std_logic_vector(31 downto 0);\r
- signal write_i2c_lock : std_logic; \r
- signal w_register_ctr : unsigned(7 downto 0);\r
\r
- signal nx_ram_output_addr_i : std_logic_vector(5 downto 0);\r
- signal nx_ram_input_addr_i : std_logic_vector(5 downto 0);\r
- signal nx_ram_input_i : std_logic_vector(7 downto 0);\r
- signal nx_ram_write_i : std_logic;\r
-\r
+ signal nx_write_i2c_command : std_logic_vector(31 downto 0);\r
+ signal nx_write_i2c_lock : std_logic; \r
+ signal w_register_ctr : unsigned(5 downto 0);\r
+ \r
-- Read I2C Registers\r
type R_STATES is (R_IDLE,\r
R_REGISTER,\r
\r
signal R_STATE, R_STATE_RETURN : R_STATES;\r
\r
- signal read_defaults_start : std_logic;\r
- signal read_i2c_command : std_logic_vector(31 downto 0);\r
- signal read_i2c_lock : std_logic; \r
- signal r_register_ctr : unsigned(7 downto 0);\r
- \r
- -- RAM Handler\r
- signal nx_ram_input_addr : std_logic_vector(5 downto 0);\r
- signal nx_ram_input : std_logic_vector(7 downto 0);\r
- signal nx_ram_write : std_logic;\r
+ signal nx_read_i2c_command : std_logic_vector(31 downto 0);\r
+ signal nx_read_i2c_lock : std_logic; \r
+ signal r_register_ctr : unsigned(5 downto 0);\r
+\r
+ -- Write DAC I2C Registers\r
+ type DW_STATES is (DW_IDLE,\r
+ DW_NEXT_REGISTER,\r
+ DW_REGISTER,\r
+ DW_WAIT_DONE\r
+ );\r
+ signal DW_STATE, DW_STATE_RETURN : DW_STATES;\r
+\r
+ signal dac_write_i2c_command : std_logic_vector(31 downto 0);\r
+ signal dac_write_i2c_lock : std_logic; \r
+ signal w_fifo_ctr : unsigned(7 downto 0);\r
\r
- signal nx_ram_output_addr : std_logic_vector(5 downto 0);\r
- signal nx_ram_output : std_logic_vector(7 downto 0);\r
+ -- Read DAC I2C Registers\r
+ type DR_STATES is (DR_IDLE,\r
+ DR_REGISTER,\r
+ DR_WRITE_BACK,\r
+ DR_NEXT_REGISTER,\r
+ DR_WAIT_DONE\r
+ );\r
\r
+ signal DR_STATE, DR_STATE_RETURN : DR_STATES;\r
+ \r
+\r
+ signal dac_read_i2c_command : std_logic_vector(31 downto 0);\r
+ signal dac_read_i2c_lock : std_logic; \r
+ signal r_fifo_ctr : unsigned(7 downto 0);\r
+\r
-- TRBNet Slave Bus\r
signal slv_data_out_o : std_logic_vector(31 downto 0);\r
signal slv_no_more_data_o : std_logic;\r
signal slv_unknown_addr_o : std_logic;\r
signal slv_ack_o : std_logic;\r
\r
- signal nx_ram_output_addr_s : std_logic_vector(5 downto 0);\r
- signal nx_ram_input_addr_s : std_logic_vector(5 downto 0);\r
- signal nx_ram_input_s : std_logic_vector(7 downto 0);\r
- signal nx_ram_write_s : std_logic;\r
+ signal read_nx_i2c_all_start : std_logic;\r
+ signal write_nx_i2c_all_start : std_logic;\r
+ \r
+ signal read_dac_all_start : std_logic;\r
+ signal write_dac_all_start : std_logic;\r
+\r
+ -- I2C Register Ram\r
+ type i2c_ram_t is array(0 to 45) of std_logic_vector(7 downto 0);\r
+ signal i2c_ram : i2c_ram_t;\r
+ signal i2c_ram_write_0 : std_logic;\r
+ signal i2c_ram_write_1 : std_logic;\r
+ signal i2c_ram_input_addr_0 : unsigned(5 downto 0);\r
+ signal i2c_ram_input_addr_1 : unsigned(5 downto 0);\r
+ signal i2c_ram_input_0 : std_logic_vector(7 downto 0);\r
+ signal i2c_ram_input_1 : std_logic_vector(7 downto 0);\r
\r
- signal register_mem_read_s : std_logic;\r
- signal register_mem_read : std_logic;\r
-\r
type register_access_type_t is array(0 to 45) of std_logic;\r
constant register_access_type : register_access_type_t :=\r
- ('1','1','1','1','1','1','1','1', -- 7\r
- '1','1','1','1','1','1','1','1', -- 15\r
- '1','1','1','1','1','1','1','1', -- 23\r
- '1','1','1','1','1','1','0','0', -- 31\r
- '1','1','0','0','0','0','1','1', --39\r
- '0','0','1','1','1','1' -- 45\r
+ ('1', '1', '1', '1', '1', '1', '1', '1', -- 0 -> 7\r
+ '1', '1', '1', '1', '1', '1', '1', '1', -- 8 -> 15\r
+ '1', '1', '1', '1', '1', '1', '1', '1', -- 16 -> 23\r
+ '1', '1', '1', '1', '1', '1', '0', '0', -- 24 -> 31 \r
+ '1', '1', '0', '0', '0', '0', '1', '1', -- 32 -> 39\r
+ '0', '0', '0', '1', '1', '1' -- 40 -> 45\r
);\r
-\r
-\r
- signal read_write_ding : std_logic;\r
\r
+ -- DAC Trim FIFO RAM\r
+ type dac_ram_t is array(0 to 129) of std_logic_vector(5 downto 0);\r
+ signal dac_ram : dac_ram_t;\r
+ signal dac_ram_write_0 : std_logic;\r
+ signal dac_ram_write_1 : std_logic;\r
+ signal dac_ram_input_addr_0 : unsigned(7 downto 0);\r
+ signal dac_ram_input_addr_1 : unsigned(7 downto 0);\r
+ signal dac_ram_input_0 : std_logic_vector(5 downto 0);\r
+ signal dac_ram_input_1 : std_logic_vector(5 downto 0);\r
+\r
+ signal ctr : std_logic_vector(5 downto 0);\r
+ signal i2c_ram_write_d : std_logic;\r
+ signal dac_ram_write_d : std_logic;\r
begin\r
\r
-----------------------------------------------------------------------------\r
-----------------------------------------------------------------------------\r
\r
DEBUG_OUT(0) <= CLK_IN;\r
- DEBUG_OUT(1) <= read_defaults_start;\r
- DEBUG_OUT(2) <= write_defaults_start;\r
- DEBUG_OUT(3) <= i2c_lock_o;\r
- DEBUG_OUT(4) <= i2c_command_busy;\r
- DEBUG_OUT(5) <= i2c_command_done;\r
- DEBUG_OUT(6) <= I2C_COMMAND_BUSY_IN;\r
- DEBUG_OUT(7) <= register_mem_read_s;\r
- DEBUG_OUT(8) <= register_mem_read;\r
- DEBUG_OUT(15 downto 9) <= (others => '0'); \r
+ DEBUG_OUT(1) <= read_nx_i2c_all_start;\r
+ DEBUG_OUT(2) <= write_nx_i2c_all_start;\r
+ DEBUG_OUT(3) <= read_dac_all_start;\r
+ DEBUG_OUT(4) <= write_dac_all_start;\r
+\r
+ DEBUG_OUT(5) <= i2c_lock_o;\r
+ DEBUG_OUT(6) <= i2c_command_busy;\r
+ DEBUG_OUT(7) <= i2c_command_done;\r
+ DEBUG_OUT(8) <= I2C_COMMAND_BUSY_IN;\r
+ \r
+ DEBUG_OUT(9) <= i2c_ram_write_d;\r
+ DEBUG_OUT(10) <= i2c_ram_write_0;\r
+ DEBUG_OUT(11) <= i2c_ram_write_1;\r
+ DEBUG_OUT(12) <= dac_ram_write_d;\r
+ DEBUG_OUT(13) <= dac_ram_write_0;\r
+ DEBUG_OUT(14) <= dac_ram_write_1;\r
+ DEBUG_OUT(15) <= '0';\r
+\r
+ --DEBUG_OUT(14 downto 9) <= ctr;\r
+ ctr <= std_logic_vector(r_register_ctr) or std_logic_vector(w_register_ctr);\r
\r
-----------------------------------------------------------------------------\r
- \r
- -- Simple RAM to hold all nXyter I2C register settings\r
\r
- \r
- ram_dp_1: ram_dp\r
- generic map (\r
- depth => 6,\r
- width => 8\r
- )\r
- port map (\r
- CLK => CLK_IN,\r
- wr1 => nx_ram_write,\r
- a1 => nx_ram_input_addr,\r
- dout1 => open,\r
- din1 => nx_ram_input,\r
- a2 => nx_ram_output_addr,\r
- dout2 => nx_ram_output \r
- );\r
-\r
- nx_ram_output_addr <= nx_ram_output_addr_s or nx_ram_output_addr_i;\r
- nx_ram_input_addr <= nx_ram_input_addr_s or nx_ram_input_addr_i;\r
- nx_ram_input <= nx_ram_input_s or nx_ram_input_i;\r
- nx_ram_write <= nx_ram_write_s or nx_ram_write_i;\r
- \r
- ----------------------------------------------------------------------\r
+ PROC_I2C_RAM_WRITE_HANDLER: process(CLK_IN)\r
+ begin\r
+ if( rising_edge(CLK_IN) ) then\r
+ if( RESET_IN = '1' ) then\r
+ i2c_ram_write_d <= '0';\r
+ else\r
+ i2c_ram_write_d <= '0';\r
+ if (i2c_ram_write_0 = '1') then\r
+ i2c_ram(to_integer(i2c_ram_input_addr_0)) <= i2c_ram_input_0;\r
+ i2c_ram_write_d <= '1';\r
+ elsif (i2c_ram_write_1 = '1') then\r
+ i2c_ram(to_integer(i2c_ram_input_addr_1)) <= i2c_ram_input_1;\r
+ i2c_ram_write_d <= '1';\r
+ end if;\r
+ end if;\r
+ end if;\r
+ end process PROC_I2C_RAM_WRITE_HANDLER;\r
\r
- i2c_lock_o <= write_i2c_lock or read_i2c_lock;\r
- i2c_command <= write_i2c_command or read_i2c_command;\r
+ PROC_DAC_RAM_WRITE_HANDLER: process(CLK_IN)\r
+ begin\r
+ if( rising_edge(CLK_IN) ) then\r
+ if( RESET_IN = '1' ) then\r
+ dac_ram_write_d <= '0';\r
+ else\r
+ dac_ram_write_d <= '0';\r
+ if (dac_ram_write_0 = '1') then\r
+ dac_ram(to_integer(dac_ram_input_addr_0)) <= dac_ram_input_0;\r
+ dac_ram_write_d <= '1';\r
+ elsif (dac_ram_write_1 = '1') then\r
+ dac_ram(to_integer(dac_ram_input_addr_1)) <= dac_ram_input_1;\r
+ dac_ram_write_d <= '1';\r
+ end if;\r
+ end if;\r
+ end if;\r
+ end process PROC_DAC_RAM_WRITE_HANDLER;\r
+ \r
+ -----------------------------------------------------------------------------\r
+\r
+ i2c_lock_o <= nx_write_i2c_lock or\r
+ nx_read_i2c_lock or\r
+ dac_read_i2c_lock;\r
+ i2c_command <= nx_write_i2c_command or\r
+ nx_read_i2c_command or\r
+ dac_read_i2c_command;\r
\r
PROC_SEND_I2C_COMMAND: process(CLK_IN)\r
begin\r
end if;\r
end process PROC_SEND_I2C_COMMAND;\r
\r
-PROC_WRITE_REGISTERS: process(CLK_IN)\r
+ -----------------------------------------------------------------------------\r
+ \r
+ PROC_READ_NX_REGISTERS: process(CLK_IN)\r
begin\r
if( rising_edge(CLK_IN) ) then\r
if( RESET_IN = '1' ) then\r
- write_i2c_lock <= '0';\r
- write_i2c_command <= (others => '0');\r
- w_register_ctr <= (others => '0');\r
+ nx_read_i2c_command <= (others => '0');\r
+ nx_read_i2c_lock <= '0';\r
+ i2c_ram_input_0 <= (others => '0');\r
+ i2c_ram_input_addr_0 <= (others => '0');\r
+ i2c_ram_write_0 <= '0';\r
+ r_register_ctr <= (others => '0');\r
\r
- nx_ram_output_addr_i <= (others => '0');\r
-\r
- W_STATE_RETURN <= W_IDLE;\r
- W_STATE <= W_IDLE;\r
+ R_STATE_RETURN <= R_IDLE;\r
+ R_STATE <= R_IDLE;\r
else\r
- write_i2c_command <= (others => '0');\r
- write_i2c_lock <= '1';\r
+ nx_read_i2c_command <= (others => '0');\r
+ nx_read_i2c_lock <= '1';\r
+ i2c_ram_input_0 <= (others => '0');\r
+ i2c_ram_input_addr_0 <= (others => '0');\r
+ i2c_ram_write_0 <= '0';\r
+\r
+ case R_STATE is\r
+ when R_IDLE =>\r
+ if (read_nx_i2c_all_start = '1') then\r
+ R_STATE <= R_REGISTER;\r
+ else\r
+ nx_read_i2c_lock <= '0';\r
+ R_STATE <= R_IDLE;\r
+ end if;\r
+ r_register_ctr <= (others => '0');\r
+\r
+ when R_REGISTER =>\r
+ if (register_access_type(to_integer(r_register_ctr)) = '1') then\r
+ nx_read_i2c_command(31 downto 16) <= x"ff08";\r
+ nx_read_i2c_command(15 downto 14) <= (others => '0');\r
+ nx_read_i2c_command(13 downto 8) <= r_register_ctr;\r
+ nx_read_i2c_command( 7 downto 0) <= (others => '0');\r
+ R_STATE_RETURN <= R_NEXT_REGISTER;\r
+ R_STATE <= R_WAIT_DONE;\r
+ else\r
+ R_STATE <= R_NEXT_REGISTER;\r
+ end if;\r
+ \r
+ when R_NEXT_REGISTER =>\r
+ if (register_access_type(to_integer(r_register_ctr)) = '1') then\r
+ i2c_ram_input_0 <= i2c_data(7 downto 0);\r
+ else\r
+ i2c_ram_input_0 <= x"be";\r
+ end if;\r
+ i2c_ram_input_addr_0 <= r_register_ctr;\r
+ i2c_ram_write_0 <= '1';\r
+\r
+ if (r_register_ctr <= x"2d") then\r
+ r_register_ctr <= r_register_ctr + 1;\r
+ R_STATE <= R_REGISTER;\r
+ else\r
+ R_STATE <= R_IDLE;\r
+ end if;\r
+ \r
+ when R_WAIT_DONE =>\r
+ if (i2c_command_done = '0') then\r
+ R_STATE <= R_WAIT_DONE;\r
+ else\r
+ R_STATE <= R_STATE_RETURN;\r
+ end if;\r
+\r
+ end case;\r
+ end if;\r
+ end if;\r
+ end process PROC_READ_NX_REGISTERS;\r
\r
- nx_ram_output_addr_i <= (others => '0');\r
- read_write_ding <= '0';\r
+ PROC_WRITE_NX_REGISTERS: process(CLK_IN)\r
+ begin\r
+ if( rising_edge(CLK_IN) ) then\r
+ if( RESET_IN = '1' ) then\r
+ nx_write_i2c_lock <= '0';\r
+ nx_write_i2c_command <= (others => '0');\r
+ w_register_ctr <= (others => '0');\r
+ \r
+ W_STATE_RETURN <= W_IDLE;\r
+ W_STATE <= W_IDLE;\r
+ else\r
+ nx_write_i2c_command <= (others => '0');\r
+ nx_write_i2c_lock <= '1';\r
\r
case W_STATE is\r
\r
when W_IDLE =>\r
- if (write_defaults_start = '1') then\r
- w_register_ctr <= (others => '0');\r
- W_STATE <= W_NEXT_REGISTER;\r
+ if (write_nx_i2c_all_start = '1') then\r
+ W_STATE <= W_NEXT_REGISTER;\r
else\r
- write_i2c_lock <= '0';\r
- W_STATE <= W_IDLE;\r
+ nx_write_i2c_lock <= '0';\r
+ W_STATE <= W_IDLE;\r
end if;\r
+ w_register_ctr <= (others => '0');\r
\r
when W_NEXT_REGISTER =>\r
if (w_register_ctr <= x"2d") then\r
- nx_ram_output_addr_i <= w_register_ctr(5 downto 0);\r
- W_STATE <= W_NOP;\r
+ W_STATE <= W_REGISTER;\r
else\r
- W_STATE <= W_IDLE;\r
+ W_STATE <= W_IDLE;\r
end if;\r
-\r
- when W_NOP =>\r
- read_write_ding <= '1';\r
- W_STATE <= W_REGISTER;\r
\r
when W_REGISTER =>\r
if (register_access_type(\r
to_integer(unsigned(w_register_ctr))) = '1') \r
then\r
- write_i2c_command(31 downto 16) <= x"bf08";\r
- write_i2c_command(15 downto 8) <= w_register_ctr;\r
- write_i2c_command(7 downto 0) <= nx_ram_output;\r
- W_STATE_RETURN <= W_NEXT_REGISTER;\r
- W_STATE <= W_WAIT_DONE;\r
+ nx_write_i2c_command(31 downto 16) <= x"bf08";\r
+ nx_write_i2c_command(15 downto 14) <= (others => '0');\r
+ nx_write_i2c_command(13 downto 8) <= w_register_ctr;\r
+ nx_write_i2c_command( 7 downto 0) <=\r
+ i2c_ram(to_integer(unsigned(w_register_ctr)));\r
+ W_STATE_RETURN <= W_NEXT_REGISTER;\r
+ W_STATE <= W_WAIT_DONE;\r
else\r
- W_STATE <= W_NEXT_REGISTER;\r
+ W_STATE <= W_NEXT_REGISTER;\r
end if;\r
\r
- w_register_ctr <= w_register_ctr + 1;\r
+ w_register_ctr <= w_register_ctr + 1;\r
\r
when W_WAIT_DONE =>\r
if (i2c_command_done = '0') then\r
- W_STATE <= W_WAIT_DONE;\r
+ W_STATE <= W_WAIT_DONE;\r
else\r
- W_STATE <= W_STATE_RETURN;\r
+ W_STATE <= W_STATE_RETURN;\r
end if;\r
\r
end case;\r
end if;\r
end if;\r
- end process PROC_WRITE_REGISTERS;\r
+ end process PROC_WRITE_NX_REGISTERS;\r
\r
- PROC_READ_REGISTERS: process(CLK_IN)\r
+ -----------------------------------------------------------------------------\r
+\r
+ PROC_READ_DAC_REGISTERS: process(CLK_IN)\r
begin\r
if( rising_edge(CLK_IN) ) then\r
if( RESET_IN = '1' ) then\r
- read_i2c_command <= (others => '0');\r
- read_i2c_lock <= '0';\r
- r_register_ctr <= (others => '0');\r
-\r
- nx_ram_input_addr_i <= (others => '0');\r
- nx_ram_input_i <= (others => '0');\r
- nx_ram_write_i <= '0';\r
-\r
- R_STATE_RETURN <= R_IDLE;\r
- R_STATE <= R_IDLE;\r
+ dac_read_i2c_command <= (others => '0');\r
+ dac_read_i2c_lock <= '0';\r
+ dac_ram_write_0 <= '0';\r
+ dac_ram_input_addr_0 <= (others => '0');\r
+ dac_ram_input_0 <= (others => '0');\r
+ r_fifo_ctr <= (others => '0');\r
+\r
+ DR_STATE_RETURN <= DR_IDLE;\r
+ DR_STATE <= DR_IDLE;\r
else\r
- read_i2c_command <= (others => '0');\r
- read_i2c_lock <= '1';\r
-\r
- nx_ram_input_addr_i <= (others => '0');\r
- nx_ram_input_i <= (others => '0');\r
- nx_ram_write_i <= '0';\r
-\r
- case R_STATE is\r
- when R_IDLE =>\r
- if (read_defaults_start = '1') then\r
- r_register_ctr <= (others => '0');\r
- R_STATE <= R_REGISTER;\r
- else\r
- read_i2c_lock <= '0';\r
- R_STATE <= R_IDLE;\r
- end if;\r
-\r
- when R_REGISTER =>\r
- if (register_access_type(to_integer(r_register_ctr)) = '1') then\r
- read_i2c_command(31 downto 16) <= x"ff08";\r
- read_i2c_command(15 downto 8) <= r_register_ctr;\r
- read_i2c_command(7 downto 0) <= (others => '0');\r
- R_STATE_RETURN <= R_NEXT_REGISTER;\r
- R_STATE <= R_WAIT_DONE;\r
- else\r
- R_STATE <= R_NEXT_REGISTER;\r
- end if;\r
- \r
- when R_NEXT_REGISTER =>\r
- if (register_access_type(to_integer(r_register_ctr)) = '1') then\r
- nx_ram_input_i <= i2c_data(7 downto 0);\r
+ dac_read_i2c_command <= (others => '0');\r
+ dac_read_i2c_lock <= '1';\r
+ dac_ram_write_0 <= '0';\r
+ dac_ram_input_addr_0 <= (others => '0');\r
+ dac_ram_input_0 <= (others => '0');\r
+ \r
+ case DR_STATE is\r
+ when DR_IDLE =>\r
+ if (read_dac_all_start = '1') then\r
+ DR_STATE <= DR_REGISTER;\r
else\r
- nx_ram_input_i <= x"be";\r
+ dac_read_i2c_lock <= '0';\r
+ DR_STATE <= DR_IDLE;\r
end if;\r
- nx_ram_write_i <= '1';\r
- nx_ram_input_addr_i <= r_register_ctr(5 downto 0);\r
+ r_fifo_ctr <= (others => '0');\r
+\r
+ when DR_REGISTER =>\r
+ dac_read_i2c_command(31 downto 16) <= x"ff08";\r
+ dac_read_i2c_command(15 downto 8) <= x"2a"; -- DAC Reg 42\r
+ dac_read_i2c_command(7 downto 0) <= (others => '0');\r
+ DR_STATE_RETURN <= DR_WRITE_BACK;\r
+ DR_STATE <= DR_WAIT_DONE;\r
+\r
+ when DR_WRITE_BACK =>\r
+ -- Store FIFO Entry\r
+ dac_ram_input_0 <= i2c_data(5 downto 0);\r
+ dac_ram_input_addr_0 <= r_fifo_ctr;\r
+ dac_ram_write_0 <= '1';\r
\r
- if (r_register_ctr <= x"2d") then\r
- r_register_ctr <= r_register_ctr + 1;\r
- R_STATE <= R_REGISTER;\r
+ -- Write Data Back to FIFO\r
+ dac_read_i2c_command(31 downto 16) <= x"bf08";\r
+ dac_read_i2c_command(15 downto 8) <= x"2a"; -- DAC Reg 42\r
+ dac_read_i2c_command(4 downto 0) <= i2c_data(4 downto 0);\r
+ dac_read_i2c_command(7 downto 5) <= (others => '0');\r
+ DR_STATE_RETURN <= DR_NEXT_REGISTER;\r
+ DR_STATE <= DR_WAIT_DONE;\r
+ \r
+ when DR_NEXT_REGISTER =>\r
+ if (r_fifo_ctr <= x"81") then\r
+ r_fifo_ctr <= r_fifo_ctr + 1;\r
+ DR_STATE <= DR_REGISTER;\r
else\r
- R_STATE <= R_IDLE;\r
+ DR_STATE <= DR_IDLE;\r
end if;\r
\r
- when R_WAIT_DONE =>\r
+ when DR_WAIT_DONE =>\r
if (i2c_command_done = '0') then\r
- R_STATE <= R_WAIT_DONE;\r
+ DR_STATE <= DR_WAIT_DONE;\r
else\r
- R_STATE <= R_STATE_RETURN;\r
+ DR_STATE <= DR_STATE_RETURN;\r
end if;\r
\r
end case;\r
end if;\r
end if;\r
- end process PROC_READ_REGISTERS;\r
- \r
+ end process PROC_READ_DAC_REGISTERS;\r
+ \r
+ -----------------------------------------------------------------------------\r
+ \r
PROC_SLAVE_BUS: process(CLK_IN)\r
+ variable mem_address : unsigned(7 downto 0) := x"00";\r
+\r
begin\r
if( rising_edge(CLK_IN) ) then\r
if( RESET_IN = '1' ) then\r
- slv_data_out_o <= (others => '0');\r
- slv_no_more_data_o <= '0';\r
- slv_unknown_addr_o <= '0';\r
- slv_ack_o <= '0';\r
- write_defaults_start <= '0';\r
- read_defaults_start <= '0';\r
- register_mem_read_s <= '0';\r
- register_mem_read <= '0';\r
- nx_ram_output_addr_s <= (others => '0'); \r
- nx_ram_input_addr_s <= (others => '0');\r
- nx_ram_input_s <= (others => '0');\r
- nx_ram_write_s <= '0';\r
+ slv_data_out_o <= (others => '0');\r
+ slv_no_more_data_o <= '0';\r
+ slv_unknown_addr_o <= '0';\r
+ slv_ack_o <= '0';\r
+\r
+ read_nx_i2c_all_start <= '0';\r
+ write_nx_i2c_all_start <= '0';\r
+ read_dac_all_start <= '0';\r
+ write_dac_all_start <= '0';\r
+\r
+ i2c_ram_input_1 <= (others => '0');\r
+ i2c_ram_input_addr_1 <= (others => '0');\r
+ i2c_ram_write_1 <= '0';\r
+ dac_ram_input_1 <= (others => '0');\r
+ dac_ram_input_addr_1 <= (others => '0');\r
+ dac_ram_write_1 <= '0';\r
else \r
- slv_data_out_o <= (others => '0');\r
- slv_unknown_addr_o <= '0';\r
- slv_no_more_data_o <= '0';\r
- write_defaults_start <= '0';\r
- read_defaults_start <= '0';\r
- register_mem_read_s <= '0';\r
- register_mem_read <= register_mem_read_s;\r
- nx_ram_output_addr_s <= (others => '0');\r
- nx_ram_input_addr_s <= (others => '0');\r
- nx_ram_input_s <= (others => '0');\r
- nx_ram_write_s <= '0';\r
-\r
- if (register_mem_read = '1') then\r
- slv_data_out_o(7 downto 0) <= nx_ram_output;\r
- slv_data_out_o(31 downto 8) <= (others => '0');\r
- slv_ack_o <= '1';\r
-\r
+ slv_data_out_o <= (others => '0');\r
+ slv_unknown_addr_o <= '0';\r
+ slv_no_more_data_o <= '0';\r
+\r
+ read_nx_i2c_all_start <= '0';\r
+ write_nx_i2c_all_start <= '0';\r
+ read_dac_all_start <= '0';\r
+ write_dac_all_start <= '0';\r
+\r
+ i2c_ram_input_1 <= (others => '0');\r
+ i2c_ram_input_addr_1 <= (others => '0');\r
+ i2c_ram_write_1 <= '0';\r
+ dac_ram_input_1 <= (others => '0');\r
+ dac_ram_input_addr_1 <= (others => '0');\r
+ dac_ram_write_1 <= '0';\r
\r
- elsif (SLV_WRITE_IN = '1') then\r
+ if (SLV_WRITE_IN = '1') then\r
if (SLV_ADDR_IN >= x"0000" and SLV_ADDR_IN <= x"002d") then\r
if (i2c_lock_o = '1') then\r
- slv_no_more_data_o <= '1';\r
- slv_ack_o <= '0';\r
+ slv_no_more_data_o <= '1';\r
+ slv_ack_o <= '0';\r
else\r
if (register_access_type(\r
to_integer(unsigned(SLV_ADDR_IN(5 downto 0)))) = '1')\r
then\r
- nx_ram_input_addr_s <= SLV_ADDR_IN(5 downto 0);\r
- nx_ram_input_s <= SLV_DATA_IN(7 downto 0);\r
- nx_ram_write_s <= '1';\r
+ -- Write value to ram\r
+ i2c_ram_input_1 <= SLV_DATA_IN(7 downto 0);\r
+ i2c_ram_input_addr_1 <= unsigned(SLV_ADDR_IN(5 downto 0));\r
+ i2c_ram_write_1 <= '1';\r
+ slv_ack_o <= '1';\r
end if;\r
- slv_ack_o <= '1';\r
+ slv_ack_o <= '1';\r
+ end if;\r
+\r
+ elsif (SLV_ADDR_IN >= x"0060" and SLV_ADDR_IN <= x"00e0") then\r
+ if (i2c_lock_o = '1') then\r
+ slv_no_more_data_o <= '1';\r
+ slv_ack_o <= '0';\r
+ else\r
+ -- Write value to ram\r
+ mem_address := unsigned(SLV_ADDR_IN(7 downto 0)) - x"60";\r
+ dac_ram_input_1 <= SLV_DATA_IN(5 downto 0);\r
+ dac_ram_input_addr_1 <= SLV_ADDR_IN(7 downto 0);\r
+ dac_ram_write_1 <= '1';\r
+ slv_ack_o <= '1';\r
end if;\r
\r
else\r
case SLV_ADDR_IN is\r
when x"0040" =>\r
- write_defaults_start <= '1';\r
- slv_ack_o <= '1';\r
- \r
+ read_nx_i2c_all_start <= '1';\r
+ slv_ack_o <= '1';\r
+\r
when x"0041" =>\r
- read_defaults_start <= '1';\r
- slv_ack_o <= '1';\r
- \r
+ write_nx_i2c_all_start <= '1';\r
+ slv_ack_o <= '1';\r
+\r
+ when x"0042" =>\r
+ read_dac_all_start <= '1';\r
+ slv_ack_o <= '1';\r
+\r
+ when x"0043" =>\r
+ write_dac_all_start <= '1';\r
+ slv_ack_o <= '1';\r
+ \r
when others => \r
- slv_unknown_addr_o <= '1';\r
- slv_ack_o <= '0'; \r
+ slv_unknown_addr_o <= '1';\r
+ slv_ack_o <= '0'; \r
\r
end case; \r
end if;\r
\r
elsif (SLV_READ_IN = '1') then\r
if (SLV_ADDR_IN >= x"0000" and SLV_ADDR_IN <= x"002d") then\r
- nx_ram_output_addr_s <= SLV_ADDR_IN(5 downto 0);\r
- register_mem_read_s <= '1';\r
- slv_ack_o <= '0';\r
+ slv_data_out_o(7 downto 0) <= \r
+ i2c_ram(to_integer(unsigned(SLV_ADDR_IN(5 downto 0))));\r
+ slv_data_out_o(31 downto 8) <= (others => '0');\r
+ slv_ack_o <= '1';\r
+ elsif (SLV_ADDR_IN >= x"0060" and SLV_ADDR_IN <= x"00e0") then\r
+ mem_address := unsigned(SLV_ADDR_IN(7 downto 0)) - x"60";\r
+ slv_data_out_o(5 downto 0) <= dac_ram(to_integer(mem_address));\r
+ slv_data_out_o(31 downto 6) <= (others => '0');\r
+ slv_ack_o <= '1';\r
else\r
- case SLV_ADDR_IN is \r
- when x"0040" => \r
- slv_data_out_o <= x"deadbeef";\r
- slv_ack_o <= '1';\r
- \r
- when x"0041" => \r
- slv_data_out_o <= i2c_data;\r
- slv_ack_o <= '1';\r
- \r
- when others => \r
- slv_unknown_addr_o <= '1';\r
- slv_ack_o <= '0';\r
- \r
- end case; \r
+ slv_unknown_addr_o <= '1';\r
+ slv_ack_o <= '0';\r
end if;\r
-\r
else \r
- slv_ack_o <= '0';\r
+ slv_ack_o <= '0';\r
end if;\r
-\r
+ \r
end if;\r
end if; \r
end process PROC_SLAVE_BUS;\r
CLK_IN : in std_logic;\r
RESET_IN : in std_logic;\r
\r
+ TRIGGER_IN : in std_logic;\r
+ \r
TRIGGER_OUT : out std_logic;\r
TS_RESET_OUT : out std_logic;\r
TESTPULSE_OUT : out std_logic;\r
signal trigger_o : std_logic;\r
signal ts_reset_o : std_logic;\r
signal testpulse_o : std_logic;\r
+ signal extern_trigger : std_logic;\r
\r
type STATES is (S_IDLE,\r
S_NEXT_CYCLE,\r
signal reg_trigger_period : unsigned(15 downto 0);\r
signal reg_testpulse_length : unsigned(15 downto 0);\r
signal reg_trigger_num_cycles : unsigned(7 downto 0); \r
- signal reg_reset_on : std_logic;\r
+ signal reg_ts_reset_on : std_logic;\r
\r
begin\r
\r
DEBUG_OUT(3) <= wait_timer_done;\r
DEBUG_OUT(4) <= ts_reset_o;\r
DEBUG_OUT(5) <= testpulse_o;\r
- DEBUG_OUT(7 downto 6) <= (others => '0');\r
+ DEBUG_OUT(6) <= TRIGGER_IN;\r
+ DEBUG_OUT(7) <= extern_trigger;\r
DEBUG_OUT(15 downto 8) <= trigger_cycle_ctr;\r
\r
-- Timer\r
ts_reset_o <= '0';\r
wait_timer_init <= (others => '0');\r
trigger_cycle_ctr <= (others => '0');\r
+ extern_trigger <= '0';\r
STATE <= S_IDLE;\r
else\r
trigger_o <= '0';\r
testpulse_o <= '0';\r
ts_reset_o <= '0';\r
wait_timer_init <= (others => '0');\r
- trigger_cycle_ctr <= trigger_cycle_ctr;\r
\r
case STATE is\r
when S_IDLE =>\r
if (start_cycle = '1') then\r
trigger_cycle_ctr <= reg_trigger_num_cycles;\r
- if (reg_reset_on = '1') then\r
+ if (reg_ts_reset_on = '1') then\r
ts_reset_o <= '1';\r
wait_timer_init <= reg_trigger_period;\r
STATE <= S_WAIT_TRIGGER_END;\r
else\r
STATE <= S_NEXT_CYCLE;\r
end if;\r
+ extern_trigger <= '0';\r
+ elsif (TRIGGER_IN = '1') then\r
+ trigger_cycle_ctr <= (others => '0');\r
+ wait_timer_init <= reg_testpulse_length;\r
+ extern_trigger <= '1';\r
+ STATE <= S_SET_TESTPULSE;\r
else\r
+ extern_trigger <= '0';\r
STATE <= S_IDLE;\r
end if;\r
\r
if (wait_timer_done = '0') then\r
STATE <= S_SET_TESTPULSE;\r
else\r
- wait_timer_init <= reg_trigger_period - reg_testpulse_length;\r
+ if (extern_trigger = '0') then\r
+ wait_timer_init <= reg_trigger_period - reg_testpulse_length;\r
+ else\r
+ wait_timer_init <= x"0001";\r
+ end if;\r
STATE <= S_WAIT_TRIGGER_END;\r
end if;\r
\r
reg_trigger_period <= x"00ff";\r
reg_trigger_num_cycles <= x"01";\r
reg_testpulse_length <= (others => '0');\r
- reg_reset_on <= '0';\r
+ reg_ts_reset_on <= '0';\r
slv_data_out_o <= (others => '0');\r
slv_no_more_data_o <= '0';\r
slv_unknown_addr_o <= '0';\r
reg_testpulse_length <= unsigned(SLV_DATA_IN(15 downto 0));\r
slv_ack_o <= '1';\r
when x"0004" =>\r
- reg_reset_on <= SLV_DATA_IN(0);\r
+ reg_ts_reset_on <= SLV_DATA_IN(0);\r
slv_ack_o <= '1';\r
when others =>\r
slv_unknown_addr_o <= '1';\r
std_logic_vector(reg_testpulse_length);\r
slv_ack_o <= '1';\r
when x"0004" =>\r
- slv_data_out_o(0) <= reg_reset_on;\r
+ slv_data_out_o(0) <= reg_ts_reset_on;\r
slv_ack_o <= '1';\r
when others =>\r
slv_unknown_addr_o <= '1';\r
\r
-- Internal FPGA Trigger\r
INTERNAL_TRIGGER_IN : in std_logic;\r
- \r
+\r
-- Trigger FeedBack\r
TRIGGER_VALIDATE_BUSY_IN : in std_logic;\r
LVL2_TRIGGER_BUSY_IN : in std_logic;\r
EVENT_BUFFER_CLEAR_OUT : out std_logic;\r
FAST_CLEAR_OUT : out std_logic;\r
TRIGGER_BUSY_OUT : out std_logic;\r
+\r
+ -- Pulser\r
+ TRIGGER_TESTPULSE_OUT : out std_logic;\r
\r
-- Slave bus \r
SLV_READ_IN : in std_logic;\r
signal validate_trigger_o : std_logic;\r
signal timestamp_hold : std_logic;\r
signal lvl2_trigger_o : std_logic;\r
- signal evt_buffer_clear_o : std_logic;\r
+ signal event_buffer_clear_o : std_logic;\r
signal fast_clear_o : std_logic;\r
signal trigger_busy_o : std_logic;\r
signal fee_trg_release_o : std_logic;\r
signal fee_trg_statusbits_o : std_logic_vector(31 downto 0);\r
+ signal trigger_testpulse_o : std_logic;\r
\r
type STATES is (S_IDLE,\r
S_CTS_TRIGGER,\r
\r
-- Timestamp Hold Handler\r
type TS_STATES is (TS_IDLE,\r
- TS_WAIT_TIMER_DONE\r
- );\r
+ TS_WAIT_TIMER_DONE\r
+ );\r
signal TS_STATE : TS_STATES;\r
\r
signal timestamp_hold_o : std_logic;\r
+ signal wait_timer_reset : std_logic;\r
signal wait_timer_init : unsigned(7 downto 0);\r
signal wait_timer_done : std_logic;\r
\r
signal slv_ack_o : std_logic;\r
\r
signal reg_timestamp_hold_delay : unsigned(7 downto 0);\r
+ signal reg_testpulse_enable : std_logic;\r
\r
begin\r
\r
DEBUG_OUT(6) <= validate_trigger_o;\r
DEBUG_OUT(7) <= timestamp_hold_o;\r
DEBUG_OUT(8) <= lvl2_trigger_o;\r
- DEBUG_OUT(9) <= evt_buffer_clear_o;\r
+ DEBUG_OUT(9) <= event_buffer_clear_o;\r
DEBUG_OUT(10) <= fee_trg_release_o;\r
DEBUG_OUT(11) <= trigger_busy_o;\r
\r
)\r
port map (\r
CLK_IN => CLK_IN,\r
- RESET_IN => RESET_IN,\r
+ RESET_IN => wait_timer_reset,\r
TIMER_START_IN => wait_timer_init,\r
TIMER_DONE_OUT => wait_timer_done\r
);\r
\r
+ wait_timer_reset <= RESET_IN or fast_clear_o;\r
+ \r
-----------------------------------------------------------------------------\r
-- Trigger Handler\r
-----------------------------------------------------------------------------\r
lvl2_trigger_o <= '0';\r
fee_trg_release_o <= '0';\r
fee_trg_statusbits_o <= (others => '0');\r
- evt_buffer_clear_o <= '0';\r
+ fast_clear_o <= '0';\r
+ event_buffer_clear_o <= '0';\r
trigger_busy_o <= '0';\r
+ trigger_testpulse_o <= '0';\r
STATE <= S_IDLE;\r
else\r
validate_trigger_o <= '0';\r
lvl2_trigger_o <= '0';\r
fee_trg_release_o <= '0';\r
fee_trg_statusbits_o <= (others => '0');\r
- evt_buffer_clear_o <= '0';\r
+ fast_clear_o <= '0';\r
+ event_buffer_clear_o <= '0';\r
trigger_busy_o <= '1';\r
- \r
- case STATE is\r
- when S_IDLE =>\r
+ trigger_testpulse_o <= '0';\r
+\r
+ if (LVL1_INVALID_TRG_IN = '1') then\r
+ fast_clear_o <= '1';\r
+ fee_trg_release_o <= '1';\r
+ STATE <= S_IDLE;\r
+ else\r
+ case STATE is\r
+ when S_IDLE =>\r
+ if (LVL1_VALID_NOTIMING_TRG_IN = '1') then\r
+ STATE <= S_WAIT_TRG_DATA_VALID;\r
+ \r
+ elsif (LVL1_VALID_TIMING_TRG_IN = '1') then\r
+ if (NXYTER_OFFLINE_IN = '1') then\r
+ STATE <= S_WAIT_TRG_DATA_VALID;\r
+ else\r
+ STATE <= S_CTS_TRIGGER;\r
+ end if;\r
+ elsif (INTERNAL_TRIGGER_IN = '1') then\r
+ STATE <= S_INTERNAL_TRIGGER;\r
+ else\r
+ trigger_busy_o <= '0';\r
+ STATE <= S_IDLE;\r
+ end if; \r
+\r
+ -- CTS Trigger Handler\r
+ when S_CTS_TRIGGER =>\r
+ event_buffer_clear_o <= '1';\r
+ validate_trigger_o <= '1';\r
+ timestamp_hold <= '1';\r
+ lvl2_trigger_o <= '1';\r
+ if (reg_testpulse_enable = '1') then\r
+ trigger_testpulse_o <= '1';\r
+ end if;\r
+ STATE <= S_WAIT_TRG_DATA_VALID;\r
+\r
+ when S_WAIT_TRG_DATA_VALID =>\r
+ if (LVL1_TRG_DATA_VALID_IN = '0') then\r
+ STATE <= S_WAIT_TRG_DATA_VALID;\r
+ else\r
+ STATE <= S_WAIT_LVL2_TRIGGER_DONE;\r
+ end if;\r
\r
- if (LVL1_VALID_NOTIMING_TRG_IN = '1') then\r
- STATE <= S_WAIT_TRG_DATA_VALID;\r
+ when S_WAIT_LVL2_TRIGGER_DONE =>\r
+ if (LVL2_TRIGGER_BUSY_IN = '1') then\r
+ STATE <= S_WAIT_LVL2_TRIGGER_DONE;\r
+ else\r
+ STATE <= S_FEE_TRIGGER_RELEASE;\r
+ end if;\r
\r
- elsif (LVL1_INVALID_TRG_IN = '1') then\r
+ when S_FEE_TRIGGER_RELEASE =>\r
fee_trg_release_o <= '1';\r
- STATE <= S_IDLE;\r
+ STATE <= S_WAIT_FEE_TRIGGER_RELEASE_ACK;\r
\r
- elsif (LVL1_VALID_TIMING_TRG_IN = '1') then\r
- if (NXYTER_OFFLINE_IN = '1') then\r
- STATE <= S_WAIT_TRG_DATA_VALID;\r
+ when S_WAIT_FEE_TRIGGER_RELEASE_ACK =>\r
+ if (LVL1_TRG_DATA_VALID_IN = '1') then\r
+ STATE <= S_WAIT_FEE_TRIGGER_RELEASE_ACK;\r
else\r
- STATE <= S_CTS_TRIGGER;\r
+ STATE <= S_IDLE;\r
end if;\r
- elsif (INTERNAL_TRIGGER_IN = '1') then\r
- STATE <= S_INTERNAL_TRIGGER;\r
- else\r
- trigger_busy_o <= '0';\r
- STATE <= S_IDLE;\r
- end if; \r
-\r
- -- CTS Trigger Handler\r
- when S_CTS_TRIGGER =>\r
- evt_buffer_clear_o <= '1';\r
- validate_trigger_o <= '1';\r
- timestamp_hold <= '1';\r
- lvl2_trigger_o <= '1';\r
- STATE <= S_WAIT_TRG_DATA_VALID;\r
-\r
- when S_WAIT_TRG_DATA_VALID =>\r
- if (LVL1_TRG_DATA_VALID_IN = '0') then\r
- STATE <= S_WAIT_TRG_DATA_VALID;\r
- else\r
- STATE <= S_WAIT_LVL2_TRIGGER_DONE;\r
- end if;\r
-\r
- when S_WAIT_LVL2_TRIGGER_DONE =>\r
- if (LVL2_TRIGGER_BUSY_IN = '1') then\r
- STATE <= S_WAIT_LVL2_TRIGGER_DONE;\r
- else\r
- STATE <= S_FEE_TRIGGER_RELEASE;\r
- end if;\r
-\r
- when S_FEE_TRIGGER_RELEASE =>\r
- fee_trg_release_o <= '1';\r
- STATE <= S_WAIT_FEE_TRIGGER_RELEASE_ACK;\r
\r
- when S_WAIT_FEE_TRIGGER_RELEASE_ACK =>\r
- if (LVL1_TRG_DATA_VALID_IN = '1') then\r
- STATE <= S_WAIT_FEE_TRIGGER_RELEASE_ACK;\r
- else\r
- STATE <= S_IDLE;\r
- end if;\r
- \r
- -- Internal Trigger Handler\r
- when S_INTERNAL_TRIGGER =>\r
- validate_trigger_o <= '1';\r
- timestamp_hold <= '1';\r
- evt_buffer_clear_o <= '1';\r
- STATE <= S_WAIT_TRIGGER_VALIDATE_ACK;\r
-\r
- when S_WAIT_TRIGGER_VALIDATE_ACK =>\r
- if (TRIGGER_VALIDATE_BUSY_IN = '0') then\r
- STATE <= S_WAIT_TRIGGER_VALIDATE_ACK;\r
- else\r
- STATE <= S_WAIT_TRIGGER_VALIDATE_DONE;\r
- end if;\r
- \r
- when S_WAIT_TRIGGER_VALIDATE_DONE =>\r
- if (TRIGGER_VALIDATE_BUSY_IN = '1') then\r
- STATE <= S_WAIT_TRIGGER_VALIDATE_DONE;\r
- else\r
- STATE <= S_IDLE;\r
- end if;\r
- \r
- end case;\r
+ -- Internal Trigger Handler\r
+ when S_INTERNAL_TRIGGER =>\r
+ validate_trigger_o <= '1';\r
+ timestamp_hold <= '1';\r
+ event_buffer_clear_o <= '1';\r
+ STATE <= S_WAIT_TRIGGER_VALIDATE_ACK;\r
+\r
+ when S_WAIT_TRIGGER_VALIDATE_ACK =>\r
+ if (TRIGGER_VALIDATE_BUSY_IN = '0') then\r
+ STATE <= S_WAIT_TRIGGER_VALIDATE_ACK;\r
+ else\r
+ STATE <= S_WAIT_TRIGGER_VALIDATE_DONE;\r
+ end if;\r
+ \r
+ when S_WAIT_TRIGGER_VALIDATE_DONE =>\r
+ if (TRIGGER_VALIDATE_BUSY_IN = '1') then\r
+ STATE <= S_WAIT_TRIGGER_VALIDATE_DONE;\r
+ else\r
+ STATE <= S_IDLE;\r
+ end if;\r
+ \r
+ end case;\r
+ end if;\r
end if;\r
end if;\r
end process PROC_TRIGGER_HANDLER;\r
begin\r
if( rising_edge(CLK_IN) ) then\r
if (RESET_IN = '1' or NXYTER_OFFLINE_IN = '1') then\r
- wait_timer_init <= (others => '0');\r
- timestamp_hold_o <= '0';\r
- TS_STATE <= TS_IDLE;\r
+ wait_timer_init <= (others => '0');\r
+ timestamp_hold_o <= '0';\r
+ TS_STATE <= TS_IDLE;\r
else\r
- wait_timer_init <= (others => '0');\r
- timestamp_hold_o <= '0';\r
+ wait_timer_init <= (others => '0');\r
+ timestamp_hold_o <= '0';\r
\r
case TS_STATE is\r
\r
slv_unknown_addr_o <= '0';\r
slv_ack_o <= '0';\r
reg_timestamp_hold_delay <= x"01";\r
+ reg_testpulse_enable <= '0';\r
else\r
slv_unknown_addr_o <= '0';\r
slv_no_more_data_o <= '0';\r
reg_timestamp_hold_delay <= unsigned(SLV_DATA_IN(7 downto 0));\r
end if;\r
slv_ack_o <= '1';\r
+\r
+ when x"0001" =>\r
+ reg_testpulse_enable <= SLV_DATA_IN(0);\r
+ slv_ack_o <= '1';\r
\r
when others =>\r
slv_unknown_addr_o <= '1';\r
slv_data_out_o(31 downto 8) <= (others => '0');\r
slv_ack_o <= '1';\r
\r
+ when x"0001" =>\r
+ slv_data_out_o(0) <= reg_testpulse_enable;\r
+ slv_data_out_o(31 downto 1) <= (others => '0');\r
+ slv_ack_o <= '1';\r
+\r
when others =>\r
slv_unknown_addr_o <= '1';\r
\r
VALIDATE_TRIGGER_OUT <= validate_trigger_o;\r
TIMESTAMP_HOLD_OUT <= timestamp_hold_o;\r
LVL2_TRIGGER_OUT <= lvl2_trigger_o;\r
- EVENT_BUFFER_CLEAR_OUT <= evt_buffer_clear_o;\r
+ EVENT_BUFFER_CLEAR_OUT <= event_buffer_clear_o;\r
FAST_CLEAR_OUT <= fast_clear_o;\r
TRIGGER_BUSY_OUT <= trigger_busy_o;\r
FEE_TRG_RELEASE_OUT <= fee_trg_release_o;\r
FEE_TRG_STATUSBITS_OUT <= fee_trg_statusbits_o;\r
\r
+ TRIGGER_TESTPULSE_OUT <= trigger_testpulse_o;\r
+\r
-- Slave Bus \r
SLV_DATA_OUT <= slv_data_out_o; \r
SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o; \r
signal t_data_o : std_logic_vector(31 downto 0);
signal t_data_clk_o : std_logic;
signal busy_time_ctr : unsigned(11 downto 0);
-
- -- Timer
- signal wait_timer_done : std_logic;
+ signal busy_time_min_done : std_logic;
+ signal wait_timer_reset : std_logic;
+ -- Timer
+ signal timer_reset : std_logic;
+ signal wait_timer_done : std_logic;
+
-- Histogram
signal histogram_fill_o : std_logic;
signal histogram_bin_o : std_logic_vector(6 downto 0);
-- Debug Line
DEBUG_OUT(0) <= CLK_IN;
--- DEBUG_OUT(2) <= trigger_busy_o;
--- DEBUG_OUT(3) <= channel_all_done;
--- DEBUG_OUT(4) <= data_clk_o;
--- DEBUG_OUT(5) <= t_data_clk_o;
--- DEBUG_OUT(6) <= out_of_window_l;
- --DEBUG_OUT(7) <= out_of_window_h;
- --DEBUG_OUT(8) <= NX_TOKEN_RETURN_IN;
- --DEBUG_OUT(9) <= NX_NOMORE_DATA_IN;
- --DEBUG_OUT(10) <= store_to_fifo;
- DEBUG_OUT(15 downto 1) <= SLV_ADDR_IN(15 downto 1);
+ DEBUG_OUT(2) <= trigger_busy_o;
+ DEBUG_OUT(3) <= channel_all_done;
+ DEBUG_OUT(4) <= data_clk_o;
+ DEBUG_OUT(5) <= t_data_clk_o;
+ DEBUG_OUT(6) <= out_of_window_l;
+ DEBUG_OUT(7) <= out_of_window_h;
+ DEBUG_OUT(8) <= NX_TOKEN_RETURN_IN;
+ DEBUG_OUT(9) <= NX_NOMORE_DATA_IN;
+ DEBUG_OUT(10) <= store_to_fifo;
+ DEBUG_OUT(11) <= wait_timer_done;
+ DEBUG_OUT(12) <= timer_reset;
+ DEBUG_OUT(13) <= busy_time_min_done;
+ DEBUG_OUT(15 downto 14) <= (others => '0');
-- Timer
nx_timer_1: nx_timer
)
port map (
CLK_IN => CLK_IN,
- RESET_IN => RESET_IN,
+ RESET_IN => timer_reset,
TIMER_START_IN => wait_timer_init,
TIMER_DONE_OUT => wait_timer_done
);
+ timer_reset <= RESET_IN or wait_timer_reset;
+
-- Sync Timestamp Ref
PROC_SYNC_TIMESTAMP_REF: process (CLK_IN)
begin
variable window_lower_thr : unsigned(11 downto 0);
variable window_upper_thr : unsigned(11 downto 0);
variable deltaT : unsigned(11 downto 0);
-
+ variable deltaTStore : unsigned(11 downto 0);
+
begin
if( rising_edge(CLK_IN) ) then
if (RESET_IN = '1') then
window_lower_thr := trigger_window_delay;
window_upper_thr := window_lower_thr + trigger_window_width;
deltaT := unsigned(TIMESTAMP_IN(13 downto 2)) - ts_ref;
-
+ deltaTStore := deltaT - window_lower_thr;
+
window_lower_thr_r <= window_lower_thr;
window_upper_thr_r <= window_upper_thr;
-
+
case readout_mode is
when x"0" => -- RefValue + valid and window filter
-- IN LUT-Data bit setzten.
channel_index <= CHANNEL_IN;
ch_status_cmd_pr <= CS_SET_WAIT;
-
- data_o(11 downto 0) <= deltaT;
- data_o(23 downto 12) <= ADC_DATA_IN;
- data_o(30 downto 24) <= CHANNEL_IN;
- data_o(31) <= '0';
- data_clk_o <= '1';
+
+ data_o( 6 downto 0) <= CHANNEL_IN;
+ data_o(7) <= TIMESTAMP_STATUS_IN(1);
+ data_o( 9 downto 8) <= TIMESTAMP_IN(1 downto 0);
+ data_o(18 downto 10) <= deltaTStore(8 downto 0);
+ data_o(30 downto 19) <= ADC_DATA_IN;
+ data_o(31) <= TIMESTAMP_STATUS_IN(2);
+ data_clk_o <= '1';
end if;
end if;
when x"1" => -- RefValue + valid filter
if (TIMESTAMP_STATUS_IN(1) = '0') then
- data_o(11 downto 0) <= deltaT;
- data_o(23 downto 12) <= ADC_DATA_IN;
- data_o(30 downto 24) <= CHANNEL_IN;
- data_o(31) <= '0';
+ data_o( 6 downto 0) <= CHANNEL_IN;
+ data_o(7) <= TIMESTAMP_STATUS_IN(1);
+ data_o( 9 downto 8) <= TIMESTAMP_IN(1 downto 0);
+ data_o(18 downto 10) <= deltaTStore(8 downto 0);
+ data_o(30 downto 19) <= ADC_DATA_IN;
+ data_o(31) <= TIMESTAMP_STATUS_IN(2);
data_clk_o <= '1';
end if;
when x"3" => -- RefValue + valid filter
if (TIMESTAMP_STATUS_IN(1) = '0') then
- data_o(11 downto 0) <= TIMESTAMP_IN(13 downto 2);
- data_o(23 downto 12) <= ADC_DATA_IN;
- data_o(30 downto 24) <= CHANNEL_IN;
- data_o(31) <= '0';
+ data_o( 6 downto 0) <= CHANNEL_IN;
+ data_o(7) <= TIMESTAMP_STATUS_IN(1);
+ data_o( 9 downto 8) <= TIMESTAMP_IN(1 downto 0);
+ data_o(18 downto 10) <= deltaTStore(8 downto 0);
+ data_o(30 downto 19) <= ADC_DATA_IN;
+ data_o(31) <= TIMESTAMP_STATUS_IN(2);
data_clk_o <= '1';
end if;
when x"4" => -- RawValue
- data_o(11 downto 0) <= TIMESTAMP_IN(13 downto 2);
- data_o(23 downto 12) <= ADC_DATA_IN;
- data_o(30 downto 24) <= CHANNEL_IN;
- data_o(31) <= '0';
+ data_o( 6 downto 0) <= CHANNEL_IN;
+ data_o(7) <= TIMESTAMP_STATUS_IN(1);
+ data_o( 9 downto 8) <= TIMESTAMP_IN(1 downto 0);
+ data_o(18 downto 10) <= deltaTStore(8 downto 0);
+ data_o(30 downto 19) <= ADC_DATA_IN;
+ data_o(31) <= TIMESTAMP_STATUS_IN(2);
data_clk_o <= '1';
when x"5" => -- RawValue + valid filter
if (TIMESTAMP_STATUS_IN(1) = '0') then
- data_o(11 downto 0) <= TIMESTAMP_IN(13 downto 2);
- data_o(23 downto 12) <= ADC_DATA_IN;
- data_o(30 downto 24) <= CHANNEL_IN;
- data_o(31) <= '0';
+ data_o( 6 downto 0) <= CHANNEL_IN;
+ data_o(7) <= TIMESTAMP_STATUS_IN(1);
+ data_o( 9 downto 8) <= TIMESTAMP_IN(1 downto 0);
+ data_o(18 downto 10) <= deltaTStore(8 downto 0);
+ data_o(30 downto 19) <= ADC_DATA_IN;
+ data_o(31) <= TIMESTAMP_STATUS_IN(2);
data_clk_o <= '1';
end if;
-----------------------------------------------------------------------------
PROC_TRIGGER_HANDLER: process(CLK_IN)
- variable min_validation_time : unsigned(23 downto 0);
+ variable min_validation_time : unsigned(11 downto 0);
begin
if( rising_edge(CLK_IN) ) then
- if (RESET_IN = '1') then
+ if (RESET_IN = '1' or FAST_CLEAR_IN = '1') then
store_to_fifo <= '0';
trigger_busy_o <= '0';
nomore_data_o <= '0';
wait_timer_init <= (others => '0');
+ wait_timer_reset <= '0';
t_data_o <= (others => '0');
t_data_clk_o <= '0';
busy_time_ctr <= (others => '0');
+ busy_time_min_done <= '0';
token_return_ctr <= '0';
ch_status_cmd_tr <= CS_RESET;
STATE <= S_IDLE;
else
store_to_fifo <= '0';
wait_timer_init <= (others => '0');
+ wait_timer_reset <= '0';
trigger_busy_o <= '1';
nomore_data_o <= '0';
t_data_o <= (others => '0');
ch_status_cmd_tr <= CS_NONE;
min_validation_time := x"020" +
- (trigger_window_delay * 2 +
- trigger_window_delay / 2) +
- (trigger_window_width * 2 +
- trigger_window_width / 2);
-
+ (trigger_window_delay / 2) +
+ (trigger_window_width / 2);
+
+
case STATE is
when S_IDLE =>
busy_time_ctr > min_validation_time(11 downto 0))
)
then
+ wait_timer_reset <= '1';
STATE <= S_WRITE_TRAILER;
else
store_to_fifo <= '1';
STATE <= S_WAIT_PROCESS_END;
-- Check Token_Return
- if (busy_time_ctr > min_validation_time(11 downto 0)) then
+ if (busy_time_ctr > min_validation_time) then
if (readout_mode = x"0" and NX_TOKEN_RETURN_IN = '1') then
if (token_return_ctr = '1') then
ch_status_cmd_tr <= CS_TOKEN_UPDATE;
busy_time_ctr <= busy_time_ctr + 1;
end if;
+ if (busy_time_ctr > min_validation_time) then
+ busy_time_min_done <= '1';
+ else
+ busy_time_min_done <= '0';
+ end if;
end if;
end if;
end process PROC_TRIGGER_HANDLER;
SDA_OUT : out std_logic;
SCL_OUT : out std_logic;
SDA_IN : in std_logic;
+ SCL_IN : in std_logic;
ACK_OUT : out std_logic
);
end component;
component nx_histograms
generic (
- NUM_BINS : integer);
+ BUS_WIDTH : integer;
+ ENABLE : integer
+ );
port (
CLK_IN : in std_logic;
RESET_IN : in std_logic;
RESET_HISTS_IN : in std_logic;
CHANNEL_STAT_FILL_IN : in std_logic;
- CHANNEL_ID_IN : in std_logic_vector(NUM_BINS - 1 downto 0);
+ CHANNEL_ID_IN : in std_logic_vector(BUS_WIDTH - 1 downto 0);
SLV_READ_IN : in std_logic;
SLV_WRITE_IN : in std_logic;
SLV_DATA_OUT : out std_logic_vector(31 downto 0);
EVENT_BUFFER_CLEAR_OUT : out std_logic;
FAST_CLEAR_OUT : out std_logic;
TRIGGER_BUSY_OUT : out std_logic;
+ TRIGGER_TESTPULSE_OUT : out std_logic;
SLV_READ_IN : in std_logic;
SLV_WRITE_IN : in std_logic;
SLV_DATA_OUT : out std_logic_vector(31 downto 0);
port (
CLK_IN : in std_logic;
RESET_IN : in std_logic;
+ TRIGGER_IN : out std_logic;
TRIGGER_OUT : out std_logic;
TS_RESET_OUT : out std_logic;
TESTPULSE_OUT : out std_logic;
);
end component;
+type debug_array_t is array(integer range <>) of std_logic_vector(15 downto 0);
+
+component debug_multiplexer
+ generic (
+ NUM_PORTS : integer range 1 to 32);
+ port (
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+ DEBUG_LINE_IN : in debug_array_t(0 to NUM_PORTS-1);
+ DEBUG_LINE_OUT : out std_logic_vector(15 downto 0);
+ SLV_READ_IN : in std_logic;
+ SLV_WRITE_IN : in std_logic;
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);
+ SLV_ADDR_IN : in std_logic_vector(15 downto 0);
+ SLV_ACK_OUT : out std_logic;
+ SLV_NO_MORE_DATA_OUT : out std_logic;
+ SLV_UNKNOWN_ADDR_OUT : out std_logic
+ );
+end component;
+
end package;
signal clk_250_o : std_logic;
-- Bus Handler
- constant NUM_PORTS : integer := 11;
+ constant NUM_PORTS : integer := 12;
signal slv_read : std_logic_vector(NUM_PORTS-1 downto 0);
signal slv_write : std_logic_vector(NUM_PORTS-1 downto 0);
signal fast_clear : std_logic;
signal nxyter_offline : std_logic;
signal fee_trg_release_o : std_logic;
+ signal trigger_testpulse : std_logic;
-- FPGA Timestamp
signal timestamp_trigger : unsigned(11 downto 0);
signal trigger_intern : std_logic;
signal nx_testpulse_o : std_logic;
+ -- Debug Handler
+ constant DEBUG_NUM_PORTS : integer := 12;
+ signal debug_line : debug_array_t(0 to DEBUG_NUM_PORTS-1);
+
begin
-------------------------------------------------------------------------------
generic map(
PORT_NUMBER => NUM_PORTS,
- PORT_ADDRESSES => ( 0 => x"0100", -- Control Register Handler
- 1 => x"0040", -- I2C Master
- 2 => x"0500", -- Data Receiver
- 3 => x"0600", -- Data Buffer
- 4 => x"0060", -- SPI Master
- 5 => x"0140", -- Trigger Generator
- 6 => x"0120", -- Data Validate
- 7 => x"0160", -- Trigger Handler
- 8 => x"0180", -- Trigger Validate
- 9 => x"0200", -- NX Register Setup
- 10 => x"0800", -- NX Histograms
- others => x"0000"),
-
- PORT_ADDR_MASK => ( 0 => 3, -- Control Register Handler
- 1 => 0, -- I2C master
- 2 => 3, -- Data Receiver
- 3 => 3, -- Data Buffer
- 4 => 0, -- SPI Master
- 5 => 3, -- Trigger Generator
- 6 => 4, -- Data Validate
- 7 => 1, -- Trigger Handler
- 8 => 4, -- Trigger Validate
- 9 => 8, -- NX Register Setup
- 10 => 8, -- NX Histograms
- others => 0),
+ PORT_ADDRESSES => ( 0 => x"0100", -- Control Register Handler
+ 1 => x"0040", -- I2C Master
+ 2 => x"0500", -- Data Receiver
+ 3 => x"0600", -- Data Buffer
+ 4 => x"0060", -- SPI Master
+ 5 => x"0140", -- Trigger Generator
+ 6 => x"0120", -- Data Validate
+ 7 => x"0160", -- Trigger Handler
+ 8 => x"0180", -- Trigger Validate
+ 9 => x"0200", -- NX Register Setup
+ 10 => x"0800", -- NX Histograms
+ 11 => x"0020", -- Debug Handler
+ others => x"0000"
+ ),
+
+ PORT_ADDR_MASK => ( 0 => 3, -- Control Register Handler
+ 1 => 0, -- I2C master
+ 2 => 3, -- Data Receiver
+ 3 => 3, -- Data Buffer
+ 4 => 0, -- SPI Master
+ 5 => 3, -- Trigger Generator
+ 6 => 4, -- Data Validate
+ 7 => 1, -- Trigger Handler
+ 8 => 4, -- Trigger Validate
+ 9 => 8, -- NX Register Setup
+ 10 => 8, -- NX Histograms
+ 11 => 0, -- Debug Handler
+ others => 0
+ ),
PORT_MASK_ENABLE => 1
)
DAT_NO_MORE_DATA_OUT => REGIO_NO_MORE_DATA_OUT,
DAT_UNKNOWN_ADDR_OUT => REGIO_UNKNOWN_ADDR_OUT,
- -- Control Registers
+ -- All NXYTER Ports
BUS_READ_ENABLE_OUT => slv_read,
BUS_WRITE_ENABLE_OUT => slv_write,
BUS_DATA_OUT => slv_data_wr,
NX_TS_RESET_OUT => nx_ts_reset_1,
OFFLINE_OUT => nxyter_offline,
--DEBUG_OUT => DEBUG_LINE_OUT
- DEBUG_OUT => open
+ DEBUG_OUT => debug_line(0)
);
nx_register_setup_1: nx_setup
SLV_NO_MORE_DATA_OUT => slv_no_more_data(9),
SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(9),
--DEBUG_OUT => DEBUG_LINE_OUT
- DEBUG_OUT => open
+ DEBUG_OUT => debug_line(1)
);
-------------------------------------------------------------------------------
SLV_NO_MORE_DATA_OUT => slv_no_more_data(1),
SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(1),
--DEBUG_OUT => DEBUG_LINE_OUT
- DEBUG_OUT => open
+ DEBUG_OUT => debug_line(2)
);
-------------------------------------------------------------------------------
SLV_NO_MORE_DATA_OUT => slv_no_more_data(4),
SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(4),
-- DEBUG_OUT => DEBUG_LINE_OUT
- DEBUG_OUT => open
+ DEBUG_OUT => debug_line(3)
);
-------------------------------------------------------------------------------
SLV_NO_MORE_DATA_OUT => open,
SLV_UNKNOWN_ADDR_OUT => open,
-- DEBUG_OUT => DEBUG_LINE_OUT
- DEBUG_OUT => open
+ DEBUG_OUT => debug_line(4)
);
-------------------------------------------------------------------------------
FAST_CLEAR_OUT => fast_clear,
TRIGGER_BUSY_OUT => trigger_busy,
+ TRIGGER_TESTPULSE_OUT => trigger_testpulse,
+
SLV_READ_IN => slv_read(7),
SLV_WRITE_IN => slv_write(7),
SLV_DATA_OUT => slv_data_rd(7*32+31 downto 7*32),
SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(7),
--DEBUG_OUT => DEBUG_LINE_OUT
- DEBUG_OUT => open
+ DEBUG_OUT => debug_line(5)
);
-------------------------------------------------------------------------------
port map (
CLK_IN => CLK_IN,
RESET_IN => RESET_IN,
+ TRIGGER_IN => trigger_testpulse,
TRIGGER_OUT => trigger_intern,
TS_RESET_OUT => nx_ts_reset_2,
TESTPULSE_OUT => nx_testpulse_o,
SLV_NO_MORE_DATA_OUT => slv_no_more_data(5),
SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(5),
--DEBUG_OUT => DEBUG_LINE_OUT
- DEBUG_OUT => open
+ DEBUG_OUT => debug_line(6)
);
-------------------------------------------------------------------------------
SLV_NO_MORE_DATA_OUT => slv_no_more_data(2),
SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(2),
--DEBUG_OUT => DEBUG_LINE_OUT
- DEBUG_OUT => open
+ DEBUG_OUT => debug_line(7)
);
-------------------------------------------------------------------------------
SLV_NO_MORE_DATA_OUT => slv_no_more_data(6),
SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(6),
--DEBUG_OUT => DEBUG_LINE_OUT
- DEBUG_OUT => open
+ DEBUG_OUT => debug_line(8)
);
-------------------------------------------------------------------------------
SLV_ACK_OUT => slv_ack(8),
SLV_NO_MORE_DATA_OUT => slv_no_more_data(8),
SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(8),
- DEBUG_OUT => DEBUG_LINE_OUT
- --DEBUG_OUT => open
+ --DEBUG_OUT => DEBUG_LINE_OUT
+ DEBUG_OUT => debug_line(9)
);
-------------------------------------------------------------------------------
SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(3),
--DEBUG_OUT => DEBUG_LINE_OUT
- DEBUG_OUT => open
+ DEBUG_OUT => debug_line(10)
);
nx_histograms_1: nx_histograms
generic map (
- NUM_BINS => 7
+ BUS_WIDTH => 7,
+ ENABLE => 0
)
port map (
CLK_IN => CLK_IN,
SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(10),
--DEBUG_OUT => DEBUG_LINE_OUT
- DEBUG_OUT => open
+ DEBUG_OUT => debug_line(11)
);
-------------------------------------------------------------------------------
I2C_SM_RESET_OUT <= not i2c_sm_reset_o;
I2C_REG_RESET_OUT <= not i2c_reg_reset_o;
+
+
+-------------------------------------------------------------------------------
+-- DEBUG Line Select
+-------------------------------------------------------------------------------
+ debug_multiplexer_1: debug_multiplexer
+ generic map (
+ NUM_PORTS => DEBUG_NUM_PORTS
+ )
+ port map (
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+ DEBUG_LINE_IN => debug_line,
+ DEBUG_LINE_OUT => DEBUG_LINE_OUT,
+ SLV_READ_IN => slv_read(11),
+ SLV_WRITE_IN => slv_write(11),
+ SLV_DATA_OUT => slv_data_rd(11*32+31 downto 11*32),
+ SLV_DATA_IN => slv_data_wr(11*32+31 downto 11*32),
+ SLV_ADDR_IN => slv_addr(11*16+15 downto 11*16),
+ SLV_ACK_OUT => slv_ack(11),
+ SLV_NO_MORE_DATA_OUT => slv_no_more_data(11),
+ SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(11)
+ );
-------------------------------------------------------------------------------
-- END
0x8103 : r/w Put nxyter into offline mode
-- NX Data Validate
-0x8120 : rw Invalid Frame Counter (16 bit) / w: clear all counters
+0x8120 : r/w Invalid Frame Counter (16 bit) / w: clear all counters
0x8121 : r Overflow Counter (16 bit)
0x8122 : r Pileup Counter (16 bit)
0x8123 : r Parity Error Counter (16 bit)
-- Trigger Handler
0x8160 : r/w Bit 15-0 : Delay Timestamp Hold signal (8bit, 10ns)
+0x8161 : r/w Bit 0 : Enable Testpulse Signal (default: off)
-- NX Data Receiver
0x8500 : r current Timestamp FIFO value
0x8600 : r read FIFO buffer
0x8601 : r FIFO write counter
0x8602 : r FIFO flush counter
-0x8603 : r/w r: read FIFO status
- w: enable/disable FIFO write
+0x8603 : r read FIFO status
-- I2C Master
-0x8040 : Access to I2C Interface
+0x8040 : Access to I2C Interface
+ Chip Ids: 0x08 : nXyter
+ 0x29 : AD7991-1
+ 0x50 : EEPROM
-- SPI Master
0x8060 : Access to SPI Interface
+
+-- NX I2C Setup Handler
+0x8200 : r/w I2C Memeory Register (Depth: 0 - 45 ... 0x822c)
+0x8260 : r/w DAC Register Memory (Depth: 0 - 129 ... 0x82e0)
+0x8240 : w Read all I2C Registers into Memory
+0x8241 : w Write all Memory to I2C Registers
+0x8242 : w Read Trim DAC Register(129 deep FIFO) to Memory
+0x8243 : w Write Memory to Trim DAC Register(129 deep FIFO)
+
+-- Debug Multiplexer
+0x8020 : r/w Select Debug Entity
+ 0: nxyter_registers
+ 1: nx_setup
+ 2: nx_i2c_master
+ 3: adc_spi_master
+ 4: nx_fpga_timestamp
+ 5: nx_trigger_handler
+ 6: nx_trigger_generator
+ 7: nx_data_receiver
+ 8: nx_data_validate
+ 9: nx_trigger_validate
+ 10: nx_event_buffer
+ 11: nx_histograms
+
add_file -vhdl -lib "work" "source/gray_decoder.vhd"
add_file -vhdl -lib "work" "source/gray_encoder.vhd"
add_file -vhdl -lib "work" "source/nx_timer.vhd"
+add_file -vhdl -lib "work" "source/debug_multiplexer.vhd"
add_file -vhdl -lib "work" "source/nxyter_fee_board.vhd"
add_file -vhdl -lib "work" "source/nx_data_receiver.vhd"
PROHIBIT PRIMARY NET "NX2_CLK128_IN_c";
PROHIBIT SECONDARY NET "NX2_CLK128_IN_c";
-PROHIBIT PRIMARY NET "TEST_LINE_c_0";
-PROHIBIT SECONDARY NET "TEST_LINE_c_0";
+PROHIBIT PRIMARY NET "TEST_LINE_c_0_1";
+PROHIBIT SECONDARY NET "TEST_LINE_c_0_1";
DEFINE PORT GROUP "NX1_IN" "NX1_TIMESTAMP_*";
INPUT_SETUP GROUP "NX1_IN" 3.0 ns HOLD 3.0 ns CLKPORT="NX1_CLK128_IN" ;
jspc29 / trb3.git / commitdiff