CTS: change to new ping module, add CTS monitor outputs

diff --git a/cts/trb3sc_cts.prj b/cts/trb3sc_cts.prj
index c440017f7efaa8480945a91dc0f2f47944f99f17..a110b6d1be6b0686f2099ffc90456c0bdb9134d1 100644 (file)
--- a/cts/trb3sc_cts.prj
+++ b/cts/trb3sc_cts.prj
@@ -206,7 +206,8 @@ add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_receive_contro
 add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_main_control.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_mac_control.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_protocol_prioritizer.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_protocol_selector.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_protocol_selector.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_protocol_selector.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_type_validator.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_trans.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_constr.vhd"
@@ -216,7 +217,8 @@ add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_event_constr.v
 add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_setup.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/base/ip_configurator.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_ARP.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Ping.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Ping.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/gbe_response_constructor_Ping.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_DHCP.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_SCTRL.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_TrbNetData.vhd"
@@ -229,6 +231,7 @@ add_file -verilog -lib work "../../trbnet/gbe_trb/media/reset_controller_cdr.v"
 add_file -verilog -lib work "../../trbnet/gbe_trb/media/register_interface_hb.v"
 add_file -verilog -lib work "../../trbnet/gbe_trb/media/rate_resolution.v"
 
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/ram_dp_true_2kx9.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_8kx9.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_4096x9.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_512x32.vhd"

diff --git a/cts/trb3sc_cts.vhd b/cts/trb3sc_cts.vhd
index 3b4a9393ac087ca41e6fb34f856c9b1755e91f41..dbf209a6fd03f4b5436c6eb2cd77b2c62d2b8803 100644 (file)
--- a/cts/trb3sc_cts.vhd
+++ b/cts/trb3sc_cts.vhd
@@ -164,6 +164,7 @@ architecture trb3sc_arch of trb3sc_cts is
   signal trigger_gen_outputs_i: std_logic_vector(TRIG_GEN_OUTPUT_NUM-1 downto 0);
   signal trigger_busy_i              : std_logic;
   signal cts_trigger_out             : std_logic;
+  signal cts_monitor_out             : std_logic_vector(1 downto 0);
   
   signal gbe_cts_number                   : std_logic_vector(15 downto 0);
   signal gbe_cts_code                     : std_logic_vector(7 downto 0);
@@ -889,7 +890,7 @@ end generate;
 
         PERIPH_TRIGGER_IN => (others => '0'),
 
-        OUTPUT_MULTIPLEXERS_OUT => open,
+        OUTPUT_MULTIPLEXERS_OUT => cts_monitor_out,
 
         CTS_TRG_SEND_OUT        => cts_trg_send,
         CTS_TRG_TYPE_OUT        => cts_trg_type,
@@ -1203,8 +1204,13 @@ end generate;
   
 gen_busy : if GEN_BUSY_OUTPUT = c_YES generate
   RJ_IO(3)  <= trigger_busy_i;
+else generate
+  RJ_IO(3)  <= cts_monitor_out(1);
 end generate;
 
+gen_muxout_0 : if ETM_CHOICE /= ETM_CHOICE_R3B or INCLUDE_ETM = c_NO generate
+  RJ_IO(2) <= cts_monitor_out(0);
+end generate;
 
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