--- VHDL netlist generated by SCUBA Diamond (64-bit) 3.11.2.446
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.12.1.454
-- Module Version: 5.7
---/d/jspc29/lattice/diamond/3.11_x64/ispfpga/bin/lin64/scuba -w -n pll_200_160 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 200 -fclkop 160 -fclkop_tol 0.0 -fclkos 320 -fclkos_tol 0.0 -phases 0 -phase_cntl STATIC -fb_mode 1 -fdc /local/trb/git/trb5sc/mimosis/cores/pll_200_160/pll_200_160.fdc
+--/d/jspc29/lattice/diamond/3.12/ispfpga/bin/lin64/scuba -w -n pll_200_160 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 200 -fclkop 160 -fclkop_tol 0.0 -fclkos 320 -fclkos_tol 0.0 -phases 0 -fclkos2 40.00 -fclkos2_tol 0.0 -phases2 0 -phase_cntl STATIC -fb_mode 1
--- Fri Jul 2 12:08:04 2021
+-- Fri Nov 12 15:18:43 2021
library IEEE;
use IEEE.std_logic_1164.all;
port (
CLKI: in std_logic;
CLKOP: out std_logic;
- CLKOS: out std_logic);
+ CLKOS: out std_logic;
+ CLKOS2: out std_logic);
end pll_200_160;
architecture Structure of pll_200_160 is
-- internal signal declarations
signal REFCLK: std_logic;
signal LOCK: std_logic;
+ signal CLKOS2_t: std_logic;
signal CLKOS_t: std_logic;
signal CLKOP_t: std_logic;
signal scuba_vhi: std_logic;
signal scuba_vlo: std_logic;
+ attribute FREQUENCY_PIN_CLKOS2 : string;
attribute FREQUENCY_PIN_CLKOS : string;
attribute FREQUENCY_PIN_CLKOP : string;
attribute FREQUENCY_PIN_CLKI : string;
attribute ICP_CURRENT : string;
attribute LPF_RESISTOR : string;
+ attribute FREQUENCY_PIN_CLKOS2 of PLLInst_0 : label is "40.000000";
attribute FREQUENCY_PIN_CLKOS of PLLInst_0 : label is "320.000000";
attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "160.000000";
attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "200.000000";
generic map (PLLRST_ENA=> "DISABLED", INTFB_WAKE=> "DISABLED",
STDBY_ENABLE=> "DISABLED", DPHASE_SOURCE=> "DISABLED",
CLKOS3_FPHASE=> 0, CLKOS3_CPHASE=> 0, CLKOS2_FPHASE=> 0,
- CLKOS2_CPHASE=> 0, CLKOS_FPHASE=> 0, CLKOS_CPHASE=> 1,
+ CLKOS2_CPHASE=> 15, CLKOS_FPHASE=> 0, CLKOS_CPHASE=> 1,
CLKOP_FPHASE=> 0, CLKOP_CPHASE=> 3, PLL_LOCK_MODE=> 0,
CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "FALLING",
CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "FALLING",
OUTDIVIDER_MUXD=> "DIVD", CLKOS3_ENABLE=> "DISABLED",
- OUTDIVIDER_MUXC=> "DIVC", CLKOS2_ENABLE=> "DISABLED",
+ OUTDIVIDER_MUXC=> "DIVC", CLKOS2_ENABLE=> "ENABLED",
OUTDIVIDER_MUXB=> "DIVB", CLKOS_ENABLE=> "ENABLED",
OUTDIVIDER_MUXA=> "DIVA", CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=> 1,
- CLKOS2_DIV=> 1, CLKOS_DIV=> 2, CLKOP_DIV=> 4, CLKFB_DIV=> 4,
+ CLKOS2_DIV=> 16, CLKOS_DIV=> 2, CLKOP_DIV=> 4, CLKFB_DIV=> 4,
CLKI_DIV=> 5, FEEDBK_PATH=> "CLKOP")
port map (CLKI=>CLKI, CLKFB=>CLKOP_t, PHASESEL1=>scuba_vlo,
PHASESEL0=>scuba_vlo, PHASEDIR=>scuba_vlo,
STDBY=>scuba_vlo, PLLWAKESYNC=>scuba_vlo, RST=>scuba_vlo,
ENCLKOP=>scuba_vlo, ENCLKOS=>scuba_vlo, ENCLKOS2=>scuba_vlo,
ENCLKOS3=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>CLKOS_t,
- CLKOS2=>open, CLKOS3=>open, LOCK=>LOCK, INTLOCK=>open,
+ CLKOS2=>CLKOS2_t, CLKOS3=>open, LOCK=>LOCK, INTLOCK=>open,
REFCLK=>REFCLK, CLKINTFB=>open);
+ CLKOS2 <= CLKOS2_t;
CLKOS <= CLKOS_t;
CLKOP <= CLKOP_t;
end Structure;
H2 : inout std_logic_vector(4 downto 0);\r
H3 : inout std_logic_vector(4 downto 0);\r
H4 : inout std_logic_vector(4 downto 0);\r
- H5 : inout std_logic_vector(4 downto 0);\r
+ H5 : inout std_logic_vector(3 downto 0);\r
H6 : inout std_logic_vector(4 downto 0);\r
H7 : inout std_logic_vector(4 downto 0);\r
\r
PIN : inout std_logic_vector(8 downto 1);\r
\r
+ MIMOSIS_SCL, MIMOSIS_SDA : inout std_logic;\r
+ \r
--ADC\r
ADC_SCLK : out std_logic;\r
ADC_NCS : out std_logic;\r
attribute syn_keep : boolean;\r
attribute syn_preserve : boolean;\r
\r
- signal clk_sys, clk_full, clk_full_osc, clk_160, clk_320 : std_logic;\r
+ signal clk_sys, clk_full, clk_full_osc, clk_160, clk_320, clk_40 : std_logic;\r
signal GSR_N : std_logic;\r
signal reset_i : std_logic;\r
signal clear_i : std_logic;\r
signal readout_rx : READOUT_RX;\r
signal readout_tx : readout_tx_array_t(0 to 0);\r
\r
- signal ctrlbus_tx, bustdc_tx, bussci_tx, bustools_tx, bustc_tx, busthresh_tx, bus_master_in, busmimosis_tx : CTRLBUS_TX;\r
- signal ctrlbus_rx, bustdc_rx, bussci_rx, bustools_rx, bustc_rx, busthresh_rx, bus_master_out, busmimosis_rx : CTRLBUS_RX;\r
+ signal ctrlbus_tx, bustdc_tx, bussci_tx, bustools_tx, bustc_tx, busthresh_tx, bus_master_in, busmimosis_tx, busi2c_tx : CTRLBUS_TX;\r
+ signal ctrlbus_rx, bustdc_rx, bussci_rx, bustools_rx, bustc_rx, busthresh_rx, bus_master_out, busmimosis_rx, busi2c_rx : CTRLBUS_RX;\r
\r
signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');\r
signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0);\r
signal inp_i : std_logic_vector( 7 downto 0);\r
signal dummy : std_logic_vector( 1 downto 0);\r
\r
+ \r
+ signal i2c_reg_0, i2c_reg_1 : std_logic_vector(31 downto 0);\r
+ signal i2c_reg_2 : std_logic_vector(31 downto 0);\r
+ signal i2c_reg_4, i2c_reg_5 : std_logic_vector(31 downto 0);\r
+ signal mimosis_scl_drv, mimosis_sda_drv : std_logic;\r
+ signal i2c_go_100, i2c_go : std_logic;\r
+ signal i2c_reg_5_40 : std_logic_vector(31 downto 0);\r
+ \r
begin\r
\r
\r
port map(\r
CLKI => clk_full_osc,\r
CLKOP => clk_160,\r
- CLKOS => clk_320\r
+ CLKOS => clk_320,\r
+ CLKOS2=> clk_40\r
);\r
\r
H5(3) <= clk_320;\r
+RJ(0) <= clk_40;\r
\r
---------------------------------------------------------------------------\r
-- TrbNet Uplink\r
-- Bus Handler\r
---------------------------------------------------------------------------\r
\r
-\r
THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record\r
generic map(\r
- PORT_NUMBER => 4,\r
- PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"a000", 5 => x"c000", others => x"0000"),\r
- PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 12, 4 => 5, 5 => 12, others => 0),\r
+ PORT_NUMBER => 5,\r
+ PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"a000", 4 => x"de00", others => x"0000"),\r
+ PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 12, 4 => 5, others => 0),\r
PORT_MASK_ENABLE => 1\r
)\r
port map(\r
BUS_RX(1) => bussci_rx, --SCI Serdes\r
BUS_RX(2) => bustc_rx, --Clock switch\r
BUS_RX(3) => busmimosis_rx,\r
--- BUS_RX(4) => bustdc_rx,\r
+ BUS_RX(4) => busi2c_rx,\r
BUS_TX(0) => bustools_tx,\r
BUS_TX(1) => bussci_tx,\r
BUS_TX(2) => bustc_tx,\r
BUS_TX(3) => busmimosis_tx,\r
--- BUS_TX(4) => bustdc_tx,\r
+ BUS_TX(4) => busi2c_tx,\r
STAT_DEBUG => open\r
);\r
\r
FLASH_HOLD <= '1';\r
FLASH_WP <= '1';\r
\r
+---------------------------------------------------------------------------\r
+-- I2C\r
+---------------------------------------------------------------------------\r
+THE_I2C : entity work.i2c_slim \r
+ port map(\r
+ CLOCK => clk_40,\r
+ RESET => reset_i,\r
+ -- I2C command / setup\r
+ I2C_GO_IN => i2c_go,\r
+ ACTION_IN => i2c_reg_1(8), -- '0' -> write, '1' -> read\r
+ WORD_IN => i2c_reg_1(0), -- '0' -> byte, '1' -> word\r
+ I2C_SPEED_IN => i2c_reg_0(5 downto 0), -- speed adjustment (to be defined)\r
+ I2C_ADDR_IN => i2c_reg_2(7 downto 0), -- I2C address byte (R/W bit is ignored)\r
+ I2C_CMD_IN => i2c_reg_2(15 downto 8), -- I2C command byte (sent after address byte)\r
+ I2C_DW_IN => i2c_reg_2(31 downto 16),-- data word for write command\r
+ I2C_DR_OUT => i2c_reg_4(15 downto 0), -- data word from read command\r
+ STATUS_OUT => i2c_reg_4(23 downto 16),\r
+ VALID_OUT => i2c_reg_4(31),\r
+ I2C_BUSY_OUT => i2c_reg_4(30),\r
+ I2C_DONE_OUT => i2c_reg_4(29),\r
+ -- I2C connections\r
+ SDA_IN => PIN(4),\r
+ SDA_OUT => mimosis_sda_drv,\r
+ SCL_IN => PIN(3),\r
+ SCL_OUT => mimosis_scl_drv,\r
+ -- Debug\r
+ BSM_OUT => i2c_reg_4(28 downto 24)\r
+);\r
+\r
+-- I2C signal open collector driver\r
+PIN(4) <= '0' when (mimosis_sda_drv = '0') else 'Z';\r
+PIN(3) <= '0' when (mimosis_scl_drv = '0') else 'Z';\r
+H5(1) <= i2c_reg_5_40(0); --MIMOSIS_SYNC\r
+PIN(1) <= i2c_reg_5_40(4); --MIMOSIS_START\r
+PIN(2) <= i2c_reg_5_40(8); --MIMOSIS_RESET\r
+\r
+PROC_I2C_REGS : process begin\r
+ wait until rising_edge(CLK_SYS);\r
+ busi2c_tx.ack <= '0';\r
+ busi2c_tx.unknown <= '0';\r
+ busi2c_tx.nack <= '0';\r
+ busi2c_tx.data <= (others => '0');\r
+ i2c_go_100 <= '0';\r
+ \r
+ if busi2c_rx.write = '1' then\r
+ busi2c_tx.ack <= '1';\r
+ if busi2c_rx.addr(3 downto 0) = x"0" then\r
+ i2c_reg_0 <= busi2c_rx.data;\r
+ elsif busi2c_rx.addr(3 downto 0) = x"1" then\r
+ i2c_reg_1 <= busi2c_rx.data;\r
+ elsif busi2c_rx.addr(3 downto 0) = x"2" then\r
+ i2c_reg_2 <= busi2c_rx.data;\r
+ elsif busi2c_rx.addr(3 downto 0) = x"3" then\r
+ i2c_go_100 <= busi2c_rx.data(0);\r
+ elsif busi2c_rx.addr(3 downto 0) = x"5" then\r
+ i2c_reg_5 <= busi2c_rx.data;\r
+ else\r
+ busi2c_tx.ack <= '0';\r
+ busi2c_tx.unknown <= '1';\r
+ end if;\r
+ elsif busi2c_rx.read = '1' then\r
+ busi2c_tx.ack <= '1';\r
+ if busi2c_rx.addr(3 downto 0) = x"0" then\r
+ busi2c_tx.data <= i2c_reg_0;\r
+ elsif busi2c_rx.addr(3 downto 0) = x"1" then\r
+ busi2c_tx.data <= i2c_reg_1;\r
+ elsif busi2c_rx.addr(3 downto 0) = x"2" then\r
+ busi2c_tx.data <= i2c_reg_2;\r
+ elsif busi2c_rx.addr(3 downto 0) = x"3" then\r
+ busi2c_tx.data <= (others => '0');\r
+ elsif busi2c_rx.addr(3 downto 0) = x"4" then\r
+ busi2c_tx.data <= i2c_reg_4;\r
+ elsif busi2c_rx.addr(3 downto 0) = x"5" then\r
+ busi2c_tx.data <= i2c_reg_5;\r
+ else\r
+ busi2c_tx.ack <= '0';\r
+ busi2c_tx.unknown <= '1';\r
\r
+ end if;\r
+ end if;\r
+end process;\r
+\r
+ THE_I2C_GO_SYNC : pulse_sync\r
+ port map(\r
+ CLK_A_IN => clk_sys,\r
+ RESET_A_IN => reset_i,\r
+ PULSE_A_IN => i2c_go_100,\r
+ CLK_B_IN => clk_40,\r
+ RESET_B_IN => reset_i,\r
+ PULSE_B_OUT => i2c_go\r
+ );\r
+\r
+ THE_MIMOSIS_SIGNAL_SYNC : signal_sync \r
+ generic map(\r
+ WIDTH => 32,\r
+ DEPTH => 2\r
+ )\r
+ port map(\r
+ RESET => reset_i,\r
+ CLK0 => clk_sys,\r
+ CLK1 => clk_40,\r
+ D_IN => i2c_reg_5,\r
+ D_OUT => i2c_reg_5_40\r
+ );\r
+ \r
+\r
+\r
---------------------------------------------------------------------------\r
-- LED\r
---------------------------------------------------------------------------\r
TEST(14) <= flash_ncs_i;\r
FLASH_NCS <= flash_ncs_i; \r
\r
- ---------------------------------------------------------------------------\r
+---------------------------------------------------------------------------\r
-- Output stage\r
--------------------------------------------------------------------------- \r
THE_OUT : entity work.testout\r
when 3 => out_data <= x"0000";\r
when 4 => out_data <= x"5555";\r
when 5 => out_data <= x"5555";\r
- when 6 => out_data <= x"5555";--sdummy & dummy & dummy & dummy & dummy & dummy & dummy & dummy;\r
+ when 6 => out_data <= x"5555";--dummy & dummy & dummy & dummy & dummy & dummy & dummy & dummy;\r
when 7 => out_data <= x"5555";--dummy & dummy & dummy & dummy & dummy & dummy & dummy & dummy;\r
end case;\r
end process; \r
jspc29 / trb5sc.git / commitdiff