<Source name="soda_client.lpf" type="Logic Preference" type_short="LPF">
<Options/>
</Source>
+ <Source name="soda_client_probe.rvl" type="Reveal" type_short="Reveal">
+ <Options/>
+ </Source>
+ <Source name="trb3_soda_client.xcf" type="Programming Project File" type_short="Programming">
+ <Options/>
+ </Source>
</Implementation>
<Strategy name="Strategy1" file="soda_client1.sty"/>
</BaliProject>
+rvl_alias "clk_raw_internal" "clk_raw_internal";
BLOCK RESETPATHS ;
BLOCK ASYNCPATHS ;
BLOCK RD_DURING_WR_PATHS ;
MULTICYCLE TO CELL "THE_SODA_SOURCE/wa_pos*" 20 ns;
MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns;
+BLOCK JTAGPATHS;
<Source name="source/soda_superburst_gen.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="source/soda_packet_handler.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
<Source name="source/soda_packet_builder.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
<Source name="source/serdes_sync_downstream.ipx" type="IPX_Module" type_short="IPX">
<Options/>
</Source>
- <Source name="../trbnet/trb_net_components.vhd" type="VHDL" type_short="VHDL">
+ <Source name="source/soda_SOB_faker.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="source/soda_calibration_timer.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="source/soda_reply_handler.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
<Source name="../trbnet/trb_net16_term_buf.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
+ <Source name="../trbnet/trb_net_components.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
<Source name="../trbnet/trb_net_CRC.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
<Source name="../trbnet/special/spi_flash_and_fpga_reload.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="source/soda_reply_handler.vhd" type="VHDL" type_short="VHDL">
+ <Source name="../trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="source/soda_calibration_timer.vhd" type="VHDL" type_short="VHDL">
+ <Source name="source/posedge_to_pulse.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="source/soda_SOB_faker.vhd" type="VHDL" type_short="VHDL">
+ <Source name="soda_source.lpf" type="Logic Preference" type_short="LPF">
<Options/>
</Source>
- <Source name="../trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.vhd" type="VHDL" type_short="VHDL">
+ <Source name="soda_source_probe.rvl" type="Reveal" type_short="Reveal">
<Options/>
</Source>
- <Source name="soda_source.lpf" type="Logic Preference" type_short="LPF">
+ <Source name="trb3_soda_source.xcf" type="Programming Project File" type_short="Programming">
<Options/>
</Source>
</Implementation>
+rvl_alias "clk_raw_internal" "clk_raw_internal";
BLOCK RESETPATHS ;
BLOCK ASYNCPATHS ;
BLOCK RD_DURING_WR_PATHS ;
MULTICYCLE TO CELL "THE_SODA_SOURCE/wa_pos*" 20 ns;
MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns;
+BLOCK JTAGPATHS;
architecture TestBench of TB_soda_chain is\r
\r
-- Clock period definitions
- constant sysclk_period: time:= 5ns;
- constant sodaclk_period: time:= 4.999ns;
+ constant sysclk_period: time:= 10ns;
+ constant sodaclk_period: time:= 5ns;
\r
\r
--Inputs
THE_SODA_SOURCE : soda_source
port map(
SYSCLK => sys_clk_S,
+ SODACLK => soda_clk_S,
RESET => rst_S,
CLEAR => '0',
CLK_EN => '1',
use IEEE.STD_LOGIC_UNSIGNED.all;
entity posedge_to_pulse is
- port (
- clock_in : in std_logic;
- clock_out : in std_logic;
- en_clk : in std_logic;
- signal_in : in std_logic;
- pulse : out std_logic
- );
+ port (
+ IN_CLK : in std_logic;
+ OUT_CLK : in std_logic;
+ CLK_EN : in std_logic;
+ SIGNAL_IN : in std_logic;
+ PULSE_OUT : out std_logic
+ );
end posedge_to_pulse;
architecture behavioral of posedge_to_pulse is
- signal resetff : std_logic := '0';
- signal last_signal_in : std_logic := '0';
- signal qff : std_logic := '0';
- signal qff1 : std_logic := '0';
- signal qff2 : std_logic := '0';
- signal qff3 : std_logic := '0';
-begin
+ signal resetff : std_logic := '0';
+ signal last_signal_in : std_logic := '0';
+ signal qff : std_logic := '0';
+ signal qff1 : std_logic := '0';
+ signal qff2 : std_logic := '0';
+ signal qff3 : std_logic := '0';
+ begin
-process (clock_in)
-begin
- if rising_edge(clock_in) then
- if resetff='1' then
- qff <= '0';
- elsif (en_clk='1') and ((signal_in='1') and (qff='0') and (last_signal_in='0')) then
- qff <= '1';
- else
- qff <= qff;
+ process (IN_CLK)
+ begin
+ if rising_edge(IN_CLK) then
+ if resetff='1' then
+ qff <= '0';
+ elsif (CLK_EN='1') and ((SIGNAL_IN='1') and (qff='0') and (last_signal_in='0')) then
+ qff <= '1';
+ else
+ qff <= qff;
+ end if;
+ last_signal_in <= SIGNAL_IN;
end if;
- last_signal_in <= signal_in;
- end if;
-end process;
-resetff <= qff2;
+ end process;
-process (clock_out)
-begin
- if rising_edge(clock_out) then
- if qff3='0' and qff2='1' then
- pulse <= '1';
- else
- pulse <= '0';
+ resetff <= qff2;
+
+ process (OUT_CLK)
+ begin
+ if rising_edge(OUT_CLK) then
+ if qff3='0' and qff2='1' then
+ PULSE_OUT <= '1';
+ else
+ PULSE_OUT <= '0';
+ end if;
+ qff3 <= qff2;
+ qff2 <= qff1;
+ qff1 <= qff;
end if;
- qff3 <= qff2;
- qff2 <= qff1;
- qff1 <= qff;
- end if;
-end process;
+ end process;
end behavioral;
CLEAR : in std_logic; -- asynchronous reset
CLK_EN : in std_logic;
--Internal Connection
- LINK_PHASE : natural range 0 to 1 := 0;
+ LINK_PHASE_IN : in std_logic_vector(1 downto 0) := (others => '0');
SODA_CMD_STROBE_IN : in std_logic := '0'; --
START_OF_SUPERBURST : in std_logic := '0';
SUPER_BURST_NR_IN : in std_logic_vector(30 downto 0) := (others => '0');
IN_CLK : in std_logic;
OUT_CLK : in std_logic;
CLK_EN : in std_logic;
- SINGAL_IN : in std_logic;
+ SIGNAL_IN : in std_logic;
PULSE_OUT : out std_logic
);
end component;
library ieee;\r
use ieee.std_logic_1164.all;\r
use ieee.numeric_std.all;\r
+use ieee.std_logic_unsigned.all;
\r
library work;
use work.trb_net_std.all;
CLEAR : in std_logic; -- asynchronous reset\r
CLK_EN : in std_logic; \r
--Internal Connection\r
- LINK_PHASE : natural range 0 to 1 := 0;
+ LINK_PHASE_IN : in std_logic_vector(1 downto 0) := (others => '0');
SODA_CMD_STROBE_IN : in std_logic := '0'; -- \r
START_OF_SUPERBURST : in std_logic := '0';\r
SUPER_BURST_NR_IN : in std_logic_vector(30 downto 0) := (others => '0');\r
case packet_state_S is\r
when c_IDLE =>\r
if (START_OF_SUPERBURST='1') then
- if (LINK_PHASE=0) then\r
+ if (LINK_PHASE_IN = "00") then\r
packet_state_S <= c_BST1;
else
packet_state_S <= c_WAIT4BST1;
end if;\r
elsif (soda_cmd_strobe_S='1') then\r
- if (LINK_PHASE=0) then\r
+ if (LINK_PHASE_IN = "00") then\r
packet_state_S <= c_CMD1;\r
else
packet_state_S <= c_WAIT4CMD1;
else
packet_state_S <= c_IDLE;
end if;\r
--- when c_IDLE =>\r
--- if (START_OF_SUPERBURST='1') then\r
--- packet_state_S <= c_BST1;\r
--- elsif (soda_cmd_strobe_S='1') then\r
--- packet_state_S <= c_CMD1;\r
--- end if;\r
when c_WAIT4BST1 =>\r
- if (LINK_PHASE=0) then\r
+ if (LINK_PHASE_IN = "00") then\r
packet_state_S <= c_BST1;
else
packet_state_S <= c_WAIT4BST1;
packet_state_S <= c_CMD1;\r
end if;\r
when c_WAIT4CMD1 =>\r
- if (LINK_PHASE=0) then\r
+ if (LINK_PHASE_IN = "00") then
packet_state_S <= c_CMD1;\r
else
packet_state_S <= c_WAIT4CMD1;
CLEAR : in std_logic; -- asynchronous reset
CLK_EN : in std_logic;
--Internal Connection
--- LAST_PACKET _IN : in t_PACKET_TYPE_SENT := c_NO_PACKET;
EXPECTED_REPLY_IN : in std_logic_vector(7 downto 0) := (others => '0');
RX_DLM_IN : in std_logic := '0';
RX_DLM_WORD_IN : in std_logic_vector(7 downto 0) := (others => '0');
REPLY_VALID_OUT : out std_logic := '0';
--- SUPERBURST_ERROR_OUT : out std_logic := '0';
--- CRC_ERROR_OUT : out std_logic := '0';
REPLY_OK_OUT : out std_logic := '0'
);
end soda_reply_handler;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
library work;
use work.trb_net_std.all;
architecture Behavioral of soda_source is
-component posedge_to_pulse is
- port (
- clock_in : in std_logic;
- clock_out : in std_logic;
- en_clk : in std_logic;
- signal_in : in std_logic;
- pulse : out std_logic
- );
-end component;
-
--SODA
- signal link_phase_S : natural range 0 to 1 := 0;
+ signal link_phase_S : std_logic_vector(1 downto 0) := (others => '0');
signal soda_cmd_word_S : std_logic_vector(30 downto 0) := (others => '0');
signal soda_cmd_strobe_S : std_logic := '0';
signal soda_cmd_strobe_sodaclk_S : std_logic := '0';
type t_STATES is (SLEEP,RD_RDY,WR_RDY,RD_ACK,WR_ACK,DONE);
signal CURRENT_STATE, NEXT_STATE: t_STATES;
- signal last_packet_sent_S : t_PACKET_TYPE_SENT := c_NO_PACKET;
+-- signal last_packet_sent_S : t_PACKET_TYPE_SENT := c_NO_PACKET;
-- slave bus signals
signal bus_ack_x : std_logic;
CLEAR => '0',
CLK_EN => CLK_EN,
--Internal Connection
- LINK_PHASE => link_phase_S,
+ LINK_PHASE_IN => link_phase_S,
SODA_CMD_STROBE_IN => soda_cmd_strobe_sodaclk_S,
START_OF_SUPERBURST => start_of_superburst_S,
SUPER_BURST_NR_IN => super_burst_nr_S,
CLEAR => '0',
CLK_EN => '1',
--Internal Connection
--- LAST_PACKET => last_packet_sent_S,
EXPECTED_REPLY_IN => expected_reply_S,
RX_DLM_IN => RX_DLM_IN,
RX_DLM_WORD_IN => RX_DLM_WORD_IN,
begin
if rising_edge(SODACLK) then
if( RESET = '1' ) then
- link_phase_S <= 0;
+ link_phase_S <= (0 => '1', others => '0');
elsif (link_phase_S < 1) then
link_phase_S <= link_phase_S + 1;
else
- link_phase_S <= 0;
+ link_phase_S <= (others => '0');
end if;
end if;
end process;
------------------------------------------------------------
--- Transmission history for reply-checking --
------------------------------------------------------------
--- packet_history_proc : process(SYSCLK)
--- begin
--- if rising_edge(SYSCLK) then
--- if( RESET = '1' ) then
--- last_packet_sent_S <= c_NO_PACKET;
--- elsif (start_of_superburst_S='1') then
--- last_packet_sent_S <= c_BST_PACKET;
--- elsif (soda_cmd_strobe_S='1') then
--- last_packet_sent_S <= c_CMD_PACKET;
--- end if;
--- end if;
--- end process;
-
---------------------------------------------------------
-- RegIO Statemachine
---------------------------------------------------------
end case;
end process TRANSFORM;
-posedge_to_pulse1: posedge_to_pulse port map(
- clock_in => SYSCLK,
- clock_out => SODACLK,
- en_clk => '1',
- signal_in => soda_cmd_strobe_S,
- pulse => soda_cmd_strobe_sodaclk_S);
+soda_cmd_strobe_posedge_to_pulse: posedge_to_pulse
+ port map(
+ IN_CLK => SYSCLK,
+ OUT_CLK => SODACLK,
+ CLK_EN => '1',
+ SIGNAL_IN => soda_cmd_strobe_S,
+ PULSE_OUT => soda_cmd_strobe_sodaclk_S
+ );
---------------------------------------------------------
-- data handling --
elsif( (store_wr = '1') and (SODA_ADDR_IN = "0001") ) then
soda_cmd_strobe_S <= '0';
LEDregister_i <= SODA_DATA_IN;
--- elsif( (store_wr = '1') and (SODA_ADDR_IN = "0010") ) then
--- TEST_LINE_i <= SODA_DATA_IN;
else
soda_cmd_strobe_S <= '0';
end if;
buf_bus_data_out <= calib_register_S;
elsif( (store_rd = '1') and (SODA_ADDR_IN = "0011") ) then
buf_bus_data_out <= LEDregister_i;
--- elsif( (store_rd = '1') and (SODA_ADDR_IN = "0011") ) then
--- buf_bus_data_out <= TEST_LINE_i;
end if;
end if;
end process THE_READ_REG_PROC;
-- output signals
LEDS_OUT <= LEDregister_i(3 downto 0);
--- TEST_LINE <= TEST_LINE_i(15 downto 0);
SODA_DATA_OUT <= buf_bus_data_out;
SODA_ACK_OUT <= bus_ack;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_ARITH.ALL;
-use ieee.std_logic_signed.all;
+use ieee.std_logic_unsigned.all;
library work;
use work.trb_net_std.all;
---------------------------------------------------------------------------
THE_ENDPOINT : trb_net16_endpoint_hades_full_handler
generic map(
- USE_CHANNEL => (c_YES,c_YES,c_NO,c_YES),
+-- USE_CHANNEL => (c_YES,c_YES,c_NO,c_YES),
REGIO_NUM_STAT_REGS => REGIO_NUM_STAT_REGS, --4, --16 stat reg
REGIO_NUM_CTRL_REGS => REGIO_NUM_CTRL_REGS, --3, --8 cotrol reg
ADDRESS_MASK => x"FFFF",
--SODA
signal SOB_S : std_logic := '0';
--- signal soda_cmd_word_S : std_logic_vector(31 downto 0) := (others => '0');
--- signal soda_cmd_strobe_S : std_logic := '0';
--- signal SOS_S : std_logic := '0';
--- signal super_burst_nr_S : std_logic_vector(30 downto 0) := (others => '0'); -- from super-burst-nr-generator
--- signal dlm_word_S : std_logic_vector(7 downto 0) := (others => '0');
--- signal dlm_valid_S : std_logic;
+
begin
---------------------------------------------------------------------------
BUS_TIMEOUT_OUT(2) => open,
BUS_TIMEOUT_OUT(3) => open,
- BUS_DATA_IN(0*32+31 downto 0*32) => spimem_data_out,
- BUS_DATA_IN(1*32+7 downto 1*32) => sci1_data_out,
- BUS_DATA_IN(2*32+7 downto 2*32) => sci2_data_out,
- BUS_DATA_IN(3*32+31 downto 3*32) => soda_data_out,
+ BUS_DATA_IN(0*32+31 downto 0*32) => spimem_data_out,
+ BUS_DATA_IN(1*32+7 downto 1*32) => sci1_data_out,
+ BUS_DATA_IN(1*32+31 downto 1*32+8) => (others => '0'),
+ BUS_DATA_IN(2*32+7 downto 2*32) => sci2_data_out,
+ BUS_DATA_IN(2*32+31 downto 2*32+8) => (others => '0'),
+ BUS_DATA_IN(3*32+31 downto 3*32) => soda_data_out,
BUS_DATAREADY_IN(0) => spimem_dataready_out,
BUS_DATAREADY_IN(1) => sci1_ack,
THE_SOB_SOURCE : soda_start_of_burst_faker
port map(
- SYSCLK => clk_raw_internal,
+ SYSCLK => soda_rx_clock_half, --clk_raw_internal,
RESET => reset_i,
SODA_BURST_PULSE_OUT => SOB_S
);
jspc29 / soda.git / commitdiff