###################################################################################
#Settings for this project
my $TOPNAME = "trb3_periph_adc"; #Name of top-level entity
-my $lattice_path = '/d/jspc29/lattice/diamond/3.0_x64';
-my $synplify_path = '/d/jspc29/lattice/synplify/I-2013.09-SP1/';
+my $lattice_path = '/d/jspc29/lattice/diamond/2.1_x64';
+my $synplify_path = '/d/jspc29/lattice/synplify/F-2012.03-SP1/';
my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de";
my $lm_license_file_for_par = "1702\@hadeb05.gsi.de";
###################################################################################
add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd"
add_file -vhdl -lib "work" "../base/cores/pll_in200_out100.vhd"
-
+add_file -vhdl -lib "work" "../base/cores/pll_in200_out40.vhd"
add_file -vhdl -lib "work" "../base/cores/pll_adc10bit.vhd"
add_file -vhdl -lib "work" "../base/cores/dqsinput_7x5.vhd"
add_file -vhdl -lib "work" "../base/cores/dqsinput_5x5.vhd"
signal clk_adcref_i : std_logic;
signal debug_adc : std_logic_vector(31 downto 0);
signal adc_restart_i : std_logic;
-type q_t is array(0 to 4) of std_logic_vector(19 downto 0);
-signal q : q_t;
-signal clk_data_left : std_logic;
+
+ signal adc_data : std_logic_vector(479 downto 0);
+
begin
---------------------------------------------------------------------------
-- Reset Generation
---------------------------------------------------------------------------
THE_MAIN_PLL : pll_in200_out100
port map(
- CLK => CLK_GPLL_RIGHT,
+ CLK => CLK_PCLK_LEFT,
CLKOP => clk_100_i,
CLKOK => clk_200_i,
LOCK => pll_lock
);
- THE_ADC_PLL : entity work.pll_adc10bit
- port map(
- CLK => CLK_PCLK_RIGHT,
- CLKOS => open,
- CLKOP => clk_adcref_i,
- LOCK => open
- );
-
- clk_adcfast_i <= clk_200_i;
+
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- AddOn
---------------------------------------------------------------------------
--- THE_ADC : entity work.adc_ad9219
--- generic map(
--- CHANNELS => 4,
--- DEVICES_LEFT => 7,
--- DEVICES_RIGHT => 5,
--- RESOLUTION => 10
--- )
--- port map(
--- CLK => clk_100_i,
--- CLK_ADCREF => clk_adcref_i,
--- CLK_ADCDAT => clk_adcfast_i,
--- RESTART_IN => adc_restart_i,
--- ADCCLK_OUT => P_CLOCK,
---
--- ADC_DATA( 4 downto 0) => ADC1_CH,
--- ADC_DATA( 9 downto 5) => ADC2_CH,
--- ADC_DATA(14 downto 10) => ADC3_CH,
--- ADC_DATA(19 downto 15) => ADC4_CH,
--- ADC_DATA(24 downto 20) => ADC5_CH,
--- ADC_DATA(29 downto 25) => ADC6_CH,
--- ADC_DATA(34 downto 30) => ADC7_CH,
--- ADC_DATA(39 downto 35) => ADC8_CH,
--- ADC_DATA(44 downto 40) => ADC9_CH,
--- ADC_DATA(49 downto 45) => ADC10_CH,
--- ADC_DATA(54 downto 50) => ADC11_CH,
--- ADC_DATA(59 downto 55) => ADC12_CH,
---
--- ADC_DCO => ADC_DCO,
---
--- DATA_OUT => open,
--- FCO_OUT => open,
--- DATA_VALID_OUT => open,
--- DEBUG => debug_adc
--- );
-
-
-THE_LEFT : entity work.dqsinput_5x5
- port map(
- clk_0 => ADC_DCO(8),
- clk_1 => ADC_DCO(9),
- clk_2 => ADC_DCO(10),
- clk_3 => ADC_DCO(11),
- clk_4 => ADC_DCO(12),
- clkdiv_reset => '0',
- eclk => clk_adcref_i,
- reset_0 => '0',
- reset_1 => '0',
- reset_2 => '0',
- reset_3 => '0',
- reset_4 => '0',
- sclk => clk_data_left,
- datain_0 => ADC8_CH,
- datain_1 => ADC9_CH,
- datain_2 => ADC10_CH,
- datain_3 => ADC11_CH,
- datain_4 => ADC12_CH,
- q_0 => q(0),
- q_1 => q(1),
- q_2 => q(2),
- q_3 => q(3),
- q_4 => q(4)
- );
-
-
---Just to hinder optimization to remove the DDR buffers
-LED_RED <= q(0)(0) or q(1)(0) or q(2)(0) or q(3)(0) or q(4)(0);
-
-
+THE_ADC : entity work.adc_ad9219
+ generic map(
+ CHANNELS => 4,
+ DEVICES_LEFT => 7,
+ DEVICES_RIGHT => 5,
+ RESOLUTION => 10
+ )
+ port map(
+ CLK => clk_100_i,
+ CLK_ADCRAW => CLK_PCLK_RIGHT,
+ CLK_ADCREF => clk_adcref_i,
+ CLK_ADCDAT => clk_adcfast_i,
+ RESTART_IN => adc_restart_i,
+ ADCCLK_OUT => P_CLOCK,
+
+ ADC_DATA( 4 downto 0) => ADC1_CH,
+ ADC_DATA( 9 downto 5) => ADC2_CH,
+ ADC_DATA(14 downto 10) => ADC3_CH,
+ ADC_DATA(19 downto 15) => ADC4_CH,
+ ADC_DATA(24 downto 20) => ADC5_CH,
+ ADC_DATA(29 downto 25) => ADC6_CH,
+ ADC_DATA(34 downto 30) => ADC7_CH,
+ ADC_DATA(39 downto 35) => ADC8_CH,
+ ADC_DATA(44 downto 40) => ADC9_CH,
+ ADC_DATA(49 downto 45) => ADC10_CH,
+ ADC_DATA(54 downto 50) => ADC11_CH,
+ ADC_DATA(59 downto 55) => ADC12_CH,
+
+ ADC_DCO => ADC_DCO,
+
+ DATA_OUT => adc_data,
+ FCO_OUT => open,
+ DATA_VALID_OUT => open,
+ DEBUG => debug_adc
+ );
adc_restart_i <= '0';
FPGA_SPI : spi_ltc2600
generic map (
- BITS => 16,
+ BITS => 32,
WAITCYCLES => 15)
port map (
CLK_IN => clk_100_i,
+ SPI_ADC_SCK <= clk_100_i;
+ SPI_ADC_SDIO <= '0';
+
+ LMK_CLK <= clk_100_i;
+ LMK_DATA <= '0';
+ LMK_LE_1 <= reset_i;
+ LMK_LE_2 <= reset_i;
+
+
---------------------------------------------------------------------------
-- LED
---------------------------------------------------------------------------
LED_GREEN <= not med_stat_op(9);
LED_ORANGE <= not med_stat_op(10);
--- LED_RED <= not or_all(debug_adc) when rising_edge(clk_100_i);
+LED_RED <= not or_all(debug_adc) when rising_edge(clk_100_i);
LED_YELLOW <= not med_stat_op(11);
---------------------------------------------------------------------------
--- /dev/null
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+BLOCK RD_DURING_WR_PATHS ;
+
+#################################################################
+# Basic Settings
+#################################################################
+
+ SYSCONFIG MCCLK_FREQ = 20;
+
+ FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
+ FREQUENCY PORT CLK_PCLK_LEFT 200 MHz;
+ FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz;
+ FREQUENCY PORT CLK_GPLL_LEFT 125 MHz;
+
+#################################################################
+# Reset Nets
+#################################################################
+GSR_NET NET "GSR_N";
+
+MULTICYCLE TO CELL "THE_RESET_HANDLER/final_reset*" 20 ns;
+
+
+#################################################################
+# Clocks
+#################################################################
+USE PRIMARY NET "CLK_GPLL_RIGHT_c";
+USE PRIMARY NET "CLK_PCLK_LEFT_c";
+USE PRIMARY NET "CLK_PCLK_RIGHT_c";
+
+#USE PRIMARY2EDGE NET "THE_ADC/clk_adcfast_i_0";
+#USE PRIMARY2EDGE NET "THE_ADC/clk_adcfast_i_1";
+
<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="pll_adc10bit" module="PLL" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 01 31 19:35:11.856" version="5.4" type="Module" synthesis="" source_format="VHDL">
+<DiamondModule name="pll_adc10bit" module="PLL" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 02 27 18:02:54.297" version="5.3" type="Module" synthesis="" source_format="VHDL">
<Package>
- <File name="pll_adc10bit.lpc" type="lpc" modified="2014 01 31 19:35:08.000"/>
- <File name="pll_adc10bit.vhd" type="top_level_vhdl" modified="2014 01 31 19:35:08.000"/>
- <File name="pll_adc10bit_tmpl.vhd" type="template_vhdl" modified="2014 01 31 19:35:08.000"/>
+ <File name="pll_adc10bit.lpc" type="lpc" modified="2014 02 27 18:02:53.000"/>
+ <File name="pll_adc10bit.vhd" type="top_level_vhdl" modified="2014 02 27 18:02:53.000"/>
+ <File name="pll_adc10bit_tmpl.vhd" type="template_vhdl" modified="2014 02 27 18:02:53.000"/>
</Package>
</DiamondModule>
CoreType=LPM
CoreStatus=Demo
CoreName=PLL
-CoreRevision=5.4
+CoreRevision=5.3
ModuleName=pll_adc10bit
SourceFormat=VHDL
ParameterFileVersion=1.0
-Date=01/31/2014
-Time=19:35:08
+Date=02/27/2014
+Time=18:02:53
[Parameters]
Verilog=0
Type=ehxpllb
mode=normal
IFrq=200
-Div=5
+Div=1
ClkOPBp=0
-Post=16
-U_OFrq=40
+Post=4
+U_OFrq=200
OP_Tol=0.0
-OFrq=40.000000
+OFrq=200.000000
DutyTrimP=Rising
DelayMultP=0
-fb_mode=CLKOP
+fb_mode=Internal
Mult=1
Phase=0.0
Duty=8
DelayMultD=0
ClkOSDelay=0
PhaseDuty=Static
-CLKOK_INPUT=CLKOP
+CLKOK_INPUT=CLKOS
SecD=6
U_KFrq=40
OK_Tol=10.0
PCDR=0
FINDELA=0
VcoRate=
-Bandwidth=2.191564
+Bandwidth=2.970786
;DelayControl=No
-EnCLKOS=1
-ClkOSBp=1
+EnCLKOS=0
+ClkOSBp=0
EnCLKOK=0
ClkOKBp=0
enClkOK2=0
--- VHDL netlist generated by SCUBA Diamond_2.2_Production (99)
--- Module Version: 5.4
---/d/jspc29/lattice/diamond/2.2_x64/ispfpga/bin/lin64/scuba -w -n pll_adc10bit -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -bypasss -fclkop 40 -fclkop_tol 0.0 -fb_mode CLOCKTREE -phaseadj 0.0 -duty 8 -noclkok -norst -noclkok2 -bw -e
+-- VHDL netlist generated by SCUBA Diamond_2.1_Production (100)
+-- Module Version: 5.3
+--/d/jspc29/lattice/diamond/2.1_x64/ispfpga/bin/lin64/scuba -w -n pll_adc10bit -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -fclkop 200 -fclkop_tol 0.0 -fb_mode INTERNAL -noclkos -noclkok -norst -noclkok2 -bw -e
--- Fri Jan 31 19:35:08 2014
+-- Thu Feb 27 18:02:53 2014
library IEEE;
use IEEE.std_logic_1164.all;
port (
CLK: in std_logic;
CLKOP: out std_logic;
- CLKOS: out std_logic;
LOCK: out std_logic);
attribute dont_touch : boolean;
attribute dont_touch of pll_adc10bit : entity is true;
architecture Structure of pll_adc10bit is
-- internal signal declarations
- signal CLKOS_t: std_logic;
signal CLKOP_t: std_logic;
+ signal CLKFB_t: std_logic;
signal scuba_vlo: std_logic;
-- local component declarations
port (Z: out std_logic);
end component;
attribute FREQUENCY_PIN_CLKOP : string;
- attribute FREQUENCY_PIN_CLKOS : string;
attribute FREQUENCY_PIN_CLKI : string;
- attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "40.000000";
- attribute FREQUENCY_PIN_CLKOS of PLLInst_0 : label is "200.000000";
+ attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "200.000000";
attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "200.000000";
attribute syn_keep : boolean;
attribute syn_noprune : boolean;
port map (Z=>scuba_vlo);
PLLInst_0: EHXPLLF
- generic map (FEEDBK_PATH=> "CLKOP", CLKOK_BYPASS=> "DISABLED",
- CLKOS_BYPASS=> "ENABLED", CLKOP_BYPASS=> "DISABLED", CLKOK_INPUT=> "CLKOP",
- DELAY_PWD=> "DISABLED", DELAY_VAL=> 0, CLKOS_TRIM_DELAY=> 0,
- CLKOS_TRIM_POL=> "RISING", CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "RISING",
+ generic map (FEEDBK_PATH=> "INTERNAL", CLKOK_BYPASS=> "DISABLED",
+ CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED",
+ CLKOK_INPUT=> "CLKOP", DELAY_PWD=> "DISABLED", DELAY_VAL=> 0,
+ CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "RISING",
+ CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "RISING",
PHASE_DELAY_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0",
- CLKOK_DIV=> 2, CLKOP_DIV=> 16, CLKFB_DIV=> 1, CLKI_DIV=> 5,
+ CLKOK_DIV=> 2, CLKOP_DIV=> 4, CLKFB_DIV=> 1, CLKI_DIV=> 1,
FIN=> "200.000000")
- port map (CLKI=>CLK, CLKFB=>CLKOP_t, RST=>scuba_vlo,
+ port map (CLKI=>CLK, CLKFB=>CLKFB_t, RST=>scuba_vlo,
RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo,
DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo,
DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo,
DFPAI0=>scuba_vlo, FDA3=>scuba_vlo, FDA2=>scuba_vlo,
FDA1=>scuba_vlo, FDA0=>scuba_vlo, CLKOP=>CLKOP_t,
- CLKOS=>CLKOS_t, CLKOK=>open, CLKOK2=>open, LOCK=>LOCK,
- CLKINTFB=>open);
+ CLKOS=>open, CLKOK=>open, CLKOK2=>open, LOCK=>LOCK,
+ CLKINTFB=>CLKFB_t);
- CLKOS <= CLKOS_t;
CLKOP <= CLKOP_t;
end Structure;
# ADC INPUTS
#################################################################
-
LOCATE COMP "ADC1_CH_0" SITE "P1";
LOCATE COMP "ADC1_CH_1" SITE "T2";
LOCATE COMP "ADC1_CH_2" SITE "R1";
LOCATE COMP "ADC_DCO_6" SITE "G5";
LOCATE COMP "ADC6_CH_4" SITE "H6";
-LOCATE COMP "ADC7_CH_0" SITE "G2";
-LOCATE COMP "ADC7_CH_1" SITE "F2";
-LOCATE COMP "ADC7_CH_2" SITE "C2";
-LOCATE COMP "ADC7_CH_3" SITE "H5";
-LOCATE COMP "ADC_DCO_7" SITE "K7";
-LOCATE COMP "ADC7_CH_4" SITE "K8";
+LOCATE COMP "ADC7_CH_0" SITE "J23";
+LOCATE COMP "ADC7_CH_1" SITE "G26";
+LOCATE COMP "ADC7_CH_2" SITE "H26";
+LOCATE COMP "ADC7_CH_3" SITE "K23";
+LOCATE COMP "ADC_DCO_7" SITE "F24";
+LOCATE COMP "ADC7_CH_4" SITE "F25";
-LOCATE COMP "ADC8_CH_0" SITE "W23";
-LOCATE COMP "ADC8_CH_1" SITE "AA25";
-LOCATE COMP "ADC8_CH_2" SITE "AA26";
-LOCATE COMP "ADC8_CH_3" SITE "AA24";
-LOCATE COMP "ADC_DCO_8" SITE "W21";
-LOCATE COMP "ADC8_CH_4" SITE "AD26";
+LOCATE COMP "ADC8_CH_0" SITE "G2";
+LOCATE COMP "ADC8_CH_1" SITE "F2";
+LOCATE COMP "ADC8_CH_2" SITE "C2";
+LOCATE COMP "ADC8_CH_3" SITE "H5";
+LOCATE COMP "ADC_DCO_8" SITE "K7";
+LOCATE COMP "ADC8_CH_4" SITE "K8";
LOCATE COMP "ADC9_CH_0" SITE "AC26";
LOCATE COMP "ADC9_CH_1" SITE "Y19";
LOCATE COMP "ADC_DCO_11" SITE "P23";
LOCATE COMP "ADC11_CH_4" SITE "P21";
-LOCATE COMP "ADC12_CH_0" SITE "J23";
-LOCATE COMP "ADC12_CH_1" SITE "G26";
-LOCATE COMP "ADC12_CH_2" SITE "H26";
-LOCATE COMP "ADC12_CH_3" SITE "K23";
-LOCATE COMP "ADC_DCO_12" SITE "F24";
-LOCATE COMP "ADC12_CH_4" SITE "F25";
+LOCATE COMP "ADC12_CH_0" SITE "W23";
+LOCATE COMP "ADC12_CH_1" SITE "AA25";
+LOCATE COMP "ADC12_CH_2" SITE "AA26";
+LOCATE COMP "ADC12_CH_3" SITE "AA24";
+LOCATE COMP "ADC_DCO_12" SITE "W21";
+LOCATE COMP "ADC12_CH_4" SITE "AD26";
DEFINE PORT GROUP "ADC_group" "ADC*" ;
IOBUF GROUP "ADC_group" IO_TYPE=LVDS25 DIFFRESISTOR=100;
LOCATE COMP "FPGA_SDO_1" SITE "T24";
DEFINE PORT GROUP "FPGA_group" "FPGA_*" ;
IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN;
+
jspc29 / trb3.git / commitdiff