]> jspc29.x-matter.uni-frankfurt.de Git - TOMcat.git/commitdiff
first working version
authorMichael Boehmer <mboehmer@ph.tum.de>
Mon, 27 Jun 2022 22:03:59 +0000 (00:03 +0200)
committerMichael Boehmer <mboehmer@ph.tum.de>
Mon, 27 Jun 2022 22:03:59 +0000 (00:03 +0200)
cores/serdes_gbe.vhd
gbe/tomcat_gbe.lpf
gbe/tomcat_gbe.vhd

index a2fb73089e2493e7021db3f73417bf3e9bf2d9dc..4947ba969ec2b1f1c06741fcbc2ce4e75c57db4b 100644 (file)
@@ -103,7 +103,7 @@ begin
         D_CDR_LOL_SET=>"0b11",D_TXPLL_PWDNB=>"0b1",D_BITCLK_LOCAL_EN=>"0b1",
         D_BITCLK_ND_EN=>"0b0",D_BITCLK_FROM_ND_EN=>"0b0",D_SYNC_LOCAL_EN=>"0b1",
         D_SYNC_ND_EN=>"0b0",CH0_UC_MODE=>"0b0",CH0_PCIE_MODE=>"0b0",CH0_RIO_MODE=>"0b0",
-        CH0_WA_MODE=>"0b0",CH0_INVERT_RX=>"0b0",CH0_INVERT_TX=>"0b0",CH0_PRBS_SELECTION=>"0b0",
+        CH0_WA_MODE=>"0b0",CH0_INVERT_RX=>"0b0",CH0_INVERT_TX=>"0b1",CH0_PRBS_SELECTION=>"0b0",
         CH0_GE_AN_ENABLE=>"0b1",CH0_PRBS_LOCK=>"0b0",CH0_PRBS_ENABLE=>"0b0",
         CH0_ENABLE_CG_ALIGN=>"0b1",CH0_TX_GEAR_MODE=>"0b0",CH0_RX_GEAR_MODE=>"0b0",
         CH0_PCS_DET_TIME_SEL=>"0b00",CH0_PCIE_EI_EN=>"0b0",CH0_TX_GEAR_BYPASS=>"0b0",
index 10feea9f9584033cde43f28cc16ad9199e649974..4ea8f7e96fdb284264bd1dc4e77e8453b04df59b 100644 (file)
@@ -7,12 +7,10 @@ BLOCK RD_DURING_WR_PATHS ;
 # Basic Settings
 #################################################################
 
-#FREQUENCY PORT CLK_200       200 MHz;
-#FREQUENCY PORT CLK_125       125 MHz;
-
 FREQUENCY NET "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/serdes_sync_0_inst/clk_tx_full" 200 MHz;
 FREQUENCY NET "THE_MEDIA_INTERFACE/gen_pcs1.THE_SERDES/serdes_sync_0_inst/clk_tx_full" 200 MHz;
 
+# to be checked...
 FREQUENCY NET "med2int_0.clk_full" 200 MHz;
 
 BLOCK PATH TO   PORT "LED*";
@@ -34,6 +32,3 @@ GSR_NET NET "clear_i";
 REGION               "MEDIA" "R81C44D" 13 25;
 LOCATE UGROUP        "THE_MEDIA_INTERFACE/media_interface_group" REGION "MEDIA" ;
 
-FREQUENCY NET "GBE/clk_125_rx_from_pcs"            125.000 MHz;
-FREQUENCY NET "CLK_125_c"                          125.000 MHz;
-FREQUENCY NET "GBE/physical/gbe_serdes/tx_pclk"    125.000 MHz;
index 8a37076135940d1f1982a81800a6542093012bf3..c58f248b254908faed92b60ec10d5265577cbe0c 100644 (file)
@@ -273,10 +273,12 @@ begin
 -------------------------------------------------------------------------------
 --  INTCOM(19 downto 0) <= (others => '0');
   INTCOM              <= debug(19 downto 0);
+--  INTCOM(19 downto 0) <= (others => 'Z');
   
 --  GPIO                <= (others => '0');
   GPIO(15 downto 14)  <= (others => '0');
   GPIO(13 downto 0)   <= debug(33 downto 20);
+--  GPIO                <= (others => 'Z');
   
   TIMING_TEST         <= reset_via_gbe; --'0';
 
@@ -286,8 +288,8 @@ begin
   LED_SFP_GREEN   <= not '0';
   LED_SFP_RED     <= not '0';
   LED_SFP_YELLOW  <= not '0';
-  LED(3)          <= not debug(9); --'0'; LRR
-  LED(2)          <= not debug(10); --'0'; LTR
+  LED(3)          <= not debug(126); --'0'; LRR
+  LED(2)          <= not debug(127); --'0'; LTR
   LED(1)          <= not '0';
   LED(0)          <= not '0';