D_CDR_LOL_SET=>"0b11",D_TXPLL_PWDNB=>"0b1",D_BITCLK_LOCAL_EN=>"0b1",
D_BITCLK_ND_EN=>"0b0",D_BITCLK_FROM_ND_EN=>"0b0",D_SYNC_LOCAL_EN=>"0b1",
D_SYNC_ND_EN=>"0b0",CH0_UC_MODE=>"0b0",CH0_PCIE_MODE=>"0b0",CH0_RIO_MODE=>"0b0",
- CH0_WA_MODE=>"0b0",CH0_INVERT_RX=>"0b0",CH0_INVERT_TX=>"0b0",CH0_PRBS_SELECTION=>"0b0",
+ CH0_WA_MODE=>"0b0",CH0_INVERT_RX=>"0b0",CH0_INVERT_TX=>"0b1",CH0_PRBS_SELECTION=>"0b0",
CH0_GE_AN_ENABLE=>"0b1",CH0_PRBS_LOCK=>"0b0",CH0_PRBS_ENABLE=>"0b0",
CH0_ENABLE_CG_ALIGN=>"0b1",CH0_TX_GEAR_MODE=>"0b0",CH0_RX_GEAR_MODE=>"0b0",
CH0_PCS_DET_TIME_SEL=>"0b00",CH0_PCIE_EI_EN=>"0b0",CH0_TX_GEAR_BYPASS=>"0b0",
# Basic Settings
#################################################################
-#FREQUENCY PORT CLK_200 200 MHz;
-#FREQUENCY PORT CLK_125 125 MHz;
-
FREQUENCY NET "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/serdes_sync_0_inst/clk_tx_full" 200 MHz;
FREQUENCY NET "THE_MEDIA_INTERFACE/gen_pcs1.THE_SERDES/serdes_sync_0_inst/clk_tx_full" 200 MHz;
+# to be checked...
FREQUENCY NET "med2int_0.clk_full" 200 MHz;
BLOCK PATH TO PORT "LED*";
REGION "MEDIA" "R81C44D" 13 25;
LOCATE UGROUP "THE_MEDIA_INTERFACE/media_interface_group" REGION "MEDIA" ;
-FREQUENCY NET "GBE/clk_125_rx_from_pcs" 125.000 MHz;
-FREQUENCY NET "CLK_125_c" 125.000 MHz;
-FREQUENCY NET "GBE/physical/gbe_serdes/tx_pclk" 125.000 MHz;
-------------------------------------------------------------------------------
-- INTCOM(19 downto 0) <= (others => '0');
INTCOM <= debug(19 downto 0);
+-- INTCOM(19 downto 0) <= (others => 'Z');
-- GPIO <= (others => '0');
GPIO(15 downto 14) <= (others => '0');
GPIO(13 downto 0) <= debug(33 downto 20);
+-- GPIO <= (others => 'Z');
TIMING_TEST <= reset_via_gbe; --'0';
LED_SFP_GREEN <= not '0';
LED_SFP_RED <= not '0';
LED_SFP_YELLOW <= not '0';
- LED(3) <= not debug(9); --'0'; LRR
- LED(2) <= not debug(10); --'0'; LTR
+ LED(3) <= not debug(126); --'0'; LRR
+ LED(2) <= not debug(127); --'0'; LTR
LED(1) <= not '0';
LED(0) <= not '0';