STATE_OUT => tx_fsm_state
);
--- Master does not do bit-locking
-wa_position_rx <= wa_position when (IS_SYNC_SLAVE = 1) else x"0000";
+
+
+-- Master does not do bit-locking
+SYNC_WA_POSITION : process begin
+ wait until rising_edge(clk_200_i);
+ if IS_SYNC_SLAVE = 1 then
+ wa_position_rx <= wa_position;
+ else
+ wa_position_rx <= x"0000";
+ end if;
+end process;
--Slave enables RX/TX when sync is done, Master waits additional time to make sure link is stable
-------------------------------------------------
-- Debug Registers
-------------------------------------------------
-debug_reg(3 downto 0) <= rx_fsm_state;
+debug_reg(2 downto 0) <= rx_fsm_state(2 downto 0);
+debug_reg(3) <= rx_serdes_rst;
debug_reg(4) <= CLEAR;
debug_reg(5) <= tx_allow_q;
debug_reg(6) <= rx_los_low;
debug_reg(11) <= CTRL_OP(15);
debug_reg(12) <= make_link_reset_i;
debug_reg(13) <= send_link_reset_i;
-debug_reg(14) <= rst_qd;
+debug_reg(14) <= sd_los_i;
debug_reg(15) <= rx_pcs_rst;
-- debug_reg(31 downto 24) <= tx_data;
HUB_STAT_GEN(31 downto 4) <= (others => '0');
TIMER_TICKS_OUT(0) <= timer_us_tick;
- TIMER_TICKS_OUT(1) <= timer_us_tick;
+ TIMER_TICKS_OUT(1) <= timer_ms_tick;
end architecture;