gbe update

diff --git a/gbe2_ecp3/tb_gbe_buf.vhd b/gbe2_ecp3/tb_gbe_buf.vhd
index 959173bf57a367b1e2e9c09f131ae82575efdfe1..d953228b28a94d6735e5d6b3e727f5e14eff6e83 100755 (executable)
--- a/gbe2_ecp3/tb_gbe_buf.vhd
+++ b/gbe2_ecp3/tb_gbe_buf.vhd
@@ -276,33 +276,33 @@ begin
 end process CLOCK2_GEN_PROC;
 
 
-SCTRL_TESTBENCH_PROC : process
-begin
-
-for j in 0 to 5000 loop
-
-       reply_dataready <= '0';
-       reply_busy <= '0';
-       reply_data <= (others => '0');
-       
-       wait for 76 us;
-       
-       for i in 0 to 1000 loop
-       
-               wait until rising_edge(clk);
-               reply_dataready <= '1';
-               reply_busy <= '1';
-               reply_data <= std_logic_vector(to_unsigned(i, 16));
-                       
-       end loop;
-       wait until rising_edge(clk);
-       reply_dataready <= '0';
-       reply_busy <= '0';
-       
-       wait for 13 us;
-end loop;
-
-end process SCTRL_TESTBENCH_PROC;
+--SCTRL_TESTBENCH_PROC : process
+--begin
+--
+--for j in 0 to 5000 loop
+--
+--     reply_dataready <= '0';
+--     reply_busy <= '0';
+--     reply_data <= (others => '0');
+--     
+--     wait for 76 us;
+--     
+--     for i in 0 to 1000 loop
+--     
+--             wait until rising_edge(clk);
+--             reply_dataready <= '1';
+--             reply_busy <= '1';
+--             reply_data <= std_logic_vector(to_unsigned(i, 16));
+--                     
+--     end loop;
+--     wait until rising_edge(clk);
+--     reply_dataready <= '0';
+--     reply_busy <= '0';
+--     
+--     wait for 13 us;
+--end loop;
+--
+--end process SCTRL_TESTBENCH_PROC;
 
 
 
@@ -398,7 +398,7 @@ begin
 
        --ip_cfg_start_in <= '1';
 
-       wait for 500 ns;
+       wait for 700 us;
 
 
 -------------------------------------------------------------------------------
@@ -413,17 +413,29 @@ begin
        wait until rising_edge(RX_MAC_CLK);
        MAC_RX_EN_IN <= '1';
 -- dest mac
-       MAC_RXD_IN              <= x"02";
+--     MAC_RXD_IN              <= x"02";
+--     wait until rising_edge(RX_MAC_CLK);
+--     MAC_RXD_IN              <= x"00";
+--     wait until rising_edge(RX_MAC_CLK);
+--     MAC_RXD_IN              <= x"be";
+--     wait until rising_edge(RX_MAC_CLK);
+--     MAC_RXD_IN              <= x"00";
+--     wait until rising_edge(RX_MAC_CLK);
+--     MAC_RXD_IN              <= x"00";
+--     wait until rising_edge(RX_MAC_CLK);
+--     MAC_RXD_IN              <= x"00";
+--     wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"ff";
        wait until rising_edge(RX_MAC_CLK);
-       MAC_RXD_IN              <= x"00";
+       MAC_RXD_IN              <= x"ff";
        wait until rising_edge(RX_MAC_CLK);
-       MAC_RXD_IN              <= x"be";
+       MAC_RXD_IN              <= x"ff";
        wait until rising_edge(RX_MAC_CLK);
-       MAC_RXD_IN              <= x"00";
+       MAC_RXD_IN              <= x"ff";
        wait until rising_edge(RX_MAC_CLK);
-       MAC_RXD_IN              <= x"00";
+       MAC_RXD_IN              <= x"ff";
        wait until rising_edge(RX_MAC_CLK);
-       MAC_RXD_IN              <= x"00";
+       MAC_RXD_IN              <= x"ff";
        wait until rising_edge(RX_MAC_CLK);
 -- src mac
        MAC_RXD_IN              <= x"00";
@@ -510,9 +522,9 @@ begin
        wait until rising_edge(RX_MAC_CLK);
        MAC_RXD_IN              <= x"00";
        wait until rising_edge(RX_MAC_CLK);
-       MAC_RXD_IN              <= x"de";
+       MAC_RXD_IN              <= x"00";
        wait until rising_edge(RX_MAC_CLK);
-       MAC_RXD_IN              <= x"ad";
+       MAC_RXD_IN              <= x"00";
        wait until rising_edge(RX_MAC_CLK);
        MAC_RXD_IN              <= x"fa";
        wait until rising_edge(RX_MAC_CLK);
@@ -566,7 +578,157 @@ begin
        
        
        
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RX_EN_IN <= '1';
+-- dest mac
+       MAC_RXD_IN              <= x"02";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"00";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"be";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"00";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"00";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"00";
+       wait until rising_edge(RX_MAC_CLK);
+-- src mac
+       MAC_RXD_IN              <= x"00";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"aa";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"bb";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"cc";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"dd";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"ee";
+       wait until rising_edge(RX_MAC_CLK);
+-- frame type
+       MAC_RXD_IN              <= x"08";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"00";
+       wait until rising_edge(RX_MAC_CLK);
+-- ip headers
+       MAC_RXD_IN              <= x"45";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"10";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"01";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"5a";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"49";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"00";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"00";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"00";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"ff";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"11";  -- udp
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"cc";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"cc";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"c0";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"a8";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"00";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"01";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"c0";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"a8";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"00";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"02";
+-- udp headers
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"00";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"43";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"00";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"44";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"02";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"2c";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"aa";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"bb";
+-- dhcp data
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"02";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"01";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"06";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"00";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"00";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"00";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"fa";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"ce";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"00";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"00";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"00";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"00";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"00";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"00";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"00";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"00";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"c0";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"a8";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"00";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"10";
+       
+       for i in 0 to 219 loop
+               wait until rising_edge(RX_MAC_CLK);
+               MAC_RXD_IN              <= x"00";
+       end loop;
+       
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"35";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"01";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"02";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"00";
+       wait until rising_edge(RX_MAC_CLK);
+               MAC_RX_EOF_IN <= '1';
        
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RX_EN_IN <='0';
+       MAC_RX_EOF_IN <= '0';
        
        
        

diff --git a/gbe2_ecp3/trb_net16_gbe_buf.vhd b/gbe2_ecp3/trb_net16_gbe_buf.vhd
index b97dfb88c373b4ccb4f84ea46d4ea2322dbdcd6f..ae1e38d47d0c4d994f5f85de9b29b21e1c27eedb 100755 (executable)
--- a/gbe2_ecp3/trb_net16_gbe_buf.vhd
+++ b/gbe2_ecp3/trb_net16_gbe_buf.vhd
@@ -600,12 +600,16 @@ signal insert_ttype, additional_hdr : std_logic;
 signal reset_dhcp : std_logic;
 signal dbg_hist, dbg_hist2 : hist_array;
 signal soft_gbe_reset, soft_rst, dhcp_done : std_logic;
-signal rst_ctr : std_logic_vector(25 downto 0);
+signal rst_ctr : std_logic_vector(24 downto 0);
+signal mac_reset : std_logic;
+signal global_reset : std_logic;
 
 begin
 
 stage_ctrl_regs <= STAGE_CTRL_REGS_IN;
 
+global_reset <= not GSR_N;
+
 -- gk 23.04.10
 LED_PACKET_SENT_OUT <= '0'; --timeout_noticed; --pc_ready;
 LED_AN_DONE_N_OUT   <= '0'; --not link_ok; --not pcs_an_complete;
@@ -616,26 +620,14 @@ fc_ttl              <= x"ff";
 
 --reset_dhcp <= not GSR_N;
 
-
-process(CLK)
-begin
-       if rising_edge(CLK) then
-               if (GSR_N = '0') then
-                       rst_ctr <= (others => '0');
-               else 
-                       rst_ctr <= rst_ctr + x"1";
-               end if; 
-       end if;
-end process;
-
-soft_gbe_reset <= '1' when soft_rst = '1' or (dhcp_done = '0' and rst_ctr(25) = '1') else '0';
+--soft_gbe_reset <= '1' when soft_rst = '1' or (dhcp_done = '0' and rst_ctr(24) = '1') else '0';
 
 MAIN_CONTROL : trb_net16_gbe_main_control
   port map(
          CLK                   => CLK,
          CLK_125               => serdes_clk_125,
-         RESET                 => RESET,
-         RESET_FOR_DHCP => soft_gbe_reset, --'0', --reset_dhcp,
+         RESET                 => global_reset, --RESET,
+         RESET_FOR_DHCP => global_reset, --'0', --soft_gbe_reset, --'0', --reset_dhcp,
 
          MC_LINK_OK_OUT        => link_ok,
          MC_RESET_LINK_IN      => '0',
@@ -758,7 +750,7 @@ MAIN_CONTROL : trb_net16_gbe_main_control
 TRANSMIT_CONTROLLER : trb_net16_gbe_transmit_control2
 port map(
        CLK                     => CLK,
-       RESET                   => RESET,
+       RESET                   => global_reset, --RESET,
 
 -- signal to/from main controller
        TC_DATAREADY_IN        => mc_transmit_ctrl,
@@ -805,7 +797,7 @@ setup_imp_gen : if (DO_SIMULATION = 0) generate
 SETUP : gbe_setup
 port map(
        CLK                         => CLK,  
-       RESET                       => RESET,
+       RESET                       => global_reset, --RESET,
 
        -- interface to regio bus
        BUS_ADDR_IN                 => BUS_ADDR_IN,     
@@ -858,7 +850,7 @@ end generate;
 FRAME_CONSTRUCTOR: trb_net16_gbe_frame_constr
 port map( 
        -- ports for user logic
-       RESET                           => RESET,
+       RESET                           => global_reset, --RESET,
        CLK                                 => CLK,
        LINK_OK_IN                      => '1', --link_ok,
        --
@@ -901,7 +893,7 @@ port map(
 RECEIVE_CONTROLLER : trb_net16_gbe_receive_control
 port map(
        CLK                     => CLK,
-       RESET                   => RESET,
+       RESET                   => global_reset, --RESET,
 
 -- signals to/from frame_receiver
        RC_DATA_IN              => fr_q,
@@ -946,7 +938,7 @@ dbg_q(15 downto 9) <= (others  => '0');
 FRAME_TRANSMITTER: trb_net16_gbe_frame_trans
 port map( 
        CLK                             => CLK,
-       RESET                           => RESET,
+       RESET                           => global_reset, --RESET,
        LINK_OK_IN                      => link_ok, --pcs_an_complete,  -- gk 03.08.10  -- gk 30.09.10
        TX_MAC_CLK                      => serdes_clk_125,
        TX_EMPTY_IN                     => ft_tx_empty,
@@ -975,7 +967,7 @@ port map(
   FRAME_RECEIVER : trb_net16_gbe_frame_receiver
   port map(
          CLK                   => CLK,
-         RESET                 => RESET,
+         RESET                 => global_reset, --RESET,
          LINK_OK_IN            => link_ok,
          ALLOW_RX_IN           => allow_rx,
          RX_MAC_CLK            => serdes_rx_clk, --serdes_clk_125,
@@ -1046,6 +1038,7 @@ imp_gen: if (DO_SIMULATION = 0) generate
                end if;
        end process TIMEOUT_NOTICED_PROC;
        
+       mac_reset <= not RESET;
        
        -- MAC part
        MAC: tsmac35 --tsmac36 --tsmac35
@@ -1153,7 +1146,7 @@ imp_gen: if (DO_SIMULATION = 0) generate
                        USE_125MHZ_EXTCLK               => 0
                )
                port map(
-                       RESET                           => soft_gbe_reset, --RESET,
+                       RESET                           => global_reset, --soft_gbe_reset, --RESET,
                        GSR_N                           => GSR_N,
                        CLK_125_OUT                     => serdes_clk_125,
                        CLK_125_RX_OUT                  => serdes_rx_clk, --open,
@@ -1203,7 +1196,7 @@ imp_gen: if (DO_SIMULATION = 0) generate
                        USE_125MHZ_EXTCLK               => 1
                )
                port map(
-                       RESET                           => soft_gbe_reset, --RESET,
+                       RESET                           => global_reset, --soft_gbe_reset, --RESET,
                        GSR_N                           => GSR_N,
                        CLK_125_OUT                     => serdes_clk_125,
                        CLK_125_RX_OUT                  => serdes_rx_clk,
@@ -1341,7 +1334,12 @@ sim_gen: if (DO_SIMULATION = 1) generate
        SFP_TXD_N_OUT                 <= '0';
        SFP_TXDIS_OUT                 <= '0';
        
-
+               mac_rxd <= MAC_RXD_IN;
+               mac_rx_eof <= MAC_RX_EOF_IN;
+               mac_rx_en <= MAC_RX_EN_IN;
+               
+               serdes_rx_clk <= TEST_CLK;
+               
 end generate sim_gen;
 
 

diff --git a/gbe2_ecp3/trb_net16_gbe_event_constr.vhd b/gbe2_ecp3/trb_net16_gbe_event_constr.vhd
index 7dd0d647b1fc173ea63822c85d6de47cbc54a023..f4e774ca8e05f9a2a29eb68fac875c2135682c45 100644 (file)
--- a/gbe2_ecp3/trb_net16_gbe_event_constr.vhd
+++ b/gbe2_ecp3/trb_net16_gbe_event_constr.vhd
@@ -241,12 +241,14 @@ end process SHF_Q_PROC;
 
 SAVE_SUB_HDR_MACHINE_PROC : process(CLK)
 begin
-       if rising_edge(CLK) then
-               if (RESET = '1') then
-                       save_sub_hdr_current_state <= IDLE;
-               else
+       if RESET = '1' then
+               save_sub_hdr_current_state <= IDLE;
+       elsif rising_edge(CLK) then
+--             if (RESET = '1') then
+--                     save_sub_hdr_current_state <= IDLE;
+--             else
                        save_sub_hdr_current_state <= save_sub_hdr_next_state;
-               end if;
+--             end if;
        end if;
 end process SAVE_SUB_HDR_MACHINE_PROC;
 
@@ -482,12 +484,14 @@ end process;
 
 LOAD_MACHINE_PROC : process(CLK) is
 begin
-       if rising_edge(CLK) then
-               if (RESET = '1') then
-                       load_current_state <= IDLE;
-               else
+       if RESET = '1' then
+               load_current_state <= IDLE;
+       elsif rising_edge(CLK) then
+--             if (RESET = '1') then
+--                     load_current_state <= IDLE;
+--             else
                        load_current_state <= load_next_state;
-               end if;
+--             end if;
        end if;
 end process LOAD_MACHINE_PROC;
 

diff --git a/gbe2_ecp3/trb_net16_gbe_frame_constr.vhd b/gbe2_ecp3/trb_net16_gbe_frame_constr.vhd
index fa866ee4b333f8de1011d6b93585dd92d9ec90b5..00f289fe9f4fb93fd42be883cb9ebb4538e751e5 100755 (executable)
--- a/gbe2_ecp3/trb_net16_gbe_frame_constr.vhd
+++ b/gbe2_ecp3/trb_net16_gbe_frame_constr.vhd
@@ -245,12 +245,14 @@ end process ipCsProc;
 \r
 constructMachineProc: process( CLK )\r
 begin\r
-       if( rising_edge(CLK) ) then\r
-               if( RESET = '1' ) then\r
-                       constructCurrentState <= IDLE;\r
-               else\r
+       if RESET = '1' then\r
+               constructCurrentState <= IDLE;\r
+       elsif( rising_edge(CLK) ) then\r
+--             if( RESET = '1' ) then\r
+--                     constructCurrentState <= IDLE;\r
+--             else\r
                        constructCurrentState <= constructNextState;\r
-               end if;\r
+--             end if;\r
        end if;\r
 end process constructMachineProc;\r
 \r
@@ -522,8 +524,10 @@ end process;
 \r
 transmitMachineProc: process( RD_CLK )\r
 begin\r
-       if( rising_edge(RD_CLK) ) then\r
-               if( RESET = '1' ) or (link_ok_125 = '0') then  -- gk 01.10.10\r
+       if RESET = '1' then\r
+               transmitCurrentState <= T_IDLE;\r
+       elsif( rising_edge(RD_CLK) ) then\r
+               if (link_ok_125 = '0') then  -- gk 01.10.10\r
                        transmitCurrentState <= T_IDLE;\r
                else\r
                        transmitCurrentState <= transmitNextState;\r

diff --git a/gbe2_ecp3/trb_net16_gbe_frame_receiver.vhd b/gbe2_ecp3/trb_net16_gbe_frame_receiver.vhd
index 6f307f5df394879fa8cb14143c95179b29a2472f..cd0c724b92853283f34b74b66b5d25c3f52d9643 100644 (file)
--- a/gbe2_ecp3/trb_net16_gbe_frame_receiver.vhd
+++ b/gbe2_ecp3/trb_net16_gbe_frame_receiver.vhd
@@ -125,7 +125,7 @@ begin
 NEW_FRAME_PROC : process(RX_MAC_CLK)
 begin
        if rising_edge(RX_MAC_CLK) then
-               if (RESET = '1') or (MAC_RX_EOF_IN = '1') then
+               if (LINK_OK_IN = '0' or MAC_RX_EOF_IN = '1') then
                        new_frame <= '0';
                        new_frame_lock <= '0';
                elsif (new_frame_lock = '0') and (MAC_RX_EN_IN = '1') then
@@ -133,6 +133,7 @@ begin
                        new_frame_lock <= '1';
                else
                        new_frame <= '0';
+                       new_frame_lock <= new_frame_lock;
                end if;
        end if;
 end process NEW_FRAME_PROC;
@@ -140,12 +141,14 @@ end process NEW_FRAME_PROC;
 
 FILTER_MACHINE_PROC : process(RX_MAC_CLK)
 begin
-       if rising_edge(RX_MAC_CLK) then
-               if (RESET = '1') then
-                       filter_current_state <= IDLE;
-               else
+       if RESET = '1' then
+               filter_current_state <= IDLE;
+       elsif rising_edge(RX_MAC_CLK) then
+--             if (RESET = '1') then
+--                     filter_current_state <= IDLE;
+--             else
                        filter_current_state <= filter_next_state;
-               end if;
+--             end if;
        end if;
 end process FILTER_MACHINE_PROC;
 

diff --git a/gbe2_ecp3/trb_net16_gbe_frame_trans.vhd b/gbe2_ecp3/trb_net16_gbe_frame_trans.vhd
index 07d3df2567ff4eaf9c69d65f2aa7aa7e583904cb..00dfd78542bed38eb49cff9ef789a2ae5bcd833f 100755 (executable)
--- a/gbe2_ecp3/trb_net16_gbe_frame_trans.vhd
+++ b/gbe2_ecp3/trb_net16_gbe_frame_trans.vhd
@@ -113,8 +113,10 @@ debug(63 downto 32) <= (others => '0');
 \r
 TransmitStateMachineProc : process (TX_MAC_CLK)\r
 begin\r
-       if rising_edge(TX_MAC_CLK) then\r
-               if (RESET = '1') or (LINK_OK_IN = '0') then -- gk 01.10.10\r
+       if RESET = '1' then\r
+               transmitCurrentState <= T_IDLE;\r
+       elsif rising_edge(TX_MAC_CLK) then\r
+               if (LINK_OK_IN = '0') then -- gk 01.10.10\r
                        transmitCurrentState <= T_IDLE;\r
                else\r
                        transmitCurrentState <= transmitNextState;\r

diff --git a/gbe2_ecp3/trb_net16_gbe_ipu_interface.vhd b/gbe2_ecp3/trb_net16_gbe_ipu_interface.vhd
index 219e3cbac9d3d4a1598699e9723f5f26181f7a45..a7ff5d4f4b007004567ed7fd1ac254356b202c9f 100644 (file)
--- a/gbe2_ecp3/trb_net16_gbe_ipu_interface.vhd
+++ b/gbe2_ecp3/trb_net16_gbe_ipu_interface.vhd
@@ -106,12 +106,14 @@ begin
 
 SAVE_MACHINE_PROC : process(CLK_IPU)
 begin
-       if rising_edge(CLK_IPU) then
-               if (RESET = '1') then
+       if RESET = '1' then
                        save_current_state <= IDLE;
-               else
+       elsif rising_edge(CLK_IPU) then
+--             if (RESET = '1') then
+--                     save_current_state <= IDLE;
+--             else
                        save_current_state <= save_next_state;
-               end if;
+--             end if;
        end if;
 end process SAVE_MACHINE_PROC;
 
@@ -399,12 +401,14 @@ end process PC_DATA_PROC;
 
 LOAD_MACHINE_PROC : process(CLK_GBE)
 begin
-       if rising_edge(CLK_GBE) then
-               if (RESET = '1') then
-                       load_current_state <= IDLE;
-               else
+       if RESET = '1' then
+               load_current_state <= IDLE;
+       elsif rising_edge(CLK_GBE) then
+--             if (RESET = '1') then
+--                     load_current_state <= IDLE;
+--             else
                        load_current_state <= load_next_state;
-               end if;
+--             end if;
        end if;
 end process LOAD_MACHINE_PROC;
 

diff --git a/gbe2_ecp3/trb_net16_gbe_mac_control.vhd b/gbe2_ecp3/trb_net16_gbe_mac_control.vhd
index d05ec4640f1db288ef4ff3885b8ebd0343ddd15b..5a9a60783ee4db1d814189811ef5d01485714ed4 100644 (file)
--- a/gbe2_ecp3/trb_net16_gbe_mac_control.vhd
+++ b/gbe2_ecp3/trb_net16_gbe_mac_control.vhd
@@ -88,12 +88,14 @@ reg_tx_rx_ctrl1(0)           <= MC_PROMISC_IN; -- promiscuous mode
 
 MAC_CONF_MACHINE_PROC : process(CLK)
 begin
-  if rising_edge(CLK) then
-    if (RESET = '1') then
-      mac_conf_current_state <= IDLE;
-    else
+       if RESET = '1' then
+               mac_conf_current_state <= IDLE;
+  elsif rising_edge(CLK) then
+--    if (RESET = '1') then
+--      mac_conf_current_state <= IDLE;
+--    else
       mac_conf_current_state <= mac_conf_next_state;
-    end if;
+--    end if;
   end if;
 end process MAC_CONF_MACHINE_PROC;
 

diff --git a/gbe2_ecp3/trb_net16_gbe_main_control.vhd b/gbe2_ecp3/trb_net16_gbe_main_control.vhd
index 1bc971cbed4640bee6096a73a2f0a201aa7b5972..261e3d048c77aa08ff2a68a34f585c2ee31fab54 100644 (file)
--- a/gbe2_ecp3/trb_net16_gbe_main_control.vhd
+++ b/gbe2_ecp3/trb_net16_gbe_main_control.vhd
@@ -159,7 +159,7 @@ signal tsm_hcs_n                            : std_logic;
 signal tsm_hwrite_n                         : std_logic;
 signal tsm_hread_n                          : std_logic;
 
-type link_states is (ACTIVE, INACTIVE, ENABLE_MAC, TIMEOUT, FINALIZE, WAIT_FOR_BOOT, GET_ADDRESS);
+type link_states is (INACTIVE, ACTIVE, ENABLE_MAC, TIMEOUT, FINALIZE, WAIT_FOR_BOOT, GET_ADDRESS);
 signal link_current_state, link_next_state : link_states;
 attribute syn_encoding of link_current_state : signal is "onehot";
 
@@ -380,12 +380,14 @@ end process SYNC_PROC;
 
 REDIRECT_MACHINE_PROC : process(CLK)
 begin
-       if rising_edge(CLK) then
-               if (RESET = '1') then
+       if RESET = '1' then
                        redirect_current_state <= IDLE;
-               else
+       elsif rising_edge(CLK) then
+--             if (RESET = '1') then
+--                     redirect_current_state <= IDLE;
+--             else
                        redirect_current_state <= redirect_next_state;
-               end if;
+--             end if;
        end if;
 end process REDIRECT_MACHINE_PROC;
 
@@ -517,12 +519,14 @@ end process FIRST_BYTE_PROC;
 
 FLOW_MACHINE_PROC : process(CLK)
 begin
-  if rising_edge(CLK) then
-    if (RESET = '1') then
-      flow_current_state <= IDLE;
-    else
+       if RESET = '1' then
+                       flow_current_state <= IDLE;
+  elsif rising_edge(CLK) then
+--    if (RESET = '1') then
+--      flow_current_state <= IDLE;
+--    else
       flow_current_state <= flow_next_state;
-    end if;
+--    end if;
   end if;
 end process FLOW_MACHINE_PROC;
 
@@ -584,32 +588,26 @@ end process;
 
 LINK_STATE_MACHINE_PROC : process(CLK)
 begin
-       if rising_edge(CLK) then
-               --if (RESET = '1') then
-               if (RESET_FOR_DHCP = '1') then
-                       if (g_SIMULATE = 0) then
-                               link_current_state <= INACTIVE;
-                       else
-                               link_current_state <= FINALIZE; --ACTIVE; --GET_ADDRESS; --ACTIVE;
-                       end if;
-               else
+       if RESET = '1' then
+               link_current_state <= INACTIVE;
+       elsif rising_edge(CLK) then
+--             --if (RESET = '1') then
+--             if (RESET_FOR_DHCP = '1') then
+--                     if (g_SIMULATE = 0) then
+--                             link_current_state <= INACTIVE;
+--                     else
+--                             link_current_state <= FINALIZE; --ACTIVE; --GET_ADDRESS; --ACTIVE;
+--                     end if;
+--             else
                        link_current_state <= link_next_state;
-               end if;
+--             end if;
        end if;
 end process;
 
 LINK_STATE_MACHINE : process(link_current_state, dhcp_done, wait_ctr, PCS_AN_COMPLETE_IN, tsm_ready, link_ok_timeout_ctr)
 begin
        case link_current_state is
-
-               when ACTIVE =>
-                       link_state <= x"1";
-                       if (PCS_AN_COMPLETE_IN = '0') then
-                               link_next_state <= INACTIVE;
-                       else
-                               link_next_state <= ACTIVE;
-                       end if;
-
+               
                when INACTIVE =>
                        link_state <= x"2";
                        if (PCS_AN_COMPLETE_IN = '1') then
@@ -617,7 +615,7 @@ begin
                        else
                                link_next_state <= INACTIVE;
                        end if;
-
+                       
                when TIMEOUT =>
                        link_state <= x"3";
                        if (PCS_AN_COMPLETE_IN = '0') then
@@ -653,7 +651,7 @@ begin
                        if (PCS_AN_COMPLETE_IN = '0') then
                                link_next_state <= INACTIVE;
                        else
-                               if (wait_ctr = x"0010_0000") then
+                               if (wait_ctr = x"0000_1000") then
                                        link_next_state <= GET_ADDRESS;
                                else
                                        link_next_state <= WAIT_FOR_BOOT;
@@ -671,6 +669,14 @@ begin
                                        link_next_state <= GET_ADDRESS;
                                end if;
                        end if;
+                       
+               when ACTIVE =>
+                       link_state <= x"1";
+                       if (PCS_AN_COMPLETE_IN = '0') then
+                               link_next_state <= INACTIVE;
+                       else
+                               link_next_state <= ACTIVE;
+                       end if;
 
        end case;
 end process LINK_STATE_MACHINE;

diff --git a/gbe2_ecp3/trb_net16_gbe_packet_constr.vhd b/gbe2_ecp3/trb_net16_gbe_packet_constr.vhd
index dd2b4c198126d9ba72a2b8c1d471a951241ece4a..c552a6199eee8a7aae4a0034ba955d9b10939454 100755 (executable)
--- a/gbe2_ecp3/trb_net16_gbe_packet_constr.vhd
+++ b/gbe2_ecp3/trb_net16_gbe_packet_constr.vhd
@@ -239,12 +239,14 @@ end process dfQProc;
 -- Construction state machine
 constructMachineProc : process(CLK)
 begin
-       if rising_edge(CLK) then
-               if (RESET = '1') then
-                       constructCurrentState <= CIDLE;
-               else
+       if RESET = '1' then
+               constructCurrentState <= CIDLE;
+       elsif rising_edge(CLK) then
+--             if (RESET = '1') then
+--                     constructCurrentState <= CIDLE;
+--             else
                        constructCurrentState <= constructNextState;
-               end if;
+--             end if;
        end if;
 end process constructMachineProc;
 
@@ -311,12 +313,14 @@ end process queueSizeProc;
 
 loadMachineProc : process(CLK)
 begin
-       if rising_edge(CLK) then
-               if (RESET = '1') then
+       if RESET = '1' then
                        loadCurrentState <= LIDLE;
-               else
+       elsif rising_edge(CLK) then
+--             if (RESET = '1') then
+--                     loadCurrentState <= LIDLE;
+--             else
                        loadCurrentState <= loadNextState;
-               end if;
+--             end if;
        end if;
 end process loadMachineProc;
 
@@ -940,12 +944,14 @@ end process shfDataProc;
 
 saveSubMachineProc : process(CLK)
 begin
-       if rising_edge(CLK) then
-               if (RESET = '1') then
-                       saveSubCurrentState <= SIDLE;
-               else
+       if RESET = '1' then
+               saveSubCurrentState <= SIDLE;
+       elsif rising_edge(CLK) then
+--             if (RESET = '1') then
+--                     saveSubCurrentState <= SIDLE;
+--             else
                        saveSubCurrentState <= saveSubNextState;
-               end if;
+--             end if;
        end if;
 end process saveSubMachineProc;
 

diff --git a/gbe2_ecp3/trb_net16_gbe_protocol_selector.vhd b/gbe2_ecp3/trb_net16_gbe_protocol_selector.vhd
index 31a2a24bbf2e896cea61f56be3c549752641fe8a..94a91355ceb0b1eac53a0cc34641ab064f09d4e2 100644 (file)
--- a/gbe2_ecp3/trb_net16_gbe_protocol_selector.vhd
+++ b/gbe2_ecp3/trb_net16_gbe_protocol_selector.vhd
@@ -556,12 +556,14 @@ PS_BUSY_OUT <= busy;
 
 SELECT_MACHINE_PROC : process(CLK)
 begin
-       if rising_edge(CLK) then
-               if (RESET = '1') then
-                       select_current_state <= IDLE;
-               else
+       if RESET = '1' then
+               select_current_state <= IDLE;
+       elsif rising_edge(CLK) then
+--             if (RESET = '1') then
+--                     select_current_state <= IDLE;
+--             else
                        select_current_state <= select_next_state;
-               end if;
+--             end if;
        end if;
 end process SELECT_MACHINE_PROC;
 

diff --git a/gbe2_ecp3/trb_net16_gbe_receive_control.vhd b/gbe2_ecp3/trb_net16_gbe_receive_control.vhd
index 08d45349e6b5870fbaec1f8ef7319f4c89aa1063..4644a57e2f3fbdeb562520c059a6f21967ac047b 100644 (file)
--- a/gbe2_ecp3/trb_net16_gbe_receive_control.vhd
+++ b/gbe2_ecp3/trb_net16_gbe_receive_control.vhd
@@ -121,12 +121,14 @@ RC_FRAME_PROTO_OUT <= proto_code;  -- no more ones as the incorrect value, last
 
 LOAD_MACHINE_PROC : process(CLK)
 begin
-  if rising_edge(CLK) then
-    if (RESET = '1') then
-      load_current_state <= IDLE;
-    else
+       if RESET = '1' then
+               load_current_state <= IDLE;
+  elsif rising_edge(CLK) then
+--    if (RESET = '1') then
+--      load_current_state <= IDLE;
+--    else
       load_current_state <= load_next_state;
-    end if;
+--    end if;
   end if;
 end process LOAD_MACHINE_PROC;
 

diff --git a/gbe2_ecp3/trb_net16_gbe_response_constructor_ARP.vhd b/gbe2_ecp3/trb_net16_gbe_response_constructor_ARP.vhd
index 42917529c064dfe33ebae19db27ee810419d07ef..8154f9f1d90da6722bafc503c403053fccd6ee62 100644 (file)
--- a/gbe2_ecp3/trb_net16_gbe_response_constructor_ARP.vhd
+++ b/gbe2_ecp3/trb_net16_gbe_response_constructor_ARP.vhd
@@ -110,12 +110,14 @@ values(223 downto 192) <= saved_sender_ip;  -- target ip
 
 DISSECT_MACHINE_PROC : process(CLK)
 begin
-       if rising_edge(CLK) then
-               if (RESET = '1') then
-                       dissect_current_state <= IDLE;
-               else
+       if RESET = '1' then
+               dissect_current_state <= IDLE;
+       elsif rising_edge(CLK) then
+--             if (RESET = '1') then
+--                     dissect_current_state <= IDLE;
+--             else
                        dissect_current_state <= dissect_next_state;
-               end if;
+--             end if;
        end if;
 end process DISSECT_MACHINE_PROC;
 

diff --git a/gbe2_ecp3/trb_net16_gbe_response_constructor_DHCP.vhd b/gbe2_ecp3/trb_net16_gbe_response_constructor_DHCP.vhd
index b8af231bdf82765bfe37b646bd2af3bf6885e337..ab9edc17950374df4a5572c027e3fbfd309e657b 100644 (file)
--- a/gbe2_ecp3/trb_net16_gbe_response_constructor_DHCP.vhd
+++ b/gbe2_ecp3/trb_net16_gbe_response_constructor_DHCP.vhd
@@ -175,12 +175,14 @@ end process SAVE_SERVER_ADDR_PROC;
 
 MAIN_MACHINE_PROC : process(CLK)
 begin
-       if rising_edge(CLK) then
-               if (RESET = '1') then
-                       main_current_state <= BOOTING;
-               else
+       if RESET = '1' then
+               main_current_state <= BOOTING;
+       elsif rising_edge(CLK) then
+--             if (RESET = '1') then
+--                     main_current_state <= BOOTING;
+--             else
                        main_current_state <= main_next_state;
-               end if;
+--             end if;
        end if;
 end process MAIN_MACHINE_PROC;
 
@@ -439,8 +441,10 @@ end process SAVE_VALUES_PROC;
 
 CONSTRUCT_MACHINE_PROC : process(CLK)
 begin
-       if rising_edge(CLK) then
-               if (RESET = '1') or (main_current_state = BOOTING) then
+       if RESET = '1' then
+                       construct_current_state <= IDLE;
+       elsif rising_edge(CLK) then
+               if (main_current_state = BOOTING) then
                        construct_current_state <= IDLE;
                else
                        construct_current_state <= construct_next_state;

diff --git a/gbe2_ecp3/trb_net16_gbe_response_constructor_Ping.vhd b/gbe2_ecp3/trb_net16_gbe_response_constructor_Ping.vhd
index 9cad4b478a6b6b021cf8f06672a4b5043a8c7799..203a91ecf0b9d3e012a5b2ae9f2dccc880170b64 100644 (file)
--- a/gbe2_ecp3/trb_net16_gbe_response_constructor_Ping.vhd
+++ b/gbe2_ecp3/trb_net16_gbe_response_constructor_Ping.vhd
@@ -109,12 +109,14 @@ begin
 
 DISSECT_MACHINE_PROC : process(CLK)
 begin
-       if rising_edge(CLK) then
-               if (RESET = '1') then
-                       dissect_current_state <= IDLE;
-               else
+       if RESET = '1' then
+               dissect_current_state <= IDLE;
+       elsif rising_edge(CLK) then
+--             if (RESET = '1') then
+--                     dissect_current_state <= IDLE;
+--             else
                        dissect_current_state <= dissect_next_state;
-               end if;
+--             end if;
        end if;
 end process DISSECT_MACHINE_PROC;
 

diff --git a/gbe2_ecp3/trb_net16_gbe_response_constructor_SCTRL.vhd b/gbe2_ecp3/trb_net16_gbe_response_constructor_SCTRL.vhd
index 2b49f3cecdb962e27beb2f02177dbc509ad80f4c..98719cae7f4fc386b1f2e2c9c0a3f03a259ca098 100644 (file)
--- a/gbe2_ecp3/trb_net16_gbe_response_constructor_SCTRL.vhd
+++ b/gbe2_ecp3/trb_net16_gbe_response_constructor_SCTRL.vhd
@@ -477,16 +477,18 @@ TC_FRAME_SIZE_OUT   <= tx_data_ctr;
 
 DISSECT_MACHINE_PROC : process(CLK)
 begin
-       if rising_edge(CLK) then
-               if (RESET = '1') then
-                       if (g_SIMULATE = 0) then
-                               dissect_current_state <= IDLE;
-                       else
-                               dissect_current_state <= WAIT_FOR_RESPONSE;
-                       end if;
-               else
+       if RESET = '1' then
+               dissect_current_state <= IDLE;
+       elsif rising_edge(CLK) then
+--             if (RESET = '1') then
+--                     if (g_SIMULATE = 0) then
+--                             dissect_current_state <= IDLE;
+--                     else
+--                             dissect_current_state <= WAIT_FOR_RESPONSE;
+--                     end if;
+--             else
                        dissect_current_state <= dissect_next_state;
-               end if;
+--             end if;
        end if;
 end process DISSECT_MACHINE_PROC;
 

diff --git a/gbe2_ecp3/trb_net16_gbe_response_constructor_TrbNetData.vhd b/gbe2_ecp3/trb_net16_gbe_response_constructor_TrbNetData.vhd
index 66ce43a4393bdd6393628d8baf738a2e206912c1..fb7e5cdd6c36d055acdae42591d096eb3503f622 100644 (file)
--- a/gbe2_ecp3/trb_net16_gbe_response_constructor_TrbNetData.vhd
+++ b/gbe2_ecp3/trb_net16_gbe_response_constructor_TrbNetData.vhd
@@ -286,12 +286,14 @@ tc_rd_en <= '1' when PS_SELECTED_IN = '1' and TC_RD_EN_IN = '1' else '0';
 
 DISSECT_MACHINE_PROC : process(CLK)
 begin
-       if rising_edge(CLK) then
-               if (RESET = '1') then
-                       dissect_current_state <= IDLE;
-               else
+       if RESET = '1' then
+               dissect_current_state <= IDLE;
+       elsif rising_edge(CLK) then
+--             if (RESET = '1') then
+--                     dissect_current_state <= IDLE;
+--             else
                        dissect_current_state <= dissect_next_state;
-               end if;
+--             end if;
        end if;
 end process DISSECT_MACHINE_PROC;
 

diff --git a/gbe2_ecp3/trb_net16_gbe_transmit_control2.vhd b/gbe2_ecp3/trb_net16_gbe_transmit_control2.vhd
index e7501304c3d613d980e767394364f859cb7afb27..1443250d4b48503f926cda67b43c46bb98154cf2 100644 (file)
--- a/gbe2_ecp3/trb_net16_gbe_transmit_control2.vhd
+++ b/gbe2_ecp3/trb_net16_gbe_transmit_control2.vhd
@@ -80,12 +80,14 @@ begin
 
 TRANSMIT_MACHINE_PROC : process(CLK)
 begin
-       if rising_edge(CLK) then
-               if (RESET = '1') then
-                       transmit_current_state <= IDLE;
-               else
+       if RESET = '1' then
+               transmit_current_state <= IDLE;
+       elsif rising_edge(CLK) then
+--             if (RESET = '1') then
+--                     transmit_current_state <= IDLE;
+--             else
                        transmit_current_state <= transmit_next_state;
-               end if;
+--             end if;
        end if;
 end process TRANSMIT_MACHINE_PROC;
 

diff --git a/gbe2_ecp3/trb_net16_med_ecp_sfp_gbe_8b.vhd b/gbe2_ecp3/trb_net16_med_ecp_sfp_gbe_8b.vhd
index 37b975c2cb8aecbea0290ceff89e86f61a352e9b..13141e636a9c2fee42c391c0ee96fefae4ea0a44 100755 (executable)
--- a/gbe2_ecp3/trb_net16_med_ecp_sfp_gbe_8b.vhd
+++ b/gbe2_ecp3/trb_net16_med_ecp_sfp_gbe_8b.vhd
@@ -744,7 +744,7 @@ buf_stat_debug(11 downto 0)  <= sd_rx_debug(11 downto 0);
  \r
  SGMII_GBE_PCS : sgmii_gbe_pcs35 --sgmii_gbe_pcs36 --sgmii_gbe_pcs35\r
  port map(\r
-       rst_n                           => GSR_N,\r
+       rst_n                           => rst_n, --GSR_N,\r
        signal_detect                   => signal_detected,\r
        gbe_mode                        => '1',\r
        sgmii_mode                      => '0',\r