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+The CTS has two 34 pin pin-headers for PECL signals, fed by three outputs of the FPGA, each going through one 1-to-10 fan-out. This gives 15 signals on each pin-header, 10 from the first resp. the third output plus 5 from the second output.
+Additionally there are 16 LVDS lines on one pin-header. 
+
+Trigger cables to TOF and MDC3/4 as well as RPC, Shower and Forward Wall are transported using one 34 pin flat cable from the CTS to the front right (approx. 60 ns delay) resp. the rear right corner (83 ns) of the mainframe. From the front right corner there are two twisted pair wires going to each TOF sector, one pair used for TOF trigger, the other for MDC common stop.
+
+From the rear right corner there is a 20m Cat6 Ethernet cable (delay 105 ns) going to each sector of Shower and RPC plus two pais of twisted pair cable (80 ns delay) to Forward Wall. Veto and MDC1/2 are using twisted pair cables directly from the CTS using LVDS. RICH has a Cat7 Ethernet cables with all four wire pairs connecting CTS and RICH. 
+
+The delay of standard Ethernet cables has been measured to be 5.17 ns/m. The full setup is shown in figure \ref{trigger_cables}.
+
+\begin{figure}
+  \centering
+  \includegraphics[width=.9\textheight,angle=90]{triggercable.pdf}
+  \caption{Trigger Cables between CTS and detectors. Black times are delay requirements, red times are measured latencies.}
+  \label{trigger_cables}
+\end{figure}
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