]> jspc29.x-matter.uni-frankfurt.de Git - trb3.git/commitdiff
latest changes, JM
authorhadeshyp <hadeshyp>
Thu, 28 Mar 2013 18:08:07 +0000 (18:08 +0000)
committerhadeshyp <hadeshyp>
Thu, 28 Mar 2013 18:08:07 +0000 (18:08 +0000)
13 files changed:
soda_source/compile_periph_frankfurt.pl
soda_source/trb3_periph_sodasource.prj
soda_source/trb3_periph_sodasource.vhd
soda_source/version.vhd
syncmode/compile_central_frankfurt.pl
syncmode/trb3_central.vhd
trb3_gbe/config.vhd
trb3_gbe/trb3_central.p2t
trb3_gbe/trb3_central.prj
trb3_gbe/trb3_central_constraints.lpf
wasa/compile_padiwa_frankfurt.pl
wasa/panda_dirc_wasa.ldf [new file with mode: 0644]
wasa/panda_dirc_wasa.p2t

index 1cc699eb2bc588ec94bdd44ecb01999eb3d84bc9..7b30f33984cd374e11f11cad95daa80211c4290d 100755 (executable)
@@ -10,7 +10,7 @@ use strict;
 #Settings for this project
 my $TOPNAME                      = "trb3_periph_sodasource";  #Name of top-level entity
 my $lattice_path                 = '/d/jspc29/lattice/diamond/2.01';
-my $synplify_path                = '/d/jspc29/lattice/synplify/G-2012.09-SP1/';
+my $synplify_path                = '/d/jspc29/lattice/synplify/F-2012.03-SP1/';
 my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de";
 #my $lm_license_file_for_par      = "1702\@hadeb05.gsi.de";
 my $lm_license_file_for_par      = "1710\@cronos.e12.physik.tu-muenchen.de";
index 60b17fe20b3513467d58599fdff2c7044e8d2a52..d6ba843c70ead38e12a072a51a17423296a3085a 100644 (file)
@@ -101,6 +101,7 @@ add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd"
 add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler.vhd"
 add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload.vhd"
 
 add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd"
 add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd"
@@ -142,6 +143,7 @@ add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_0.v
 add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync.vhd"
 
 add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_1_125_int.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd"
 
@@ -154,21 +156,21 @@ add_file -vhdl -lib "work" "../base/cores/pll_in200_out100.vhd"
 #Change path to tdc release also in compile script!
 ###############
 #add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/Adder_304.vhd"
-add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/bit_sync.vhd"
-add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/BusHandler.vhd"
-add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/Channel.vhd"
-add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/Channel_200.vhd"
-add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/Encoder_304_Bit.vhd"
-add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/FIFO_32x32_OutReg.vhd"
-add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/LogicAnalyser.vhd"
-add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/Readout.vhd"
-add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/Reference_Channel_200.vhd"
-add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/Reference_Channel.vhd"
-add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/ROM_encoder_3.vhd"
-add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/ROM_FIFO.vhd"
-add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/ShiftRegisterSISO.vhd"
-add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/TDC.vhd"
-add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/up_counter.vhd"
+#add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/bit_sync.vhd"
+#add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/BusHandler.vhd"
+#add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/Channel.vhd"
+#add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/Channel_200.vhd"
+#add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/Encoder_304_Bit.vhd"
+#add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/FIFO_32x32_OutReg.vhd"
+#add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/LogicAnalyser.vhd"
+#add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/Readout.vhd"
+#add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/Reference_Channel_200.vhd"
+#add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/Reference_Channel.vhd"
+#add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/ROM_encoder_3.vhd"
+#add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/ROM_FIFO.vhd"
+#add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/ShiftRegisterSISO.vhd"
+#add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/TDC.vhd"
+#add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/up_counter.vhd"
 
 add_file -vhdl -lib "work" "trb3_periph_sodasource.vhd"
 
index f5a02e3645a43ed53e58cbec04a9cca590575bd7..dbdbf6b16411b218c05bdf0fb255def4424373f8 100644 (file)
@@ -11,22 +11,22 @@ use work.version.all;
 
 entity trb3_periph_sodasource is
   generic(
-    SYNC_MODE : integer range 0 to 1 := c_NO   --use the RX clock for internal logic and transmission. Should be NO for soda tests!
+    SYNC_MODE : integer range 0 to 1 := c_NO;   --use the RX clock for internal logic and transmission. Should be NO for soda tests!
+    USE_125_MHZ : integer := c_YES
     );
   port(
     --Clocks
-    CLK_GPLL_LEFT  : in std_logic;      --Clock Manager 1/(2468), 125 MHz
+    CLK_GPLL_LEFT  : in std_logic;  --Clock Manager 1/(2468), 125 MHz
     CLK_GPLL_RIGHT : in std_logic;  --Clock Manager 2/(2468), 200 MHz  <-- MAIN CLOCK for FPGA
     CLK_PCLK_LEFT  : in std_logic;  --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
     CLK_PCLK_RIGHT : in std_logic;  --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
 
     --Trigger
-    TRIGGER_LEFT  : in std_logic;       --left side trigger input from fan-out
-    TRIGGER_RIGHT : in std_logic;       --right side trigger input from fan-out
-
+    --TRIGGER_LEFT  : in std_logic;       --left side trigger input from fan-out
+    --TRIGGER_RIGHT : in std_logic;       --right side trigger input from fan-out
     --Serdes Clocks - do not use
-    CLK_SERDES_INT_LEFT  : in  std_logic;  --Clock Manager 1/(1357), off, 125 MHz possible
-    CLK_SERDES_INT_RIGHT : in  std_logic;  --Clock Manager 2/(1357), 200 MHz, only in case of problems
+    --CLK_SERDES_INT_LEFT  : in  std_logic;  --Clock Manager 1/(1357), off, 125 MHz possible
+    --CLK_SERDES_INT_RIGHT : in  std_logic;  --Clock Manager 2/(1357), 200 MHz, only in case of problems
 
     --serdes I/O - connect as you like, no real use
     SERDES_ADDON_TX      : out std_logic_vector(15 downto 0);
@@ -44,10 +44,10 @@ entity trb3_periph_sodasource is
     SFP_MOD0   : in  std_logic_vector(6 downto 1);
     SFP_TXDIS  : out std_logic_vector(6 downto 1); 
     SFP_LOS    : in  std_logic_vector(6 downto 1);
---     SFP_MOD1   : inout std_logic_vector(6 downto 1); 
---     SFP_MOD2   : inout std_logic_vector(6 downto 1); 
---     SFP_RATESEL : out std_logic_vector(6 downto 1);
---     SFP_TXFAULT : in  std_logic_vector(6 downto 1);
+    --SFP_MOD1   : inout std_logic_vector(6 downto 1); 
+    --SFP_MOD2   : inout std_logic_vector(6 downto 1); 
+    --SFP_RATESEL : out std_logic_vector(6 downto 1);
+    --SFP_TXFAULT : in  std_logic_vector(6 downto 1);
 
     --Flash ROM & Reboot
     FLASH_CLK  : out   std_logic;
@@ -79,28 +79,20 @@ entity trb3_periph_sodasource is
   attribute syn_useioff of TEMPSENS      : signal is false;
   attribute syn_useioff of PROGRAMN      : signal is false;
   attribute syn_useioff of CODE_LINE     : signal is false;
-  attribute syn_useioff of TRIGGER_LEFT  : signal is false;
-  attribute syn_useioff of TRIGGER_RIGHT : signal is false;
   attribute syn_useioff of LED_LINKOK    : signal is false;
   attribute syn_useioff of LED_TX        : signal is false;
   attribute syn_useioff of LED_RX        : signal is false;
   attribute syn_useioff of SFP_MOD0      : signal is false;
   attribute syn_useioff of SFP_TXDIS     : signal is false;
   attribute syn_useioff of SFP_LOS       : signal is false;
+  attribute syn_useioff of TEST_LINE  : signal is false;
 
-  
   --important signals _with_ IO-FF
   attribute syn_useioff of FLASH_CLK  : signal is true;
   attribute syn_useioff of FLASH_CS   : signal is true;
   attribute syn_useioff of FLASH_DIN  : signal is true;
   attribute syn_useioff of FLASH_DOUT : signal is true;
   attribute syn_useioff of FPGA5_COMM : signal is true;
-  attribute syn_useioff of TEST_LINE  : signal is false;
---   attribute syn_useioff of DQLL       : signal is true;
---   attribute syn_useioff of DQUL       : signal is true;
---   attribute syn_useioff of DQLR       : signal is true;
---   attribute syn_useioff of DQUR       : signal is true;
---   attribute syn_useioff of SPARE_LINE : signal is true;
 
 
 end entity;
@@ -113,19 +105,21 @@ architecture trb3_periph_sodasource_arch of trb3_periph_sodasource is
   attribute syn_keep     : boolean;
   attribute syn_preserve : boolean;
 
+  constant USE_200_MHZ : integer := 1 - USE_125_MHZ;
+  
   --Clock / Reset
-  signal clk_100_i                : std_logic;  --clock for main logic, 100 MHz, via Clock Manager and internal PLL
-  signal clk_200_i                : std_logic;  --clock for logic at 200 MHz, via Clock Manager and bypassed PLL
+  signal clk_sys_i                : std_logic;  --clock for main logic, 100 MHz, via Clock Manager and internal PLL
+--   signal clk_200_i                : std_logic;  --clock for logic at 200 MHz, via Clock Manager and bypassed PLL
   signal pll_lock                 : std_logic;  --Internal PLL locked. E.g. used to reset all internal logic.
   signal clear_i                  : std_logic;
   signal reset_i                  : std_logic;
   signal GSR_N                    : std_logic;
   attribute syn_keep of GSR_N     : signal is true;
   attribute syn_preserve of GSR_N : signal is true;
-  signal clk_100_internal         : std_logic;
-  signal clk_200_internal         : std_logic;
-  signal rx_clock_100             : std_logic;
-  signal rx_clock_200             : std_logic;
+  signal clk_sys_internal         : std_logic;
+  signal clk_raw_internal         : std_logic;
+  signal rx_clock_half             : std_logic;
+  signal rx_clock_full             : std_logic;
   signal clk_tdc                  : std_logic;
   signal time_counter, time_counter2 : unsigned(31 downto 0);
   --Media Interface
@@ -142,31 +136,6 @@ architecture trb3_periph_sodasource_arch of trb3_periph_sodasource is
   signal med_dataready_in   : std_logic;
   signal med_read_in        : std_logic;
 
-  --LVL1 channel
-  signal timing_trg_received_i  : std_logic;
-  signal trg_data_valid_i       : std_logic;
-  signal trg_timing_valid_i     : std_logic;
-  signal trg_notiming_valid_i   : std_logic;
-  signal trg_invalid_i          : std_logic;
-  signal trg_type_i             : std_logic_vector(3 downto 0);
-  signal trg_number_i           : std_logic_vector(15 downto 0);
-  signal trg_code_i             : std_logic_vector(7 downto 0);
-  signal trg_information_i      : std_logic_vector(23 downto 0);
-  signal trg_int_number_i       : std_logic_vector(15 downto 0);
-  signal trg_multiple_trg_i     : std_logic;
-  signal trg_timeout_detected_i : std_logic;
-  signal trg_spurious_trg_i     : std_logic;
-  signal trg_missing_tmg_trg_i  : std_logic;
-  signal trg_spike_detected_i   : std_logic;
-
-  --Data channel
-  signal fee_trg_release_i    : std_logic;
-  signal fee_trg_statusbits_i : std_logic_vector(31 downto 0);
-  signal fee_data_i           : std_logic_vector(31 downto 0);
-  signal fee_data_write_i     : std_logic;
-  signal fee_data_finished_i  : std_logic;
-  signal fee_almost_full_i    : std_logic;
-
   --Slow Control channel
   signal common_stat_reg        : std_logic_vector(std_COMSTATREG*32-1 downto 0);
   signal common_ctrl_reg        : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
@@ -197,72 +166,15 @@ architecture trb3_periph_sodasource_arch of trb3_periph_sodasource is
   signal timer_ticks         : std_logic_vector(1 downto 0);
 
   --Flash
-  signal spictrl_read_en  : std_logic;
-  signal spictrl_write_en : std_logic;
-  signal spictrl_data_in  : std_logic_vector(31 downto 0);
-  signal spictrl_addr     : std_logic;
-  signal spictrl_data_out : std_logic_vector(31 downto 0);
-  signal spictrl_ack      : std_logic;
-  signal spictrl_busy     : std_logic;
-  signal spimem_read_en   : std_logic;
-  signal spimem_write_en  : std_logic;
-  signal spimem_data_in   : std_logic_vector(31 downto 0);
-  signal spimem_addr      : std_logic_vector(5 downto 0);
-  signal spimem_data_out  : std_logic_vector(31 downto 0);
-  signal spimem_ack       : std_logic;
-
-  signal dac_read_en  : std_logic;
-  signal dac_write_en : std_logic;
-  signal dac_data_in  : std_logic_vector(31 downto 0);
-  signal dac_addr     : std_logic_vector(4 downto 0);
-  signal dac_data_out : std_logic_vector(31 downto 0);
-  signal dac_ack      : std_logic;
-  signal dac_busy     : std_logic;
-
-  signal hitreg_read_en    : std_logic;
-  signal hitreg_write_en   : std_logic;
-  signal hitreg_data_in    : std_logic_vector(31 downto 0);
-  signal hitreg_addr       : std_logic_vector(6 downto 0);
-  signal hitreg_data_out   : std_logic_vector(31 downto 0);
-  signal hitreg_data_ready : std_logic;
-  signal hitreg_invalid    : std_logic;
-
-  signal srb_read_en    : std_logic;
-  signal srb_write_en   : std_logic;
-  signal srb_data_in    : std_logic_vector(31 downto 0);
-  signal srb_addr       : std_logic_vector(6 downto 0);
-  signal srb_data_out   : std_logic_vector(31 downto 0);
-  signal srb_data_ready : std_logic;
-  signal srb_invalid    : std_logic;
-
-  signal lhb_read_en    : std_logic;
-  signal lhb_write_en   : std_logic;
-  signal lhb_data_in    : std_logic_vector(31 downto 0);
-  signal lhb_addr       : std_logic_vector(6 downto 0);
-  signal lhb_data_out   : std_logic_vector(31 downto 0);
-  signal lhb_data_ready : std_logic;
-  signal lhb_invalid    : std_logic;
-
-  signal esb_read_en    : std_logic;
-  signal esb_write_en   : std_logic;
-  signal esb_data_in    : std_logic_vector(31 downto 0);
-  signal esb_addr       : std_logic_vector(6 downto 0);
-  signal esb_data_out   : std_logic_vector(31 downto 0);
-  signal esb_data_ready : std_logic;
-  signal esb_invalid    : std_logic;
-
-  signal fwb_read_en    : std_logic;
-  signal fwb_write_en   : std_logic;
-  signal fwb_data_in    : std_logic_vector(31 downto 0);
-  signal fwb_addr       : std_logic_vector(6 downto 0);
-  signal fwb_data_out   : std_logic_vector(31 downto 0);
-  signal fwb_data_ready : std_logic;
-  signal fwb_invalid    : std_logic;
-
-  signal spi_bram_addr : std_logic_vector(7 downto 0);
-  signal spi_bram_wr_d : std_logic_vector(7 downto 0);
-  signal spi_bram_rd_d : std_logic_vector(7 downto 0);
-  signal spi_bram_we   : std_logic;
+  signal spimem_read_en          : std_logic;
+  signal spimem_write_en         : std_logic;
+  signal spimem_data_in          : std_logic_vector(31 downto 0);
+  signal spimem_addr             : std_logic_vector(8 downto 0);
+  signal spimem_data_out         : std_logic_vector(31 downto 0);
+  signal spimem_dataready_out    : std_logic;
+  signal spimem_no_more_data_out : std_logic;
+  signal spimem_unknown_addr_out : std_logic;
+  signal spimem_write_ack_out    : std_logic;
 
   signal sci1_ack      : std_logic;
   signal sci1_write    : std_logic;
@@ -277,17 +189,12 @@ architecture trb3_periph_sodasource_arch of trb3_periph_sodasource is
   signal sci2_data_in  : std_logic_vector(7 downto 0);
   signal sci2_data_out : std_logic_vector(7 downto 0);
   signal sci2_addr     : std_logic_vector(8 downto 0);  
-  
-  signal padiwa_cs  : std_logic_vector(3 downto 0);
-  signal padiwa_sck : std_logic;
-  signal padiwa_sdi : std_logic;
-  signal padiwa_sdo : std_logic;
 
   --TDC
   signal hit_in_i : std_logic_vector(63 downto 0);
       
-  signal soda_rx_clock_100 : std_logic;
-  signal soda_rx_clock_200 : std_logic;
+  signal soda_rx_clock_half : std_logic;
+  signal soda_rx_clock_full : std_logic;
   signal tx_dlm_i          : std_logic;
   signal rx_dlm_i          : std_logic;
   signal tx_dlm_word       : std_logic_vector(7 downto 0);
@@ -307,8 +214,8 @@ begin
     port map(
       CLEAR_IN      => '0',              -- reset input (high active, async)
       CLEAR_N_IN    => '1',              -- reset input (low active, async)
-      CLK_IN        => clk_200_internal, -- raw master clock, NOT from PLL/DLL!
-      SYSCLK_IN     => clk_100_i,        -- PLL/DLL remastered clock
+      CLK_IN        => clk_raw_internal, -- raw master clock, NOT from PLL/DLL!
+      SYSCLK_IN     => clk_sys_i,        -- PLL/DLL remastered clock
       PLL_LOCKED_IN => pll_lock,         -- master PLL lock signal (async)
       RESET_IN      => '0',              -- general reset signal (SYSCLK)
       TRB_RESET_IN  => med_stat_op(13),  -- TRBnet reset signal (SYSCLK)
@@ -321,26 +228,31 @@ begin
 ---------------------------------------------------------------------------
 -- Clock Handling
 ---------------------------------------------------------------------------
-
+gen_200_PLL : if USE_125_MHZ = c_NO generate
   THE_MAIN_PLL : pll_in200_out100
     port map(
       CLK   => CLK_GPLL_RIGHT,
-      CLKOP => clk_100_internal,
-      CLKOK => clk_200_internal,
+      CLKOP => clk_sys_internal,
+      CLKOK => clk_raw_internal,
       LOCK  => pll_lock
       );
+end generate;      
+
+gen_125 : if USE_125_MHZ = c_YES generate
+  clk_sys_internal <= CLK_GPLL_LEFT;
+  clk_raw_internal <= CLK_GPLL_LEFT;
+end generate; 
 
-  gen_sync_clocks : if SYNC_MODE = c_YES generate
-    clk_100_i <= rx_clock_100;
-    clk_200_i <= rx_clock_200;
-    clk_tdc   <= rx_clock_200;
-  end generate;
+gen_sync_clocks : if SYNC_MODE = c_YES generate
+  clk_sys_i <= rx_clock_half;
+--   clk_200_i <= rx_clock_full;
+end generate;
+
+gen_local_clocks : if SYNC_MODE = c_NO generate
+  clk_sys_i <= clk_sys_internal;
+--   clk_200_i <= clk_raw_internal;
+end generate;
 
-  gen_local_clocks : if SYNC_MODE = c_NO generate
-    clk_100_i <= clk_100_internal;
-    clk_200_i <= clk_200_internal;
-    clk_tdc   <= CLK_PCLK_LEFT;
-  end generate;
 
 ---------------------------------------------------------------------------
 -- The TrbNet media interface (to other FPGA)
@@ -349,13 +261,14 @@ begin
     generic map(
       SERDES_NUM  => 1,     --number of serdes in quad
       EXT_CLOCK   => c_NO,  --use internal clock
-      USE_200_MHZ => c_YES, --run on 200 MHz clock
+      USE_200_MHZ => USE_200_MHZ, --run on 200 MHz clock
+      USE_125_MHZ => USE_125_MHZ,
       USE_CTC     => c_NO,
       USE_SLAVE   => SYNC_MODE
       )      
     port map(
-      CLK                => clk_200_internal,
-      SYSCLK             => clk_100_i,
+      CLK                => clk_raw_internal,
+      SYSCLK             => clk_sys_i,
       RESET              => reset_i,
       CLEAR              => clear_i,
       CLK_EN             => '1',
@@ -369,16 +282,16 @@ begin
       MED_DATAREADY_OUT  => med_dataready_in,
       MED_READ_IN        => med_read_out,
       REFCLK2CORE_OUT    => open,
-      CLK_RX_HALF_OUT    => rx_clock_100,
-      CLK_RX_FULL_OUT    => rx_clock_200,
+      CLK_RX_HALF_OUT    => rx_clock_half,
+      CLK_RX_FULL_OUT    => rx_clock_full,
       
       --SFP Connection
       SD_RXD_P_IN        => SERDES_ADDON_RX(2),
       SD_RXD_N_IN        => SERDES_ADDON_RX(3),
       SD_TXD_P_OUT       => SERDES_ADDON_TX(2),
       SD_TXD_N_OUT       => SERDES_ADDON_TX(3),
-      SD_REFCLK_P_IN     => open,
-      SD_REFCLK_N_IN     => open,
+      SD_REFCLK_P_IN     => '0',
+      SD_REFCLK_N_IN     => '0',
       SD_PRSNT_N_IN      => FPGA5_COMM(0),
       SD_LOS_IN          => FPGA5_COMM(0),
       SD_TXDIS_OUT       => FPGA5_COMM(2),
@@ -423,48 +336,48 @@ begin
       HEADER_BUFFER_FULL_THRESH => 256
       )
     port map(
-      CLK                => clk_100_i,
+      CLK                => clk_sys_i,
       RESET              => reset_i,
       CLK_EN             => '1',
-      MED_DATAREADY_OUT  => med_dataready_out,  -- open, --
-      MED_DATA_OUT       => med_data_out,  -- open, --
-      MED_PACKET_NUM_OUT => med_packet_num_out,  -- open, --
+      MED_DATAREADY_OUT  => med_dataready_out,
+      MED_DATA_OUT       => med_data_out,
+      MED_PACKET_NUM_OUT => med_packet_num_out,
       MED_READ_IN        => med_read_in,
       MED_DATAREADY_IN   => med_dataready_in,
       MED_DATA_IN        => med_data_in,
       MED_PACKET_NUM_IN  => med_packet_num_in,
-      MED_READ_OUT       => med_read_out,  -- open, --
+      MED_READ_OUT       => med_read_out,
       MED_STAT_OP_IN     => med_stat_op,
       MED_CTRL_OP_OUT    => med_ctrl_op,
 
       --Timing trigger in
-      TRG_TIMING_TRG_RECEIVED_IN  => timing_trg_received_i,
+      TRG_TIMING_TRG_RECEIVED_IN  => '0',
       --LVL1 trigger to FEE
-      LVL1_TRG_DATA_VALID_OUT     => trg_data_valid_i,
-      LVL1_VALID_TIMING_TRG_OUT   => trg_timing_valid_i,
-      LVL1_VALID_NOTIMING_TRG_OUT => trg_notiming_valid_i,
-      LVL1_INVALID_TRG_OUT        => trg_invalid_i,
+      LVL1_TRG_DATA_VALID_OUT     => open,
+      LVL1_VALID_TIMING_TRG_OUT   => open,
+      LVL1_VALID_NOTIMING_TRG_OUT => open,
+      LVL1_INVALID_TRG_OUT        => open,
 
-      LVL1_TRG_TYPE_OUT        => trg_type_i,
-      LVL1_TRG_NUMBER_OUT      => trg_number_i,
-      LVL1_TRG_CODE_OUT        => trg_code_i,
-      LVL1_TRG_INFORMATION_OUT => trg_information_i,
-      LVL1_INT_TRG_NUMBER_OUT  => trg_int_number_i,
+      LVL1_TRG_TYPE_OUT        => open,
+      LVL1_TRG_NUMBER_OUT      => open,
+      LVL1_TRG_CODE_OUT        => open,
+      LVL1_TRG_INFORMATION_OUT => open,
+      LVL1_INT_TRG_NUMBER_OUT  => open,
 
       --Information about trigger handler errors
-      TRG_MULTIPLE_TRG_OUT     => trg_multiple_trg_i,
-      TRG_TIMEOUT_DETECTED_OUT => trg_timeout_detected_i,
-      TRG_SPURIOUS_TRG_OUT     => trg_spurious_trg_i,
-      TRG_MISSING_TMG_TRG_OUT  => trg_missing_tmg_trg_i,
-      TRG_SPIKE_DETECTED_OUT   => trg_spike_detected_i,
+      TRG_MULTIPLE_TRG_OUT     => open,
+      TRG_TIMEOUT_DETECTED_OUT => open,
+      TRG_SPURIOUS_TRG_OUT     => open,
+      TRG_MISSING_TMG_TRG_OUT  => open,
+      TRG_SPIKE_DETECTED_OUT   => open,
 
       --Response from FEE
-      FEE_TRG_RELEASE_IN(0)       => fee_trg_release_i,
-      FEE_TRG_STATUSBITS_IN       => fee_trg_statusbits_i,
-      FEE_DATA_IN                 => fee_data_i,
-      FEE_DATA_WRITE_IN(0)        => fee_data_write_i,
-      FEE_DATA_FINISHED_IN(0)     => fee_data_finished_i,
-      FEE_DATA_ALMOST_FULL_OUT(0) => fee_almost_full_i,
+      FEE_TRG_RELEASE_IN(0)       => '1',
+      FEE_TRG_STATUSBITS_IN       => (others => '0'),
+      FEE_DATA_IN                 => (others => '0'),
+      FEE_DATA_WRITE_IN(0)        => '0',
+      FEE_DATA_FINISHED_IN(0)     => '1',
+      FEE_DATA_ALMOST_FULL_OUT(0) => open,
 
       -- Slow Control Data Port
       REGIO_COMMON_STAT_REG_IN           => common_stat_reg,  --0x00
@@ -509,22 +422,18 @@ begin
       DEBUG_LVL1_HANDLER_OUT      => open
       );
 
----------------------------------------------------------------------------
--- I/O
----------------------------------------------------------------------------
-  timing_trg_received_i <= TRIGGER_LEFT;
 
 ---------------------------------------------------------------------------
 -- Bus Handler
 ---------------------------------------------------------------------------
   THE_BUS_HANDLER : trb_net16_regio_bus_handler
     generic map(
-      PORT_NUMBER    => 9,
-      PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", 2 => x"d400", 3 => x"c000", 4 => x"c100", 5 => x"c200", 6 => x"c300", 7 => x"b000", 8 => x"b800", others => x"0000"),
-      PORT_ADDR_MASK => (0 => 1, 1 => 6, 2 => 5, 3 => 7, 4 => 5, 5 => 7, 6 => 7, 7 => 9, 8 => 9, others => 0)
+      PORT_NUMBER    => 3,
+      PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"b800", others => x"0000"),
+      PORT_ADDR_MASK => (0 => 9,       1 => 9,       2 => 9,       others => 0)
       )
     port map(
-      CLK   => clk_100_i,
+      CLK   => clk_sys_i,
       RESET => reset_i,
 
       DAT_ADDR_IN          => regio_addr_out,
@@ -538,117 +447,46 @@ begin
       DAT_NO_MORE_DATA_OUT => regio_no_more_data_in,
       DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in,
 
-      --Bus Handler (SPI CTRL)
-      BUS_READ_ENABLE_OUT(0)              => spictrl_read_en,
-      BUS_WRITE_ENABLE_OUT(0)             => spictrl_write_en,
-      BUS_DATA_OUT(0*32+31 downto 0*32)   => spictrl_data_in,
-      BUS_ADDR_OUT(0*16)                  => spictrl_addr,
-      BUS_ADDR_OUT(0*16+15 downto 0*16+1) => open,
+    --Bus Handler (SPI Memory)
+      BUS_READ_ENABLE_OUT(0)              => spimem_read_en,
+      BUS_WRITE_ENABLE_OUT(0)             => spimem_write_en,
+      BUS_DATA_OUT(0*32+31 downto 0*32)   => spimem_data_in,
+      BUS_ADDR_OUT(0*16+8 downto 0*16)    => spimem_addr,
+      BUS_ADDR_OUT(0*16+15 downto 0*16+9) => open,
       BUS_TIMEOUT_OUT(0)                  => open,
-      BUS_DATA_IN(0*32+31 downto 0*32)    => spictrl_data_out,
-      BUS_DATAREADY_IN(0)                 => spictrl_ack,
-      BUS_WRITE_ACK_IN(0)                 => spictrl_ack,
-      BUS_NO_MORE_DATA_IN(0)              => spictrl_busy,
-      BUS_UNKNOWN_ADDR_IN(0)              => '0',
-      --Bus Handler (SPI Memory)
-      BUS_READ_ENABLE_OUT(1)              => spimem_read_en,
-      BUS_WRITE_ENABLE_OUT(1)             => spimem_write_en,
-      BUS_DATA_OUT(1*32+31 downto 1*32)   => spimem_data_in,
-      BUS_ADDR_OUT(1*16+5 downto 1*16)    => spimem_addr,
-      BUS_ADDR_OUT(1*16+15 downto 1*16+6) => open,
+      BUS_DATA_IN(0*32+31 downto 0*32)    => spimem_data_out,
+      BUS_DATAREADY_IN(0)                 => spimem_dataready_out,
+      BUS_WRITE_ACK_IN(0)                 => spimem_write_ack_out,
+      BUS_NO_MORE_DATA_IN(0)              => spimem_no_more_data_out,
+      BUS_UNKNOWN_ADDR_IN(0)              => spimem_unknown_addr_out,
+
+
+      --SCI first Media Interface
+      BUS_READ_ENABLE_OUT(1)              => sci1_read,
+      BUS_WRITE_ENABLE_OUT(1)             => sci1_write,
+      BUS_DATA_OUT(1*32+7 downto 1*32)    => sci1_data_in,
+      BUS_DATA_OUT(1*32+31 downto 1*32+8) => open,
+      BUS_ADDR_OUT(1*16+8 downto 1*16)    => sci1_addr,
+      BUS_ADDR_OUT(1*16+15 downto 1*16+9) => open,
       BUS_TIMEOUT_OUT(1)                  => open,
-      BUS_DATA_IN(1*32+31 downto 1*32)    => spimem_data_out,
-      BUS_DATAREADY_IN(1)                 => spimem_ack,
-      BUS_WRITE_ACK_IN(1)                 => spimem_ack,
+      BUS_DATA_IN(1*32+7 downto 1*32)     => sci1_data_out,
+      BUS_DATAREADY_IN(1)                 => sci1_ack,
+      BUS_WRITE_ACK_IN(1)                 => sci1_ack,
       BUS_NO_MORE_DATA_IN(1)              => '0',
       BUS_UNKNOWN_ADDR_IN(1)              => '0',
-      --DAC
-      BUS_READ_ENABLE_OUT(2)              => dac_read_en,
-      BUS_WRITE_ENABLE_OUT(2)             => dac_write_en,
-      BUS_DATA_OUT(2*32+31 downto 2*32)   => dac_data_in,
-      BUS_ADDR_OUT(2*16+4 downto 2*16)    => dac_addr,
-      BUS_ADDR_OUT(2*16+15 downto 2*16+5) => open,
-      BUS_TIMEOUT_OUT(2)                  => open,
-      BUS_DATA_IN(2*32+31 downto 2*32)    => dac_data_out,
-      BUS_DATAREADY_IN(2)                 => dac_ack,
-      BUS_WRITE_ACK_IN(2)                 => dac_ack,
-      BUS_NO_MORE_DATA_IN(2)              => dac_busy,
-      BUS_UNKNOWN_ADDR_IN(2)              => '0',
-
-      --HitRegisters
-      BUS_READ_ENABLE_OUT(3)              => hitreg_read_en,
-      BUS_WRITE_ENABLE_OUT(3)             => hitreg_write_en,
-      BUS_DATA_OUT(3*32+31 downto 3*32)   => open,
-      BUS_ADDR_OUT(3*16+6 downto 3*16)    => hitreg_addr,
-      BUS_ADDR_OUT(3*16+15 downto 3*16+7) => open,
-      BUS_TIMEOUT_OUT(3)                  => open,
-      BUS_DATA_IN(3*32+31 downto 3*32)    => hitreg_data_out,
-      BUS_DATAREADY_IN(3)                 => hitreg_data_ready,
-      BUS_WRITE_ACK_IN(3)                 => '0',
-      BUS_NO_MORE_DATA_IN(3)              => '0',
-      BUS_UNKNOWN_ADDR_IN(3)              => hitreg_invalid,
-      --Status Registers
-      BUS_READ_ENABLE_OUT(4)              => srb_read_en,
-      BUS_WRITE_ENABLE_OUT(4)             => srb_write_en,
-      BUS_DATA_OUT(4*32+31 downto 4*32)   => open,
-      BUS_ADDR_OUT(4*16+6 downto 4*16)    => srb_addr,
-      BUS_ADDR_OUT(4*16+15 downto 4*16+7) => open,
-      BUS_TIMEOUT_OUT(4)                  => open,
-      BUS_DATA_IN(4*32+31 downto 4*32)    => srb_data_out,
-      BUS_DATAREADY_IN(4)                 => srb_data_ready,
-      BUS_WRITE_ACK_IN(4)                 => '0',
-      BUS_NO_MORE_DATA_IN(4)              => '0',
-      BUS_UNKNOWN_ADDR_IN(4)              => srb_invalid,
-      --Encoder Start Registers
-      BUS_READ_ENABLE_OUT(5)              => esb_read_en,
-      BUS_WRITE_ENABLE_OUT(5)             => esb_write_en,
-      BUS_DATA_OUT(5*32+31 downto 5*32)   => open,
-      BUS_ADDR_OUT(5*16+6 downto 5*16)    => esb_addr,
-      BUS_ADDR_OUT(5*16+15 downto 5*16+7) => open,
-      BUS_TIMEOUT_OUT(5)                  => open,
-      BUS_DATA_IN(5*32+31 downto 5*32)    => esb_data_out,
-      BUS_DATAREADY_IN(5)                 => esb_data_ready,
-      BUS_WRITE_ACK_IN(5)                 => '0',
-      BUS_NO_MORE_DATA_IN(5)              => '0',
-      BUS_UNKNOWN_ADDR_IN(5)              => esb_invalid,
-      --Fifo Write Registers
-      BUS_READ_ENABLE_OUT(6)              => fwb_read_en,
-      BUS_WRITE_ENABLE_OUT(6)             => fwb_write_en,
-      BUS_DATA_OUT(6*32+31 downto 6*32)   => open,
-      BUS_ADDR_OUT(6*16+6 downto 6*16)    => fwb_addr,
-      BUS_ADDR_OUT(6*16+15 downto 6*16+7) => open,
-      BUS_TIMEOUT_OUT(6)                  => open,
-      BUS_DATA_IN(6*32+31 downto 6*32)    => fwb_data_out,
-      BUS_DATAREADY_IN(6)                 => fwb_data_ready,
-      BUS_WRITE_ACK_IN(6)                 => '0',
-      BUS_NO_MORE_DATA_IN(6)              => '0',
-      BUS_UNKNOWN_ADDR_IN(6)              => fwb_invalid,
-      --SCI first Media Interface
-      BUS_READ_ENABLE_OUT(7)              => sci1_read,
-      BUS_WRITE_ENABLE_OUT(7)             => sci1_write,
-      BUS_DATA_OUT(7*32+7 downto 7*32)    => sci1_data_in,
-      BUS_DATA_OUT(7*32+31 downto 7*32+8) => open,
-      BUS_ADDR_OUT(7*16+8 downto 7*16)    => sci1_addr,
-      BUS_ADDR_OUT(7*16+15 downto 7*16+9) => open,
-      BUS_TIMEOUT_OUT(7)                  => open,
-      BUS_DATA_IN(7*32+7 downto 7*32)     => sci1_data_out,
-      BUS_DATAREADY_IN(7)                 => sci1_ack,
-      BUS_WRITE_ACK_IN(7)                 => sci1_ack,
-      BUS_NO_MORE_DATA_IN(7)              => '0',
-      BUS_UNKNOWN_ADDR_IN(7)              => '0',
       --SCI soda test Media Interface
-      BUS_READ_ENABLE_OUT(8)              => sci2_read,
-      BUS_WRITE_ENABLE_OUT(8)             => sci2_write,
-      BUS_DATA_OUT(8*32+7 downto 8*32)    => sci2_data_in,
-      BUS_DATA_OUT(8*32+31 downto 8*32+8) => open,
-      BUS_ADDR_OUT(8*16+8 downto 8*16)    => sci2_addr,
-      BUS_ADDR_OUT(8*16+15 downto 8*16+9) => open,
-      BUS_TIMEOUT_OUT(8)                  => open,
-      BUS_DATA_IN(8*32+7 downto 8*32)     => sci2_data_out,
-      BUS_DATAREADY_IN(8)                 => sci2_ack,
-      BUS_WRITE_ACK_IN(8)                 => sci2_ack,
-      BUS_NO_MORE_DATA_IN(8)              => '0',
-      BUS_UNKNOWN_ADDR_IN(8)              => sci2_nack,
+      BUS_READ_ENABLE_OUT(2)              => sci2_read,
+      BUS_WRITE_ENABLE_OUT(2)             => sci2_write,
+      BUS_DATA_OUT(2*32+7 downto 2*32)    => sci2_data_in,
+      BUS_DATA_OUT(2*32+31 downto 2*32+8) => open,
+      BUS_ADDR_OUT(2*16+8 downto 2*16)    => sci2_addr,
+      BUS_ADDR_OUT(2*16+15 downto 2*16+9) => open,
+      BUS_TIMEOUT_OUT(2)                  => open,
+      BUS_DATA_IN(2*32+7 downto 2*32)     => sci2_data_out,
+      BUS_DATAREADY_IN(2)                 => sci2_ack,
+      BUS_WRITE_ACK_IN(2)                 => sci2_ack,
+      BUS_NO_MORE_DATA_IN(2)              => '0',
+      BUS_UNKNOWN_ADDR_IN(2)              => sci2_nack,
       STAT_DEBUG => open
       );
 
@@ -656,84 +494,43 @@ begin
 -- SPI / Flash
 ---------------------------------------------------------------------------
 
-  THE_SPI_MASTER : spi_master
-    port map(
-      CLK_IN         => clk_100_i,
-      RESET_IN       => reset_i,
-      -- Slave bus
-      BUS_READ_IN    => spictrl_read_en,
-      BUS_WRITE_IN   => spictrl_write_en,
-      BUS_BUSY_OUT   => spictrl_busy,
-      BUS_ACK_OUT    => spictrl_ack,
-      BUS_ADDR_IN(0) => spictrl_addr,
-      BUS_DATA_IN    => spictrl_data_in,
-      BUS_DATA_OUT   => spictrl_data_out,
-      -- SPI connections
-      SPI_CS_OUT     => FLASH_CS,
-      SPI_SDI_IN     => FLASH_DOUT,
-      SPI_SDO_OUT    => FLASH_DIN,
-      SPI_SCK_OUT    => FLASH_CLK,
-      -- BRAM for read/write data
-      BRAM_A_OUT     => spi_bram_addr,
-      BRAM_WR_D_IN   => spi_bram_wr_d,
-      BRAM_RD_D_OUT  => spi_bram_rd_d,
-      BRAM_WE_OUT    => spi_bram_we,
-      -- Status lines
-      STAT           => open
-      );
-
--- data memory for SPI accesses
-  THE_SPI_MEMORY : spi_databus_memory
-    port map(
-      CLK_IN        => clk_100_i,
-      RESET_IN      => reset_i,
-      -- Slave bus
-      BUS_ADDR_IN   => spimem_addr,
-      BUS_READ_IN   => spimem_read_en,
-      BUS_WRITE_IN  => spimem_write_en,
-      BUS_ACK_OUT   => spimem_ack,
-      BUS_DATA_IN   => spimem_data_in,
-      BUS_DATA_OUT  => spimem_data_out,
-      -- state machine connections
-      BRAM_ADDR_IN  => spi_bram_addr,
-      BRAM_WR_D_OUT => spi_bram_wr_d,
-      BRAM_RD_D_IN  => spi_bram_rd_d,
-      BRAM_WE_IN    => spi_bram_we,
-      -- Status lines
-      STAT          => open
-      );
-
-
-
-
----------------------------------------------------------------------------
--- Reboot FPGA
----------------------------------------------------------------------------
-  THE_FPGA_REBOOT : fpga_reboot
-    port map(
-      CLK       => clk_100_i,
-      RESET     => reset_i,
-      DO_REBOOT => common_ctrl_reg(15),
-      PROGRAMN  => PROGRAMN
-      );
-
+THE_SPI_RELOAD : entity work.spi_flash_and_fpga_reload
+  port map(
+    CLK_IN               => clk_sys_i,
+    RESET_IN             => reset_i,
+    
+    BUS_ADDR_IN          => spimem_addr,
+    BUS_READ_IN          => spimem_read_en,
+    BUS_WRITE_IN         => spimem_write_en,
+    BUS_DATAREADY_OUT    => spimem_dataready_out,
+    BUS_WRITE_ACK_OUT    => spimem_write_ack_out,
+    BUS_UNKNOWN_ADDR_OUT => spimem_unknown_addr_out,
+    BUS_NO_MORE_DATA_OUT => spimem_no_more_data_out,
+    BUS_DATA_IN          => spimem_data_in,
+    BUS_DATA_OUT         => spimem_data_out,
+    
+    DO_REBOOT_IN         => common_ctrl_reg(15),     
+    PROGRAMN             => PROGRAMN,
+    
+    SPI_CS_OUT           => FLASH_CS,
+    SPI_SCK_OUT          => FLASH_CLK,
+    SPI_SDO_OUT          => FLASH_DIN,
+    SPI_SDI_IN           => FLASH_DOUT
+    );
 
       
 ---------------------------------------------------------------------------
 -- The synchronous interface for Soda tests
 ---------------------------------------------------------------------------      
----------------------------------------------------------------------------
--- The TrbNet media interface (Uplink)
----------------------------------------------------------------------------
-THE_SODA_SOURCE : med_ecp3_sfp_sync
+
+THE_SODA_SOURCE : entity work.med_ecp3_sfp_sync
   generic map(
     SERDES_NUM  => 0,    --number of serdes in quad
-    MASTER_CLOCK_SWITCH => c_NO,
     IS_SYNC_SLAVE => c_NO
     )
   port map(
-    CLK                => clk_200_internal, --clk_200_i,
-    SYSCLK             => clk_100_i,
+    CLK                => clk_raw_internal, --clk_200_i,
+    SYSCLK             => clk_sys_i,
     RESET              => reset_i,
     CLEAR              => clear_i,
     --Internal Connection for TrbNet data -> not used a.t.m.
@@ -744,11 +541,10 @@ THE_SODA_SOURCE : med_ecp3_sfp_sync
     MED_DATA_OUT       => open,
     MED_PACKET_NUM_OUT => open,
     MED_DATAREADY_OUT  => open,
-    MED_READ_IN        => open,
-    CLK_RX_HALF_OUT    => soda_rx_clock_100,
-    CLK_RX_FULL_OUT    => soda_rx_clock_200,
+    MED_READ_IN        => '1',
+    CLK_RX_HALF_OUT    => soda_rx_clock_half,
+    CLK_RX_FULL_OUT    => soda_rx_clock_full,
     
-    IS_SLAVE           => '0',   --will be generic soon
     RX_DLM             => rx_dlm_i,
     RX_DLM_WORD        => rx_dlm_word,
     TX_DLM             => tx_dlm_i,
@@ -758,8 +554,8 @@ THE_SODA_SOURCE : med_ecp3_sfp_sync
     SD_RXD_N_IN        => SERDES_ADDON_RX(1),
     SD_TXD_P_OUT       => SERDES_ADDON_TX(0),
     SD_TXD_N_OUT       => SERDES_ADDON_TX(1),
-    SD_REFCLK_P_IN     => open,
-    SD_REFCLK_N_IN     => open,
+    SD_REFCLK_P_IN     => '0',
+    SD_REFCLK_N_IN     => '0',
     SD_PRSNT_N_IN      => SFP_MOD0(1),
     SD_LOS_IN          => SFP_LOS(1),
     SD_TXDIS_OUT       => SFP_TXDIS(1),
@@ -777,14 +573,18 @@ THE_SODA_SOURCE : med_ecp3_sfp_sync
     STAT_DEBUG         => open,
     CTRL_DEBUG         => (others => '0')
    );      
-      
-
-
 
+   
+---------------------------------------------------------------------------
+-- The Soda Source
+---------------------------------------------------------------------------         
+   
+   
+   
 ---------------------------------------------------------------------------
 -- LED
 ---------------------------------------------------------------------------
-  LED_ORANGE <= not reset_i when rising_edge(clk_100_internal);
+  LED_ORANGE <= not reset_i when rising_edge(clk_sys_internal);
   LED_YELLOW <= '1';
   LED_GREEN  <= not med_stat_op(9);
   LED_RED    <= not (med_stat_op(10) or med_stat_op(11));
@@ -798,97 +598,11 @@ THE_SODA_SOURCE : med_ecp3_sfp_sync
 ---------------------------------------------------------------------------
   process
     begin
-      wait until rising_edge(clk_100_internal);
+      wait until rising_edge(clk_sys_internal);
       time_counter <= time_counter + 1;
     end process;
 
 
 
--------------------------------------------------------------------------------
--- TDC
--------------------------------------------------------------------------------
-  --THE_TDC : TDC
-    --generic map (
-      --CHANNEL_NUMBER => 5,             -- Number of TDC channels
-      --STATUS_REG_NR  => REGIO_NUM_STAT_REGS,
-      --CONTROL_REG_NR => REGIO_NUM_CTRL_REGS)
-    --port map (
-      --RESET                 => reset_i,
-      --CLK_TDC               => clk_tdc,  -- Clock used for the time measurement
-      --CLK_READOUT           => clk_100_i,   -- Clock for the readout
-      --REFERENCE_TIME        => timing_trg_received_i,  -- Reference time input
-      --HIT_IN                => hit_in_i(3 downto 0),  -- Channel start signals
-      --TRG_WIN_PRE           => ctrl_reg(42 downto 32),  -- Pre-Trigger window width
-      --TRG_WIN_POST          => ctrl_reg(58 downto 48),  -- Post-Trigger window width
-      ----
-      ---- Trigger signals from handler
-      --TRG_DATA_VALID_IN     => trg_data_valid_i,  -- trig data valid signal from trbnet
-      --VALID_TIMING_TRG_IN   => trg_timing_valid_i,  -- valid timing trigger signal from trbnet
-      --VALID_NOTIMING_TRG_IN => trg_notiming_valid_i,  -- valid notiming signal from trbnet
-      --INVALID_TRG_IN        => trg_invalid_i,  -- invalid trigger signal from trbnet
-      --TMGTRG_TIMEOUT_IN     => trg_timeout_detected_i,  -- timing trigger timeout signal from trbnet
-      --SPIKE_DETECTED_IN     => trg_spike_detected_i,
-      --MULTI_TMG_TRG_IN      => trg_multiple_trg_i,
-      --SPURIOUS_TRG_IN       => trg_spurious_trg_i,
-      ----
-      --TRG_NUMBER_IN         => trg_number_i,  -- LVL1 trigger information package
-      --TRG_CODE_IN           => trg_code_i,  --
-      --TRG_INFORMATION_IN    => trg_information_i,   --
-      --TRG_TYPE_IN           => trg_type_i,  -- LVL1 trigger information package
-      ----
-      ----Response to handler
-      --TRG_RELEASE_OUT       => fee_trg_release_i,   -- trigger release signal
-      --TRG_STATUSBIT_OUT     => fee_trg_statusbits_i,  -- status information of the tdc
-      --DATA_OUT              => fee_data_i,  -- tdc data
-      --DATA_WRITE_OUT        => fee_data_write_i,  -- data valid signal
-      --DATA_FINISHED_OUT     => fee_data_finished_i,  -- readout finished signal
-      ----
-      ----Hit Counter Bus
-      --HCB_READ_EN_IN        => hitreg_read_en,    -- bus read en strobe
-      --HCB_WRITE_EN_IN       => hitreg_write_en,   -- bus write en strobe
-      --HCB_ADDR_IN           => hitreg_addr,   -- bus address
-      --HCB_DATA_OUT          => hitreg_data_out,   -- bus data
-      --HCB_DATAREADY_OUT     => hitreg_data_ready,   -- bus data ready strobe
-      --HCB_UNKNOWN_ADDR_OUT  => hitreg_invalid,    -- bus invalid addr
-      ----Status Registers Bus
-      --SRB_READ_EN_IN        => srb_read_en,   -- bus read en strobe
-      --SRB_WRITE_EN_IN       => srb_write_en,  -- bus write en strobe
-      --SRB_ADDR_IN           => srb_addr,    -- bus address
-      --SRB_DATA_OUT          => srb_data_out,  -- bus data
-      --SRB_DATAREADY_OUT     => srb_data_ready,    -- bus data ready strobe
-      --SRB_UNKNOWN_ADDR_OUT  => srb_invalid,   -- bus invalid addr
-      ----Encoder Start Registers Bus
-      --ESB_READ_EN_IN        => esb_read_en,   -- bus read en strobe
-      --ESB_WRITE_EN_IN       => esb_write_en,  -- bus write en strobe
-      --ESB_ADDR_IN           => esb_addr,    -- bus address
-      --ESB_DATA_OUT          => esb_data_out,  -- bus data
-      --ESB_DATAREADY_OUT     => esb_data_ready,    -- bus data ready strobe
-      --ESB_UNKNOWN_ADDR_OUT  => esb_invalid,   -- bus invalid addr
-      ----Fifo Write Registers Bus
-      --FWB_READ_EN_IN        => fwb_read_en,   -- bus read en strobe
-      --FWB_WRITE_EN_IN       => fwb_write_en,  -- bus write en strobe
-      --FWB_ADDR_IN           => fwb_addr,    -- bus address
-      --FWB_DATA_OUT          => fwb_data_out,  -- bus data
-      --FWB_DATAREADY_OUT     => fwb_data_ready,    -- bus data ready strobe
-      --FWB_UNKNOWN_ADDR_OUT  => fwb_invalid,   -- bus invalid addr
-      ----Lost Hit Registers Bus
-      --LHB_READ_EN_IN        => '0', -- lhb_read_en,   -- bus read en strobe
-      --LHB_WRITE_EN_IN       => '0', -- lhb_write_en,  -- bus write en strobe
-      --LHB_ADDR_IN           => (others => '0'), -- lhb_addr,    -- bus address
-      --LHB_DATA_OUT          => open, -- lhb_data_out,  -- bus data
-      --LHB_DATAREADY_OUT     => open, -- lhb_data_ready,    -- bus data ready strobe
-      --LHB_UNKNOWN_ADDR_OUT  => open, -- lhb_invalid,   -- bus invalid addr
-      ----
-      --LOGIC_ANALYSER_OUT    => TEST_LINE,
-      --CONTROL_REG_IN        => ctrl_reg);
-
-
-  hit_in_i <= (others => '0');
-
-  --Gen_Hit_In_Signals : for i in 0 to 31 generate
-  -- hit_in_i(i*2)     <= INP(i);
-  -- hit_in_i(i*2+1)   <= not INP(i);
-  --end generate Gen_Hit_In_Signals;
-
 
 end architecture;
index cb2aa0fd3349f96787b7879dd06420dfa67903b6..ef9c7ac809e34462a8377f4e51d16d4e037d53e4 100644 (file)
@@ -8,6 +8,6 @@ use ieee.numeric_std.all;
 
 package version is
 
-    constant VERSION_NUMBER_TIME  : integer   := 1361540878;
+    constant VERSION_NUMBER_TIME  : integer   := 1364404198;
 
 end package version;
index b1ac900f2980d01bd998e2218ae05424e2f44187..94f07edc8e304762065c6c188828840dfacd9cea 100755 (executable)
@@ -12,7 +12,7 @@ my $TOPNAME                      = "trb3_central";  #Name of top-level entity
 #my $lattice_path                 = '/d/jspc29/lattice/diamond/2.1_x64';
 my $lattice_path                 = '/d/jspc29/lattice/diamond/2.01';
 # my $synplify_path                = '/d/jspc29/lattice/synplify/fpga_e201103/';
-my $synplify_path                = '/d/jspc29/lattice/synplify/G-2012.09-SP1/';
+my $synplify_path                = '/d/jspc29/lattice/synplify/F-2012.03-SP1/';
 my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de";
 my $lm_license_file_for_par      = "1702\@hadeb05.gsi.de";
 ###################################################################################
index ea6cf3f28e21d4daf895c647503080c21ad756c6..cae2c806c037afab986bd83379ac36d378b5c510 100644 (file)
@@ -912,7 +912,7 @@ LED_YELLOW <= link_ok; --debug(3);
   TEST_LINE(16)           <= 'Z';
   TEST_LINE(31 downto 17) <= med_stat_debug(31 downto 17);
   
-  CLK_TEST_OUT <= clk_100_internal & tx_dlm_i & rx_dlm_i;
+  CLK_TEST_OUT <= clk_100_internal & med_stat_debug(36) & rx_dlm_i;
   
 
 --   FPGA1_CONNECTOR(0) <= '0';
index 2298b1684bd83a320ab253037c116592ce83bead..41dada13dc0cbc59e89e28c3dc3c1931d5814473 100644 (file)
@@ -18,10 +18,10 @@ package config is
     constant USE_ETHERNET           : integer := c_YES;    
     
 --Run wih 125 MHz instead of 100 MHz     
-    constant USE_125_MHZ            : integer := c_NO;    
+    constant USE_125_MHZ            : integer := c_YES;    
    
 --Only slow-control, no trigger or read-out
-    constant USE_SCTRL_ONLY         : integer := c_NO;    
+    constant USE_SCTRL_ONLY         : integer := c_YES;    
 
 --Use sync mode, RX clock for all parts of the FPGA
     constant USE_RXCLOCK            : integer := c_NO;
index 09ab769c12aee698bf70a681da9b893ca75bb95e..92d276d369a0eb48543dc52666dd1be01c464953 100644 (file)
@@ -1,10 +1,10 @@
 -w
 -i 15
 -l 5
--n 1
+-n 2
 -y
 -s 12
--t 11
+-t 12
 -c 1
 -e 2
 #-g guidefile.ncd
index c273163425c7121ebc4071747718e502400e6d39..9d3b3e511e4fbd29bc784c451b8a47c561de773d 100644 (file)
@@ -93,7 +93,12 @@ add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_frame_constr.vhd"
 #add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_packet_constr_nologic.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_packet_constr.vhd"
 #add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_packet_constr_simple_sender.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_ipu2gbe.vhd"
+
+
+add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_ipu2gbe_simple_sender.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_ipu2gbe.vhd"
+
+
 #add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_ipu2gbe_nologic.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ip_configurator.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_buf.vhd"
index 5f66982b23bd01da1619f91332c75b2cb988597c..231475968449036ed87fbad5390452fd19e7ef2e 100644 (file)
@@ -41,9 +41,9 @@ MULTICYCLE TO CELL "THE_MEDIA_ONBOARD/SCI_DATA_OUT*" 50 ns;
 MULTICYCLE TO CELL "gen_uplink_THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns;\r
 \r
 #SPI Interface\r
-REGION "REGION_SPI" "R13C150D" 12 16 DEVSIZE;\r
-LOCATE UGROUP "THE_SPI_RELOAD/THE_SPI_MASTER/SPI_group" REGION "REGION_SPI" ; \r
-LOCATE UGROUP "THE_SPI_RELOAD/THE_SPI_MEMORY/SPI_group" REGION "REGION_SPI" ;\r
+#REGION "REGION_SPI" "R13C150D" 12 16 DEVSIZE;\r
+#LOCATE UGROUP "THE_SPI_RELOAD/THE_SPI_MASTER/SPI_group" REGION "REGION_SPI" ; \r
+#LOCATE UGROUP "THE_SPI_RELOAD/THE_SPI_MEMORY/SPI_group" REGION "REGION_SPI" ;\r
 \r
 \r
 MULTICYCLE FROM CELL "gen_ethernet_hub_THE_HUB/reset_i" 20 ns;\r
@@ -140,18 +140,29 @@ UGROUP "gbe_rx_tx"
        BLKNAME gen_ethernet_hub_GBE/FRAME_CONSTRUCTOR\r
        BLKNAME gen_ethernet_hub_GBE/MB_IP_CONFIG\r
        BLKNAME gen_ethernet_hub_GBE/THE_IP_CONFIGURATOR\r
-       #BLKNAME gen_ethernet_hub_GBE/PACKET_CONSTRUCTOR\r
+       BLKNAME gen_ethernet_hub_GBE/PACKET_CONSTRUCTOR\r
        #BLKNAME gen_ethernet_hub_GBE/THE_IPU_INTERFACE\r
        BLKNAME gen_ethernet_hub_GBE/setup_imp_gen_SETUP;\r
 \r
+\r
        \r
-REGION "GBE_REGION" "R40C2D" 35 40 DEVSIZE;\r
+#Normal design\r
+# REGION "GBE_REGION" "R40C2D" 35 40 DEVSIZE;\r
+# REGION "GBE_MAIN_REGION" "R74C30C" 38 36 DEVSIZE;\r
+# LOCATE UGROUP "controllers" REGION "GBE_MAIN_REGION" ;\r
+# LOCATE UGROUP "gbe_rx_tx" REGION "GBE_REGION" ;\r
+\r
+#Reduced design\r
+# REGION "GBE_REGION" "R40C2D" 35 40 DEVSIZE;\r
+#REGION "GBE_MAIN_REGION" "R74C30C" 35 90 DEVSIZE;\r
+#LOCATE UGROUP "controllers" REGION "GBE_MAIN_REGION" ;\r
+#LOCATE UGROUP "gbe_rx_tx" REGION "GBE_MAIN_REGION" ;\r
+\r
+\r
+\r
 REGION "MED0" "R70C2D" 35 40 DEVSIZE;\r
-LOCATE UGROUP "gbe_rx_tx" REGION "GBE_REGION" ;\r
 FREQUENCY NET "gen_ethernet_hub_GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/un1_PCS_SERDES_1" 125.000000 MHz ;\r
 FREQUENCY NET "gen_ethernet_hub_GBE/serdes_clk_125_c" 125.000000 MHz ;\r
-REGION "GBE_MAIN_REGION" "R74C30C" 38 36 DEVSIZE;\r
-LOCATE UGROUP "controllers" REGION "GBE_MAIN_REGION" ;\r
 LOCATE UGROUP "tsmac" REGION "MED0" ;\r
 BLOCK JTAGPATHS ;\r
 UGROUP "sd_tx_to_pcs" \r
index a417c27e9e9ced218226e67da096ab865994437e..7cc1748887144b13a55358539d425f26735db46e 100755 (executable)
@@ -9,7 +9,7 @@ use strict;
 ###################################################################################
 #Settings for this project
 my $TOPNAME                      = "trb3_periph_padiwa";  #Name of top-level entity
-my $lattice_path                 = '/d/jspc29/lattice/diamond/2.1_x64';
+my $lattice_path                 = '/d/jspc29/lattice/diamond/2.01';
 my $synplify_path                = '/d/jspc29/lattice/synplify/G-2012.09-SP1/';
 my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de";
 #my $lm_license_file_for_par      = "1702\@hadeb05.gsi.de";
diff --git a/wasa/panda_dirc_wasa.ldf b/wasa/panda_dirc_wasa.ldf
new file mode 100644 (file)
index 0000000..8859660
--- /dev/null
@@ -0,0 +1,53 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<BaliProject version="1.3" title="panda_dirc_wasa" device="LCMXO2-4000HC-6FTG256C" default_implementation="panda_dirc_wasa">
+    <Options/>
+    <Implementation title="panda_dirc_wasa" dir="panda_dirc_wasa" description="panda_dirc_wasa" default_strategy="Strategy1">
+        <Options top="panda_dirc_wasa"/>
+        <Source name="panda_dirc_wasa.vhd" type="VHDL" type_short="VHDL">
+            <Options top_module="panda_dirc_wasa"/>
+        </Source>
+        <Source name="../base/trb3_components.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../trbnet/trb_net_std.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../trbnet/trb_net_components.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="source/spi_slave.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../trbnet/trb_net_onewire.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="version.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="cores/oddr16.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="source/pwm.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="cores/efb_define_def.v" type="Verilog" type_short="Verilog">
+            <Options/>
+        </Source>
+        <Source name="cores/UFM_WB_top.v" type="Verilog" type_short="Verilog">
+            <Options/>
+        </Source>
+        <Source name="cores/pll.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="cores/flashram.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="cores/flash.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../base/panda_dirc_wasa1.lpf" type="Logic Preference" type_short="LPF">
+            <Options/>
+        </Source>
+    </Implementation>
+    <Strategy name="Strategy1" file="Strategy1.sty"/>
+</BaliProject>
index 995161f9940ecb64b00d450faa7e7d4136f2748e..0e70172113854799fb6e2bf40de993a0f5cbd80e 100644 (file)
@@ -17,4 +17,4 @@
 # -c 0
 # -e 0
 #
--exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1:
+-exp parCDP=0:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1: