INCLUDE_DHCP : std_logic := '0';
INCLUDE_ARP : std_logic := '0';
INCLUDE_PING : std_logic := '0';
+ INCLUDE_FWD : std_logic := '0';
FRAME_BUFFER_SIZE : integer range 1 to 4 := 1;
READOUT_BUFFER_SIZE : integer range 1 to 4 := 1;
SLOWCTRL_BUFFER_SIZE : integer range 1 to 4 := 1;
CFG_MAX_REPLY_SIZE_IN : in std_logic_vector(31 downto 0);
CFG_AUTO_THROTTLE_IN : in std_logic;
CFG_THROTTLE_PAUSE_IN : in std_logic_vector(15 downto 0);
+
+-- Forwarder
+FWD_DATA_IN : in std_logic_vector(7 downto 0);
+FWD_DATA_VALID_IN : in std_logic;
+FWD_SOP_IN : in std_logic;
+FWD_EOP_IN : in std_logic;
+FWD_READY_OUT : out std_logic;
+FWD_FULL_OUT : out std_logic;
+
MONITOR_RX_BYTES_OUT : out std_logic_vector(31 downto 0);
MONITOR_RX_FRAMES_OUT : out std_logic_vector(31 downto 0);
MONITOR_TX_BYTES_OUT : out std_logic_vector(31 downto 0);
INCLUDE_DHCP => INCLUDE_DHCP,
INCLUDE_ARP => INCLUDE_ARP,
INCLUDE_PING => INCLUDE_PING,
+ INCLUDE_FWD => INCLUDE_FWD,
READOUT_BUFFER_SIZE => READOUT_BUFFER_SIZE,
SLOWCTRL_BUFFER_SIZE => SLOWCTRL_BUFFER_SIZE
)
CFG_MAX_REPLY_SIZE_IN => CFG_MAX_REPLY_SIZE_IN,
CFG_AUTO_THROTTLE_IN => '0', --CFG_AUTO_THROTTLE_IN,
CFG_THROTTLE_PAUSE_IN => (others => '0'), --CFG_THROTTLE_PAUSE_IN,
+
+ FWD_DATA_IN => FWD_DATA_IN,
+ FWD_DATA_VALID_IN => FWD_DATA_VALID_IN,
+ FWD_SOP_IN => FWD_SOP_IN,
+ FWD_EOP_IN => FWD_EOP_IN,
+ FWD_READY_OUT => FWD_READY_OUT,
+ FWD_FULL_OUT => FWD_FULL_OUT,
+
+
TSM_HADDR_OUT => open, --mac_haddr,
TSM_HDATA_OUT => open, --mac_hdataout,
TSM_HCS_N_OUT => open, --mac_hcs,
INCLUDE_DHCP => INCLUDE_DHCP,
INCLUDE_ARP => INCLUDE_ARP,
INCLUDE_PING => INCLUDE_PING,
+ INCLUDE_FWD => INCLUDE_FWD,
READOUT_BUFFER_SIZE => READOUT_BUFFER_SIZE,
SLOWCTRL_BUFFER_SIZE => SLOWCTRL_BUFFER_SIZE
)
CFG_AUTO_THROTTLE_IN => CFG_AUTO_THROTTLE_IN,
CFG_THROTTLE_PAUSE_IN => CFG_THROTTLE_PAUSE_IN,
+ FWD_DATA_IN => FWD_DATA_IN,
+ FWD_DATA_VALID_IN => FWD_DATA_VALID_IN,
+ FWD_SOP_IN => FWD_SOP_IN,
+ FWD_EOP_IN => FWD_EOP_IN,
+ FWD_READY_OUT => FWD_READY_OUT,
+ FWD_FULL_OUT => FWD_FULL_OUT,
+
-- signal to/from Host interface of TriSpeed MAC
TSM_HADDR_OUT => open, --mac_haddr,
TSM_HDATA_OUT => open, --mac_hdataout,
LINK_HAS_ARP : std_logic_vector(3 downto 0) := "1111";
LINK_HAS_DHCP : std_logic_vector(3 downto 0) := "1111";
LINK_HAS_READOUT : std_logic_vector(3 downto 0) := "1111";
- LINK_HAS_SLOWCTRL : std_logic_vector(3 downto 0) := "1111"
+ LINK_HAS_SLOWCTRL : std_logic_vector(3 downto 0) := "1111";
+ LINK_HAS_FWD : std_logic_vector(3 downto 0) := "1111"
);
port(
CLK_SYS_IN : in std_logic;
-- Registers config
BUS_REG_RX : in CTRLBUS_RX;
BUS_REG_TX : out CTRLBUS_TX;
+
+-- Forwarder
+FWD_DATA_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0);
+FWD_DATA_VALID_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+FWD_SOP_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+FWD_EOP_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+FWD_READY_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+FWD_FULL_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+
MAKE_RESET_OUT : out std_logic;
DEBUG_OUT : out std_logic_vector(127 downto 0)
);
INCLUDE_DHCP => LINK_HAS_DHCP(3),
INCLUDE_ARP => LINK_HAS_ARP(3),
INCLUDE_PING => LINK_HAS_PING(3),
+ INCLUDE_FWD => LINK_HAS_FWD(3),
FRAME_BUFFER_SIZE => 1,
READOUT_BUFFER_SIZE => 4,
SLOWCTRL_BUFFER_SIZE => 2,
CFG_MAX_REPLY_SIZE_IN => cfg_max_reply,
CFG_AUTO_THROTTLE_IN => cfg_autothrottle,
CFG_THROTTLE_PAUSE_IN => cfg_throttle_pause,
+
+FWD_DATA_IN => FWD_DATA_IN(4 * 8 - 1 downto 3 * 8),
+FWD_DATA_VALID_IN => FWD_DATA_VALID_IN(3),
+FWD_SOP_IN => FWD_SOP_IN(3),
+FWD_EOP_IN => FWD_EOP_IN(3),
+FWD_READY_OUT => FWD_READY_OUT(3),
+FWD_FULL_OUT => FWD_FULL_OUT(3),
+
MONITOR_RX_FRAMES_OUT => monitor_rx_frames(4 * 32 - 1 downto 3 * 32),
MONITOR_RX_BYTES_OUT => monitor_rx_bytes(4 * 32 - 1 downto 3 * 32),
MONITOR_TX_FRAMES_OUT => monitor_tx_frames(4 * 32 - 1 downto 3 * 32),
INCLUDE_DHCP => LINK_HAS_DHCP(2),
INCLUDE_ARP => LINK_HAS_ARP(2),
INCLUDE_PING => LINK_HAS_PING(2),
+ INCLUDE_FWD => LINK_HAS_FWD(2),
FRAME_BUFFER_SIZE => 1,
READOUT_BUFFER_SIZE => 4,
SLOWCTRL_BUFFER_SIZE => 2,
CFG_MAX_REPLY_SIZE_IN => cfg_max_reply,
CFG_AUTO_THROTTLE_IN => cfg_autothrottle,
CFG_THROTTLE_PAUSE_IN => cfg_throttle_pause,
+
+FWD_DATA_IN => FWD_DATA_IN(3 * 8 - 1 downto 2 * 8),
+FWD_DATA_VALID_IN => FWD_DATA_VALID_IN(2),
+FWD_SOP_IN => FWD_SOP_IN(2),
+FWD_EOP_IN => FWD_EOP_IN(2),
+FWD_READY_OUT => FWD_READY_OUT(2),
+FWD_FULL_OUT => FWD_FULL_OUT(2),
+
MONITOR_RX_FRAMES_OUT => monitor_rx_frames(3 * 32 - 1 downto 2 * 32),
MONITOR_RX_BYTES_OUT => monitor_rx_bytes(3 * 32 - 1 downto 2 * 32),
MONITOR_TX_FRAMES_OUT => monitor_tx_frames(3 * 32 - 1 downto 2 * 32),
INCLUDE_DHCP => LINK_HAS_DHCP(1),
INCLUDE_ARP => LINK_HAS_ARP(1),
INCLUDE_PING => LINK_HAS_PING(1),
+ INCLUDE_FWD => LINK_HAS_FWD(1),
FRAME_BUFFER_SIZE => 1,
READOUT_BUFFER_SIZE => 4,
SLOWCTRL_BUFFER_SIZE => 2,
CFG_MAX_REPLY_SIZE_IN => cfg_max_reply,
CFG_AUTO_THROTTLE_IN => cfg_autothrottle,
CFG_THROTTLE_PAUSE_IN => cfg_throttle_pause,
+
+FWD_DATA_IN => FWD_DATA_IN(2 * 8 - 1 downto 1 * 8),
+FWD_DATA_VALID_IN => FWD_DATA_VALID_IN(1),
+FWD_SOP_IN => FWD_SOP_IN(1),
+FWD_EOP_IN => FWD_EOP_IN(1),
+FWD_READY_OUT => FWD_READY_OUT(1),
+FWD_FULL_OUT => FWD_FULL_OUT(1),
+
MONITOR_RX_FRAMES_OUT => monitor_rx_frames(2 * 32 - 1 downto 1 * 32),
MONITOR_RX_BYTES_OUT => monitor_rx_bytes(2 * 32 - 1 downto 1 * 32),
MONITOR_TX_FRAMES_OUT => monitor_tx_frames(2 * 32 - 1 downto 1 * 32),
INCLUDE_DHCP => LINK_HAS_DHCP(0),
INCLUDE_ARP => LINK_HAS_ARP(0),
INCLUDE_PING => LINK_HAS_PING(0),
+ INCLUDE_FWD => LINK_HAS_FWD(0),
FRAME_BUFFER_SIZE => 1,
READOUT_BUFFER_SIZE => 4,
SLOWCTRL_BUFFER_SIZE => 2,
CFG_MAX_REPLY_SIZE_IN => cfg_max_reply,
CFG_AUTO_THROTTLE_IN => cfg_autothrottle,
CFG_THROTTLE_PAUSE_IN => cfg_throttle_pause,
+
+FWD_DATA_IN => FWD_DATA_IN(1 * 8 - 1 downto 0 * 8),
+FWD_DATA_VALID_IN => FWD_DATA_VALID_IN(0),
+FWD_SOP_IN => FWD_SOP_IN(0),
+FWD_EOP_IN => FWD_EOP_IN(0),
+FWD_READY_OUT => FWD_READY_OUT(0),
+FWD_FULL_OUT => FWD_FULL_OUT(0),
+
MONITOR_RX_FRAMES_OUT => monitor_rx_frames(1 * 32 - 1 downto 0 * 32),
MONITOR_RX_BYTES_OUT => monitor_rx_bytes(1 * 32 - 1 downto 0 * 32),
MONITOR_TX_FRAMES_OUT => monitor_tx_frames(1 * 32 - 1 downto 0 * 32),
INCLUDE_DHCP : std_logic := '0';
INCLUDE_ARP : std_logic := '0';
INCLUDE_PING : std_logic := '0';
+ INCLUDE_FWD : std_logic := '0';
READOUT_BUFFER_SIZE : integer range 1 to 4;
SLOWCTRL_BUFFER_SIZE : integer range 1 to 4
MAKE_RESET_OUT : out std_logic;
+-- Forwarder
+FWD_DATA_IN : in std_logic_vector(7 downto 0);
+FWD_DATA_VALID_IN : in std_logic;
+FWD_SOP_IN : in std_logic;
+FWD_EOP_IN : in std_logic;
+FWD_READY_OUT : out std_logic;
+FWD_FULL_OUT : out std_logic;
+
-- signal to/from Host interface of TriSpeed MAC
TSM_HADDR_OUT : out std_logic_vector(7 downto 0);
TSM_HDATA_OUT : out std_logic_vector(7 downto 0);
INCLUDE_DHCP => INCLUDE_DHCP,
INCLUDE_ARP => INCLUDE_ARP,
INCLUDE_PING => INCLUDE_PING,
+ INCLUDE_FWD => INCLUDE_FWD,
READOUT_BUFFER_SIZE => READOUT_BUFFER_SIZE,
SLOWCTRL_BUFFER_SIZE => SLOWCTRL_BUFFER_SIZE
)
CFG_AUTO_THROTTLE_IN => CFG_AUTO_THROTTLE_IN,
CFG_THROTTLE_PAUSE_IN => CFG_THROTTLE_PAUSE_IN,
+ FWD_DATA_IN => FWD_DATA_IN,
+ FWD_DATA_VALID_IN => FWD_DATA_VALID_IN,
+ FWD_SOP_IN => FWD_SOP_IN,
+ FWD_EOP_IN => FWD_EOP_IN,
+ FWD_READY_OUT => FWD_READY_OUT,
+ FWD_FULL_OUT => FWD_FULL_OUT,
+
+
-- input for statistics from outside
STAT_DATA_IN => stat_data,
STAT_ADDR_IN => stat_addr,
INCLUDE_DHCP : std_logic := '0';
INCLUDE_ARP : std_logic := '0';
INCLUDE_PING : std_logic := '0';
+ INCLUDE_FWD : std_logic := '0';
READOUT_BUFFER_SIZE : integer range 1 to 4;
SLOWCTRL_BUFFER_SIZE : integer range 1 to 4
);
CFG_AUTO_THROTTLE_IN : in std_logic;
CFG_THROTTLE_PAUSE_IN : in std_logic_vector(15 downto 0);
+-- Forwarder
+FWD_DATA_IN : in std_logic_vector(7 downto 0);
+FWD_DATA_VALID_IN : in std_logic;
+FWD_SOP_IN : in std_logic;
+FWD_EOP_IN : in std_logic;
+FWD_READY_OUT : out std_logic;
+FWD_FULL_OUT : out std_logic;
+
-- input for statistics from outside
STAT_DATA_IN : in std_logic_vector(31 downto 0);
STAT_ADDR_IN : in std_logic_vector(7 downto 0);
FEE_READ_OUT <= '0';
end generate no_readout_gen;
+
+ fwd_gen : if INCLUDE_FWD = '1' generate
+
+ Forward : entity work.trb_net16_gbe_response_constructor_Forward
+ port map(
+ CLK => CLK,
+ RESET => RESET,
+
+ ---- INTERFACE
+ MY_MAC_IN => MY_MAC_IN,
+ MY_IP_IN => my_ip,
+ PS_DATA_IN => PS_DATA_IN,
+ PS_WR_EN_IN => PS_WR_EN_IN,
+ PS_ACTIVATE_IN => PS_PROTO_SELECT_IN(5),
+ PS_RESPONSE_READY_OUT => resp_ready(5),
+ PS_BUSY_OUT => busy(5),
+ PS_SELECTED_IN => selected(5),
+ PS_SRC_MAC_ADDRESS_IN => PS_SRC_MAC_ADDRESS_IN,
+ PS_DEST_MAC_ADDRESS_IN => PS_DEST_MAC_ADDRESS_IN,
+ PS_SRC_IP_ADDRESS_IN => PS_SRC_IP_ADDRESS_IN,
+ PS_DEST_IP_ADDRESS_IN => PS_DEST_IP_ADDRESS_IN,
+ PS_SRC_UDP_PORT_IN => PS_SRC_UDP_PORT_IN,
+ PS_DEST_UDP_PORT_IN => PS_DEST_UDP_PORT_IN,
+ TC_RD_EN_IN => TC_RD_EN_IN,
+ TC_DATA_OUT => tc_data(6 * 9 - 1 downto 5 * 9),
+ TC_FRAME_SIZE_OUT => tc_size(6 * 16 - 1 downto 5 * 16),
+ TC_FRAME_TYPE_OUT => tc_type(6 * 16 - 1 downto 5 * 16),
+ TC_IP_PROTOCOL_OUT => tc_ip_proto(6 * 8 - 1 downto 5 * 8),
+ TC_IDENT_OUT => tc_ident(6 * 16 - 1 downto 5 * 16),
+ TC_DEST_MAC_OUT => tc_mac(6 * 48 - 1 downto 5 * 48),
+ TC_DEST_IP_OUT => tc_ip(6 * 32 - 1 downto 5 * 32),
+ TC_DEST_UDP_OUT => tc_udp(6 * 16 - 1 downto 5 * 16),
+ TC_SRC_MAC_OUT => tc_src_mac(6 * 48 - 1 downto 5 * 48),
+ TC_SRC_IP_OUT => tc_src_ip(6 * 32 - 1 downto 5 * 32),
+ TC_SRC_UDP_OUT => tc_src_udp(6 * 16 - 1 downto 5 * 16),
+ RECEIVED_FRAMES_OUT => open,
+ SENT_FRAMES_OUT => open,
+
+ FWD_DATA_IN => FWD_DATA_IN,
+ FWD_DATA_VALID_IN => FWD_DATA_VALID_IN,
+ FWD_SOP_IN => FWD_SOP_IN,
+ FWD_EOP_IN => FWD_EOP_IN,
+ FWD_READY_OUT => FWD_READY_OUT,
+ FWD_FULL_OUT => FWD_FULL_OUT,
+
+
+
+ DEBUG_OUT => open
+ -- END OF INTERFACE
+ );
+
+ end generate fwd_gen;
+
+ no_fwd_gen : if INCLUDE_FWD = '0' generate
+ resp_ready(5) <= '0';
+ busy(5) <= '0';
+ end generate no_fwd_gen;
+
--stat_gen : if g_SIMULATE = 0 generate
--Stat : trb_net16_gbe_response_constructor_Stat
--generic map( STAT_ADDRESS_BASE => 10
if rising_edge(CLK) then
DEBUG_OUT(3 downto 0) <= select_state;
DEBUG_OUT(11 downto 4) <= std_logic_vector(to_unsigned(index, 8));
- DEBUG_OUT(19 downto 12) <= "000" & resp_ready; -- 4:0
- DEBUG_OUT(27 downto 20) <= "000" & busy; -- 4:0
+ DEBUG_OUT(19 downto 12) <= "00" & resp_ready; -- 4:0
+ DEBUG_OUT(27 downto 20) <= "00" & busy; -- 4:0
DEBUG_OUT(63 downto 28) <= (others => '0');
end if;
end process;
INCLUDE_DHCP : std_logic := '0';
INCLUDE_ARP : std_logic := '0';
INCLUDE_PING : std_logic := '0';
+ INCLUDE_FWD : std_logic := '0';
READOUT_BUFFER_SIZE : integer range 1 to 4;
SLOWCTRL_BUFFER_SIZE : integer range 1 to 4
--signal g_MY_MAC : std_logic_vector(47 downto 0) := x"001122334455";
constant c_MAX_FRAME_TYPES : integer range 1 to 16 := 2;
- constant c_MAX_PROTOCOLS : integer range 1 to 16 := 5; --5; --4; --5;
+ constant c_MAX_PROTOCOLS : integer range 1 to 16 := 6; --5; --4; --5;
constant c_MAX_IP_PROTOCOLS : integer range 1 to 16 := 2;
constant c_MAX_UDP_PROTOCOLS : integer range 1 to 16 := 4;
constant UDP_PROTOCOLS : udp_protos_a := (x"0044", x"6590", x"7530", x"7531"); --x"6590", x"7530", x"7531"); --x"61a8", x"7530", x"7531");
-- DHCP client, SCTRL, STATs
- component trb_net16_gbe_response_constructor_Forward is
- port(
- CLK : in std_logic; -- system clock
- RESET : in std_logic;
-
- -- INTERFACE
- MY_MAC_IN : in std_logic_vector(47 downto 0);
- MY_IP_IN : in std_logic_vector(31 downto 0);
- PS_DATA_IN : in std_logic_vector(8 downto 0);
- PS_WR_EN_IN : in std_logic;
- PS_ACTIVATE_IN : in std_logic;
- PS_RESPONSE_READY_OUT : out std_logic;
- PS_BUSY_OUT : out std_logic;
- PS_SELECTED_IN : in std_logic;
- PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0);
- PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0);
- TC_WR_EN_OUT : out std_logic;
- TC_DATA_OUT : out std_logic_vector(8 downto 0);
- TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
- TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0);
- TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
- TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0);
- TC_DEST_IP_OUT : out std_logic_vector(31 downto 0);
- TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0);
- TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0);
- TC_SRC_IP_OUT : out std_logic_vector(31 downto 0);
- TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0);
- TC_BUSY_IN : in std_logic;
- RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0);
- SENT_FRAMES_OUT : out std_logic_vector(15 downto 0);
- -- END OF INTERFACE
-
- -- debug
- DEBUG_OUT : out std_logic_vector(63 downto 0)
- );
- end component;
+-- component trb_net16_gbe_response_constructor_Forward is
+-- port (
+-- CLK : in std_logic; -- system clock
+-- RESET : in std_logic;
+--
+-- -- INTERFACE
+-- MY_MAC_IN : in std_logic_vector(47 downto 0);
+-- MY_IP_IN : in std_logic_vector(31 downto 0);
+-- PS_DATA_IN : in std_logic_vector(8 downto 0);
+-- PS_WR_EN_IN : in std_logic;
+-- PS_ACTIVATE_IN : in std_logic;
+-- PS_RESPONSE_READY_OUT : out std_logic;
+-- PS_BUSY_OUT : out std_logic;
+-- PS_SELECTED_IN : in std_logic;
+-- PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
+-- PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
+-- PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
+-- PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
+-- PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0);
+-- PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0);
+--
+-- TC_RD_EN_IN : in std_logic;
+-- TC_DATA_OUT : out std_logic_vector(8 downto 0);
+-- TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
+-- TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0);
+-- TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
+-- TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0);
+-- TC_DEST_IP_OUT : out std_logic_vector(31 downto 0);
+-- TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0);
+-- TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0);
+-- TC_SRC_IP_OUT : out std_logic_vector(31 downto 0);
+-- TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0);
+--
+-- TC_BUSY_IN : in std_logic;
+--
+-- RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0);
+-- SENT_FRAMES_OUT : out std_logic_vector(15 downto 0);
+-- -- END OF INTERFACE
+--
+-- FWD_DATA_IN : in std_logic_vector(7 downto 0);
+-- FWD_DATA_VALID_IN : in std_logic;
+-- FWD_SOP_IN : in std_logic;
+-- FWD_EOP_IN : in std_logic;
+-- FWD_READY_OUT : out std_logic;
+-- FWD_FULL_OUT : out std_logic;
+--
+-- -- debug
+-- DEBUG_OUT : out std_logic_vector(31 downto 0)
+-- );
+-- end component;
component trb_net16_gbe_response_constructor_ARP is
generic(STAT_ADDRESS_BASE : integer := 0
RESET : in std_logic;
-- INTERFACE
+ MY_MAC_IN : in std_logic_vector(47 downto 0);
+ MY_IP_IN : in std_logic_vector(31 downto 0);
PS_DATA_IN : in std_logic_vector(8 downto 0);
PS_WR_EN_IN : in std_logic;
PS_ACTIVATE_IN : in std_logic;
TC_DATA_OUT : out std_logic_vector(8 downto 0);
TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0);
- TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
+ TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
+ TC_IDENT_OUT : out std_logic_vector(15 downto 0);
TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0);
TC_DEST_IP_OUT : out std_logic_vector(31 downto 0);
TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0);
TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0);
TC_SRC_IP_OUT : out std_logic_vector(31 downto 0);
TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0);
-
- TC_BUSY_IN : in std_logic;
RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0);
SENT_FRAMES_OUT : out std_logic_vector(15 downto 0);
-- END OF INTERFACE
+ FWD_DST_MAC_OUT : out std_logic_vector(47 downto 0);
+ FWD_DST_IP_OUT : out std_logic_vector(31 downto 0);
+ FWD_DST_UDP_OUT : out std_logic_vector(15 downto 0);
+ FWD_DATA_IN : in std_logic_vector(7 downto 0);
+ FWD_DATA_VALID_IN : in std_logic;
+ FWD_SOP_IN : in std_logic;
+ FWD_EOP_IN : in std_logic;
+ FWD_READY_OUT : out std_logic;
+ FWD_FULL_OUT : out std_logic;
+
-- debug
DEBUG_OUT : out std_logic_vector(31 downto 0)
);
signal rec_frames : std_logic_vector(15 downto 0);
signal sent_frames : std_logic_vector(15 downto 0);
+signal local_eop : std_logic;
+
begin
DISSECT_MACHINE_PROC : process(CLK)
end if;
end process DISSECT_MACHINE_PROC;
-DISSECT_MACHINE : process(dissect_current_state, PS_WR_EN_IN, PS_ACTIVATE_IN, PS_DATA_IN, ff_q, ff_rd_lock, TC_BUSY_IN)
+DISSECT_MACHINE : process(dissect_current_state, FWD_SOP_IN, FWD_EOP_IN, ff_q, ff_rd_lock, PS_SELECTED_IN)
begin
case dissect_current_state is
when IDLE =>
state <= x"1";
- if (PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then
+ if (FWD_SOP_IN = '1') then
dissect_next_state <= SAVE;
else
dissect_next_state <= IDLE;
when SAVE =>
state <= x"2";
- if (PS_DATA_IN(8) = '1') then
+ if (FWD_EOP_IN = '1') then
dissect_next_state <= WAIT_FOR_LOAD;
else
dissect_next_state <= SAVE;
when WAIT_FOR_LOAD =>
state <= x"3";
- if (TC_BUSY_IN = '0') then
+ if (PS_SELECTED_IN = '0') then
dissect_next_state <= LOAD;
else
dissect_next_state <= WAIT_FOR_LOAD;
--PS_BUSY_OUT <= '1' when ff_wr_en = '1' else '0';
PS_BUSY_OUT <= '0' when dissect_current_state = IDLE else '1';
-ff_wr_en <= '1' when (PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') else '0';
+--ff_wr_en <= '1' when (PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') else '0';
+ff_wr_en <= '1' when (FWD_DATA_VALID_IN = '1') else '0';
+
+local_eop <= '1' when (dissect_current_state = SAVE and FWD_EOP_IN = '1' and FWD_DATA_VALID_IN = '1') else '0';
FF_RD_LOCK_PROC : process(CLK)
begin
FRAME_FIFO: fifo_4096x9
port map(
- Data => PS_DATA_IN,
+ Data(7 downto 0) => FWD_DATA_IN,
+ Data(8) => local_eop,
WrClock => CLK,
RdClock => CLK,
WrEn => ff_wr_en,
TC_FRAME_SIZE_OUT <= resp_bytes_ctr + x"1";
TC_FRAME_TYPE_OUT <= x"0008";
-TC_DEST_MAC_OUT <= x"9a680f201300";
-TC_DEST_IP_OUT <= x"0100a8c0";
-TC_DEST_UDP_OUT <= x"50c3";
-TC_SRC_MAC_OUT <= x"efbeefbe0000";
-TC_SRC_IP_OUT <= x"0b00a8c0";
-TC_SRC_UDP_OUT <= x"50c3";
+TC_DEST_MAC_OUT <= FWD_DST_MAC_OUT;
+TC_DEST_IP_OUT <= FWD_DST_IP_OUT;
+TC_DEST_UDP_OUT <= FWD_DST_UDP_OUT;
+TC_SRC_MAC_OUT <= MY_MAC_IN;
+TC_SRC_IP_OUT <= MY_IP_IN;
+TC_SRC_UDP_OUT <= FWD_DST_UDP_OUT;
TC_IP_PROTOCOL_OUT <= x"11";
+TC_IDENT_OUT <= x"6" & sent_frames(11 downto 0);
RESP_BYTES_CTR_PROC : process(CLK)
begin
if rising_edge(CLK) then
if (RESET = '1') or (dissect_current_state = IDLE) then
resp_bytes_ctr <= (others => '0');
- elsif (dissect_current_state = SAVE) then
+ elsif (dissect_current_state = SAVE and FWD_DATA_VALID_IN = '1') then
resp_bytes_ctr <= resp_bytes_ctr + x"1";
end if;
+
+ FWD_FULL_OUT <= ff_full;
+
+ if (dissect_current_state = IDLE) then
+ FWD_READY_OUT <= '1';
+ else
+ FWD_READY_OUT <= '0';
+ end if;
+
end if;
end process RESP_BYTES_CTR_PROC;
if rising_edge(CLK) then
if (RESET = '1') then
sent_frames <= (others => '0');
- elsif (dissect_current_state = WAIT_FOR_LOAD and TC_BUSY_IN = '0') then
+ elsif (dissect_current_state = WAIT_FOR_LOAD and PS_SELECTED_IN = '0') then
sent_frames <= sent_frames + x"1";
end if;
end if;
signal clk_sys, clk_125, reset, gsr_n, trigger : std_logic := '0';
signal busip0, busip1 : CTRLBUS_RX;
+ signal data : std_logic_vector(7 downto 0);
+ signal dv, sop, eop, ready : std_logic;
+
+ signal data_v : std_logic_vector(4 * 8 - 1 downto 0);
+ signal dv_v, sop_v, eop_v, ready_v : std_logic_vector(3 downto 0);
+
begin
uut : entity work.gbe_wrapper
generic map(
LINK_HAS_ARP => "1111",
LINK_HAS_DHCP => "1111",
LINK_HAS_READOUT => "1100",
- LINK_HAS_SLOWCTRL => "0000"
+ LINK_HAS_SLOWCTRL => "0000",
+ LINK_HAS_FWD => "1111"
)
port map(
CLK_SYS_IN => clk_sys,
GSC_REPLY_PACKET_NUM_IN => "111",
GSC_REPLY_READ_OUT => open,
GSC_BUSY_IN => '0',
+
+FWD_DATA_IN => data_v,
+FWD_DATA_VALID_IN => dv_v,
+FWD_SOP_IN => sop_v,
+FWD_EOP_IN => eop_v,
+FWD_READY_OUT => ready_v,
+FWD_FULL_OUT => open,
+
-- IP configuration
BUS_IP_RX => busip0,
BUS_IP_TX => open,
wait;
end process;
+
+
+dv_v <= dv & dv & dv & dv;
+sop_v <= sop & sop & sop & sop;
+eop_v <= eop & eop & eop & eop;
+data_v <= data & data & data & data;
+
+
+process
+begin
+ data <= x"00";
+ dv <= '0';
+ sop <= '0';
+ eop <= '0';
+
+ wait for 20 us;
+ wait until rising_edge(clk_sys);
+ sop <= '1';
+ dv <= '1';
+ data <= x"11";
+ wait until rising_edge(clk_sys);
+ sop <= '0';
+ for i in 0 to 9 loop
+ data <= data + x"1";
+ wait until rising_edge(clk_sys);
+ end loop;
+ data <= data + x"1";
+ eop <= '1';
+ wait until rising_edge(clk_sys);
+ eop <= '0';
+ dv <= '0';
+
+
+
+
+ wait;
+end process;
+
+
+
end;
\ No newline at end of file
jspc29 / trbnet.git / commitdiff