signal last_lsm_read : std_logic;
signal next_last_lsm_read : std_logic;
+ signal buf_HUB_MISMATCH_PATTERN : std_logic_vector(31 downto 0);
+
type counter8b_t is array (0 to 15) of unsigned(7 downto 0);
signal received_retransmit_requests : counter8b_t;
signal sent_retransmit_requests : counter8b_t;
STAT_ERRORBITS => HUB_STAT_ERRORBITS((i+1)*32-1 downto i*32),
STAT_ALL_ERRORBITS => buf_HUB_ALL_ERROR_BITS((i+1)*32*16-1 downto i*32*16),
STAT_FSM => stat_ipu_fsm,
+ STAT_MISMATCH => buf_HUB_MISMATCH_PATTERN(31 downto 0),
CTRL_TIMEOUT_TIME => current_timeout_value(i),--HUB_CTRL_TIMEOUT_TIME(i*4+3 downto i*4),
CTRL_activepoints => HUB_CTRL_final_activepoints((i+1)*32-1 downto i*32),
CTRL_TIMER_TICK(0) => timer_us_tick,
buf_HC_STAT_REGS(7*32+31 downto 7*32) <= stat_ipu_fsm;
buf_HC_STAT_REGS(15*32-1 downto 8*32) <= (others => '0');
buf_HC_STAT_REGS(16*32+MII_NUMBER-1 downto 16*32) <= mii_error(MII_NUMBER-1 downto 0);
- buf_HC_STAT_REGS(31*32+31 downto 16*32+MII_NUMBER) <= (others => '0');
+ buf_HC_STAT_REGS(30*32+31 downto 16*32+MII_NUMBER) <= (others => '0');
+ buf_HC_STAT_REGS(31*32+31 downto 31*32) <= buf_HUB_MISMATCH_PATTERN;
buf_HC_STAT_REGS(35*32+31 downto 32*32) <= HUB_STAT_ERRORBITS;
buf_HC_STAT_REGS(63*32+31 downto 36*32) <= (others => '0');
STAT_ERRORBITS : out std_logic_vector (31 downto 0);
STAT_ALL_ERRORBITS : out std_logic_vector (16*32-1 downto 0);
STAT_FSM : out std_logic_vector (31 downto 0);
+ STAT_MISMATCH : out std_logic_vector (31 downto 0);
CTRL_TIMEOUT_TIME : in std_logic_vector (15 downto 0);
CTRL_activepoints : in std_logic_vector (31 downto 0) := (others => '1');
CTRL_TIMER_TICK : in std_logic_vector (1 downto 0)
STAT_ERRORBITS : out std_logic_vector (31 downto 0);
STAT_ALL_ERRORBITS : out std_logic_vector (16*32-1 downto 0);
STAT_FSM : out std_logic_vector (31 downto 0);
+ STAT_MISMATCH : out std_logic_vector (31 downto 0);
CTRL_TIMEOUT_TIME : in std_logic_vector (15 downto 0);
CTRL_activepoints : in std_logic_vector (31 downto 0) := (others => '1');
CTRL_TIMER_TICK : in std_logic_vector (1 downto 0)
signal reply_fsm_statebits : std_logic_vector(3 downto 0);
signal last_locked : std_logic;
+ signal mismatch_pattern : std_logic_vector(31 downto 0);
begin
----------------------------------
tmp_number := '0';
if reply_compare_start = '1' then
if dhdr_addr = "100" then --upper part
+ mismatch_pattern(31 downto 16) <= (others => '0');
for i in 0 to POINT_NUMBER-1 loop
if dhdr_data(i*16+12) = '0' and reply_adder_val_enable(i) = '1' then
tmp_pack := '0';
end if;
if dhdr_data(i*16+7 downto i*16) /= evt_random_code and reply_adder_val_enable(i) = '1' then
tmp_code := '1';
+ mismatch_pattern(i+16) <= '1';
end if;
end loop;
enable_packing <= tmp_pack;
evt_code_mismatch <= tmp_code;
reply_compare_finished <= '1';
elsif dhdr_addr = "101" then
+ mismatch_pattern(15 downto 0) <= (others => '0');
for i in 0 to POINT_NUMBER-1 loop
if dhdr_data(i*16+15 downto i*16) /= evt_number and reply_adder_val_enable(i) = '1' then
tmp_number := '1';
+ mismatch_pattern(i) <= '1';
end if;
end loop;
evt_number_mismatch <= tmp_number;
else
STAT_POINTS_locked(POINT_NUMBER-1 downto 0) <= (others => '0');
end if;
- if locked = '0' and last_locked = '1' then
- STAT_ERRORBITS <= REPLY_combined_trm_F1 & REPLY_combined_trm_F2;
+ if current_state = SENDING_REPLY_TRM and packet_counter = c_F1 then
+ STAT_ERRORBITS(31 downto 16) <= comb_REPLY_POOL_DATA;
+ elsif current_state = SENDING_REPLY_TRM and packet_counter = c_F2 then
+ STAT_ERRORBITS(15 downto 0) <= comb_REPLY_POOL_DATA;
end if;
end if;
end process;
STAT_FSM(31 downto 16)<= (others => '0');
STAT_locked <= locked;
+ STAT_MISMATCH <= mismatch_pattern;
end architecture;