--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="pll_in120_out624" module="PLL" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2022 04 12 09:51:29.322" version="5.8" type="Module" synthesis="synplify" source_format="VHDL">
+ <Package>
+ <File name="pll_in120_out624.lpc" type="lpc" modified="2022 04 12 09:51:28.000"/>
+ <File name="pll_in120_out624.vhd" type="top_level_vhdl" modified="2022 04 12 09:51:28.000"/>
+ <File name="pll_in120_out624_tmpl.vhd" type="template_vhdl" modified="2022 04 12 09:51:28.000"/>
+ </Package>
+</DiamondModule>
--- /dev/null
+[Device]
+Family=latticeecp3
+PartType=LFE3-150EA
+PartName=LFE3-150EA-8FN1156C
+SpeedGrade=8
+Package=FPBGA1156
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=PLL
+CoreRevision=5.8
+ModuleName=pll_in120_out624
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=04/12/2022
+Time=09:51:28
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=None
+Order=None
+IO=0
+Type=ehxpllb
+mode=normal
+IFrq=120
+Div=25
+ClkOPBp=0
+Post=16
+U_OFrq=62.4
+OP_Tol=0.0
+OFrq=62.400000
+DutyTrimP=Rising
+DelayMultP=0
+fb_mode=CLKOP
+Mult=13
+Phase=0.0
+Duty=8
+DelayMultS=0
+DPD=50% Duty
+DutyTrimS=Rising
+DelayMultD=0
+ClkOSDelay=0
+PhaseDuty=Static
+CLKOK_INPUT=CLKOP
+SecD=2
+U_KFrq=50
+OK_Tol=0.0
+KFrq=
+ClkRst=0
+PCDR=0
+FINDELA=0
+VcoRate=
+Bandwidth=0.526818
+;DelayControl=No
+EnCLKOS=0
+ClkOSBp=0
+EnCLKOK=0
+ClkOKBp=0
+enClkOK2=0
+
+[Command]
+cmd_line= -w -n pll_in120_out624 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 120 -phase_cntl STATIC -fclkop 62.4 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw
--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.12.1.454
+-- Module Version: 5.7
+--/opt/lattice/diamond/3.12/ispfpga/bin/lin64/scuba -w -n pll_in120_out624 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 120 -phase_cntl STATIC -fclkop 62.4 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw
+
+-- Tue Apr 12 09:51:28 2022
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity pll_in120_out624 is
+ port (
+ CLK: in std_logic;
+ CLKOP: out std_logic;
+ LOCK: out std_logic);
+end pll_in120_out624;
+
+architecture Structure of pll_in120_out624 is
+
+ -- internal signal declarations
+ signal CLKOP_t: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component EHXPLLF
+ generic (FEEDBK_PATH : in String; CLKOK_INPUT : in String;
+ DELAY_PWD : in String; DELAY_VAL : in Integer;
+ CLKOS_TRIM_DELAY : in Integer;
+ CLKOS_TRIM_POL : in String;
+ CLKOP_TRIM_DELAY : in Integer;
+ CLKOP_TRIM_POL : in String; CLKOK_BYPASS : in String;
+ CLKOS_BYPASS : in String; CLKOP_BYPASS : in String;
+ PHASE_DELAY_CNTL : in String; DUTY : in Integer;
+ PHASEADJ : in String; CLKOK_DIV : in Integer;
+ CLKOP_DIV : in Integer; CLKFB_DIV : in Integer;
+ CLKI_DIV : in Integer; FIN : in String);
+ port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic;
+ RSTK: in std_logic; WRDEL: in std_logic; DRPAI3: in std_logic;
+ DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic;
+ DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic;
+ DFPAI0: in std_logic; FDA3: in std_logic; FDA2: in std_logic;
+ FDA1: in std_logic; FDA0: in std_logic; CLKOP: out std_logic;
+ CLKOS: out std_logic; CLKOK: out std_logic; CLKOK2: out std_logic;
+ LOCK: out std_logic; CLKINTFB: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ attribute FREQUENCY_PIN_CLKOP : string;
+ attribute FREQUENCY_PIN_CLKI : string;
+ attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "62.400000";
+ attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "120.000000";
+ attribute syn_keep : boolean;
+ attribute NGD_DRC_MASK : integer;
+ attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+ -- component instantiation statements
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ PLLInst_0: EHXPLLF
+ generic map (FEEDBK_PATH=> "CLKOP", CLKOK_BYPASS=> "DISABLED",
+ CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED",
+ CLKOK_INPUT=> "CLKOP", DELAY_PWD=> "DISABLED", DELAY_VAL=> 0,
+ CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "RISING",
+ CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "RISING",
+ PHASE_DELAY_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0",
+ CLKOK_DIV=> 2, CLKOP_DIV=> 16, CLKFB_DIV=> 13, CLKI_DIV=> 25,
+ FIN=> "120.000000")
+ port map (CLKI=>CLK, CLKFB=>CLKOP_t, RST=>scuba_vlo,
+ RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo,
+ DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo,
+ DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo,
+ DFPAI0=>scuba_vlo, FDA3=>scuba_vlo, FDA2=>scuba_vlo,
+ FDA1=>scuba_vlo, FDA0=>scuba_vlo, CLKOP=>CLKOP_t,
+ CLKOS=>open, CLKOK=>open, CLKOK2=>open, LOCK=>LOCK,
+ CLKINTFB=>open);
+
+ CLKOP <= CLKOP_t;
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of pll_in120_out624 is
+ for Structure
+ for all:EHXPLLF use entity ecp3.EHXPLLF(V); end for;
+ for all:VLO use entity ecp3.VLO(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="pll_in200_out120" module="PLL" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2022 04 12 09:51:04.187" version="5.8" type="Module" synthesis="synplify" source_format="VHDL">
+ <Package>
+ <File name="pll_in200_out120.lpc" type="lpc" modified="2022 04 12 09:51:02.000"/>
+ <File name="pll_in200_out120.vhd" type="top_level_vhdl" modified="2022 04 12 09:51:02.000"/>
+ <File name="pll_in200_out120_tmpl.vhd" type="template_vhdl" modified="2022 04 12 09:51:02.000"/>
+ </Package>
+</DiamondModule>
--- /dev/null
+[Device]
+Family=latticeecp3
+PartType=LFE3-150EA
+PartName=LFE3-150EA-8FN1156C
+SpeedGrade=8
+Package=FPBGA1156
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=PLL
+CoreRevision=5.8
+ModuleName=pll_in200_out120
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=04/12/2022
+Time=09:51:02
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=None
+Order=None
+IO=0
+Type=ehxpllb
+mode=normal
+IFrq=200
+Div=5
+ClkOPBp=0
+Post=8
+U_OFrq=120
+OP_Tol=0.0
+OFrq=120.000000
+DutyTrimP=Rising
+DelayMultP=0
+fb_mode=CLKOP
+Mult=3
+Phase=0.0
+Duty=8
+DelayMultS=0
+DPD=50% Duty
+DutyTrimS=Rising
+DelayMultD=0
+ClkOSDelay=0
+PhaseDuty=Static
+CLKOK_INPUT=CLKOP
+SecD=2
+U_KFrq=50
+OK_Tol=0.0
+KFrq=
+ClkRst=0
+PCDR=0
+FINDELA=0
+VcoRate=
+Bandwidth=1.461042
+;DelayControl=No
+EnCLKOS=0
+ClkOSBp=0
+EnCLKOK=0
+ClkOKBp=0
+enClkOK2=0
+
+[Command]
+cmd_line= -w -n pll_in200_out120 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -fclkop 120 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw
--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.12.1.454
+-- Module Version: 5.7
+--/opt/lattice/diamond/3.12/ispfpga/bin/lin64/scuba -w -n pll_in200_out120 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -fclkop 120 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw
+
+-- Tue Apr 12 09:51:02 2022
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity pll_in200_out120 is
+ port (
+ CLK: in std_logic;
+ CLKOP: out std_logic;
+ LOCK: out std_logic);
+end pll_in200_out120;
+
+architecture Structure of pll_in200_out120 is
+
+ -- internal signal declarations
+ signal CLKOP_t: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component EHXPLLF
+ generic (FEEDBK_PATH : in String; CLKOK_INPUT : in String;
+ DELAY_PWD : in String; DELAY_VAL : in Integer;
+ CLKOS_TRIM_DELAY : in Integer;
+ CLKOS_TRIM_POL : in String;
+ CLKOP_TRIM_DELAY : in Integer;
+ CLKOP_TRIM_POL : in String; CLKOK_BYPASS : in String;
+ CLKOS_BYPASS : in String; CLKOP_BYPASS : in String;
+ PHASE_DELAY_CNTL : in String; DUTY : in Integer;
+ PHASEADJ : in String; CLKOK_DIV : in Integer;
+ CLKOP_DIV : in Integer; CLKFB_DIV : in Integer;
+ CLKI_DIV : in Integer; FIN : in String);
+ port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic;
+ RSTK: in std_logic; WRDEL: in std_logic; DRPAI3: in std_logic;
+ DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic;
+ DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic;
+ DFPAI0: in std_logic; FDA3: in std_logic; FDA2: in std_logic;
+ FDA1: in std_logic; FDA0: in std_logic; CLKOP: out std_logic;
+ CLKOS: out std_logic; CLKOK: out std_logic; CLKOK2: out std_logic;
+ LOCK: out std_logic; CLKINTFB: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ attribute FREQUENCY_PIN_CLKOP : string;
+ attribute FREQUENCY_PIN_CLKI : string;
+ attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "120.000000";
+ attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "200.000000";
+ attribute syn_keep : boolean;
+ attribute NGD_DRC_MASK : integer;
+ attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+ -- component instantiation statements
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ PLLInst_0: EHXPLLF
+ generic map (FEEDBK_PATH=> "CLKOP", CLKOK_BYPASS=> "DISABLED",
+ CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED",
+ CLKOK_INPUT=> "CLKOP", DELAY_PWD=> "DISABLED", DELAY_VAL=> 0,
+ CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "RISING",
+ CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "RISING",
+ PHASE_DELAY_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0",
+ CLKOK_DIV=> 2, CLKOP_DIV=> 8, CLKFB_DIV=> 3, CLKI_DIV=> 5,
+ FIN=> "200.000000")
+ port map (CLKI=>CLK, CLKFB=>CLKOP_t, RST=>scuba_vlo,
+ RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo,
+ DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo,
+ DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo,
+ DFPAI0=>scuba_vlo, FDA3=>scuba_vlo, FDA2=>scuba_vlo,
+ FDA1=>scuba_vlo, FDA0=>scuba_vlo, CLKOP=>CLKOP_t,
+ CLKOS=>open, CLKOK=>open, CLKOK2=>open, LOCK=>LOCK,
+ CLKINTFB=>open);
+
+ CLKOP <= CLKOP_t;
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of pll_in200_out120 is
+ for Structure
+ for all:EHXPLLF use entity ecp3.EHXPLLF(V); end for;
+ for all:VLO use entity ecp3.VLO(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="pll_in200_out622" module="PLL" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2022 04 12 15:49:28.670" version="5.8" type="Module" synthesis="synplify" source_format="VHDL">
+ <Package>
+ <File name="pll_in200_out622.lpc" type="lpc" modified="2022 04 12 15:49:12.000"/>
+ <File name="pll_in200_out622.vhd" type="top_level_vhdl" modified="2022 04 12 15:49:12.000"/>
+ <File name="pll_in200_out622_tmpl.vhd" type="template_vhdl" modified="2022 04 12 15:49:12.000"/>
+ </Package>
+</DiamondModule>
--- /dev/null
+[Device]
+Family=latticeecp3
+PartType=LFE3-150EA
+PartName=LFE3-150EA-8FN1156C
+SpeedGrade=8
+Package=FPBGA1156
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=PLL
+CoreRevision=5.8
+ModuleName=pll_in200_out622
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=04/12/2022
+Time=15:49:12
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=None
+Order=None
+IO=0
+Type=ehxpllb
+mode=normal
+IFrq=200
+Div=45
+ClkOPBp=0
+Post=16
+U_OFrq=62.2
+OP_Tol=0.1
+OFrq=62.222222
+DutyTrimP=Rising
+DelayMultP=0
+fb_mode=CLKOP
+Mult=14
+Phase=0.0
+Duty=8
+DelayMultS=0
+DPD=50% Duty
+DutyTrimS=Rising
+DelayMultD=0
+ClkOSDelay=0
+PhaseDuty=Static
+CLKOK_INPUT=CLKOP
+SecD=2
+U_KFrq=50
+OK_Tol=0.0
+KFrq=
+ClkRst=0
+PCDR=0
+FINDELA=0
+VcoRate=
+Bandwidth=0.489188
+;DelayControl=No
+EnCLKOS=0
+ClkOSBp=0
+EnCLKOK=0
+ClkOKBp=0
+enClkOK2=0
+
+[Command]
+cmd_line= -w -n pll_in200_out622 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -fclkop 62.2 -fclkop_tol 0.1 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw
--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.12.1.454
+-- Module Version: 5.7
+--/opt/lattice/diamond/3.12/ispfpga/bin/lin64/scuba -w -n pll_in200_out622 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -fclkop 62.2 -fclkop_tol 0.1 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw
+
+-- Tue Apr 12 15:49:12 2022
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity pll_in200_out622 is
+ port (
+ CLK: in std_logic;
+ CLKOP: out std_logic;
+ LOCK: out std_logic);
+end pll_in200_out622;
+
+architecture Structure of pll_in200_out622 is
+
+ -- internal signal declarations
+ signal CLKOP_t: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component EHXPLLF
+ generic (FEEDBK_PATH : in String; CLKOK_INPUT : in String;
+ DELAY_PWD : in String; DELAY_VAL : in Integer;
+ CLKOS_TRIM_DELAY : in Integer;
+ CLKOS_TRIM_POL : in String;
+ CLKOP_TRIM_DELAY : in Integer;
+ CLKOP_TRIM_POL : in String; CLKOK_BYPASS : in String;
+ CLKOS_BYPASS : in String; CLKOP_BYPASS : in String;
+ PHASE_DELAY_CNTL : in String; DUTY : in Integer;
+ PHASEADJ : in String; CLKOK_DIV : in Integer;
+ CLKOP_DIV : in Integer; CLKFB_DIV : in Integer;
+ CLKI_DIV : in Integer; FIN : in String);
+ port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic;
+ RSTK: in std_logic; WRDEL: in std_logic; DRPAI3: in std_logic;
+ DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic;
+ DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic;
+ DFPAI0: in std_logic; FDA3: in std_logic; FDA2: in std_logic;
+ FDA1: in std_logic; FDA0: in std_logic; CLKOP: out std_logic;
+ CLKOS: out std_logic; CLKOK: out std_logic; CLKOK2: out std_logic;
+ LOCK: out std_logic; CLKINTFB: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ attribute FREQUENCY_PIN_CLKOP : string;
+ attribute FREQUENCY_PIN_CLKI : string;
+ attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "62.222222";
+ attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "200.000000";
+ attribute syn_keep : boolean;
+ attribute NGD_DRC_MASK : integer;
+ attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+ -- component instantiation statements
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ PLLInst_0: EHXPLLF
+ generic map (FEEDBK_PATH=> "CLKOP", CLKOK_BYPASS=> "DISABLED",
+ CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED",
+ CLKOK_INPUT=> "CLKOP", DELAY_PWD=> "DISABLED", DELAY_VAL=> 0,
+ CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "RISING",
+ CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "RISING",
+ PHASE_DELAY_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0",
+ CLKOK_DIV=> 2, CLKOP_DIV=> 16, CLKFB_DIV=> 14, CLKI_DIV=> 45,
+ FIN=> "200.000000")
+ port map (CLKI=>CLK, CLKFB=>CLKOP_t, RST=>scuba_vlo,
+ RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo,
+ DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo,
+ DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo,
+ DFPAI0=>scuba_vlo, FDA3=>scuba_vlo, FDA2=>scuba_vlo,
+ FDA1=>scuba_vlo, FDA0=>scuba_vlo, CLKOP=>CLKOP_t,
+ CLKOS=>open, CLKOK=>open, CLKOK2=>open, LOCK=>LOCK,
+ CLKINTFB=>open);
+
+ CLKOP <= CLKOP_t;
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of pll_in200_out622 is
+ for Structure
+ for all:EHXPLLF use entity ecp3.EHXPLLF(V); end for;
+ for all:VLO use entity ecp3.VLO(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport_oreg.vhd"
add_file -vhdl -lib work "../../trbnet/lattice/ecp3/ram_18x256_oreg.vhd"
-
#Flash & Reload, Tools
add_file -vhdl -lib work "../../trbnet/special/slv_register.vhd"
add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_all_125M_RS.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_all_200M_RS.vhd"
+add_file -vhdl -lib work "../../trbnet/special/phaser.vhd"
+add_file -vhdl -lib work "../../trbnet/special/phaser_core.vhd"
+
+add_file -vhdl -lib work "../../trb3sc/cores/pll_in200_out120.vhd"
+add_file -vhdl -lib work "../../trb3sc/cores/pll_in120_out624.vhd"
+add_file -vhdl -lib work "../../trbnet/special/ddmtd.vhd"
+add_file -vhdl -lib work "../../trbnet/special/deglitch.vhd"
+
#TrbNet Endpoint
add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd"
use work.med_sync_define_RS.all;
use work.cts_pkg.all;
+library ecp3;
+use ecp3.components.all;
+
entity trb3sc_cts is
port(
CLK_SUPPL_PCLK : in std_logic; --125 MHz for GbE
CLK_CORE_PCLK : in std_logic; --Main Oscillator
CLK_EXT_PLL_LEFT : in std_logic; --External Clock
--Additional IO
--- HDR_IO : inout std_logic_vector(10 downto 1);
+ HDR_IO : inout std_logic_vector(10 downto 1);
BACK_LVDS : inout std_logic_vector( 1 downto 0);
BACK_GPIO : inout std_logic_vector( 3 downto 0);
SPARE_IN : in std_logic_vector( 1 downto 0);
signal init_quad : std_logic;
signal link_clock : std_logic;
+-- signal phaser_data : std_logic_vector(31 downto 0);
+ signal ping_i : std_logic;
+ signal ping_q : std_logic;
+ signal pong_i : std_logic;
+ signal pong_q : std_logic;
+ signal pong_clk_i : std_logic;
+
+ signal clk_120m : std_logic;
+ signal clk_sample : std_logic;
+
+ signal ping_stretched_i : std_logic;
+ signal ping_stretched_q : std_logic;
+ signal pong_stretched_i : std_logic;
+ signal pong_stretched_q : std_logic;
+ signal start_ping_i : std_logic;
+ signal start_ping_q : std_logic;
+ signal start_pong_i : std_logic;
+ signal start_pong_q : std_logic;
+ signal toggle_i : std_logic;
+ signal toggle_q : std_logic;
+ signal beat_i : std_logic;
+ signal beat_q : std_logic;
+ signal tristate_pings_i : std_logic;
+
begin
THE_TIME_COUNTER_PROC: process( clk_full_osc )
RX_RST_WORD_OUT => open,
TX_RST_IN => tx_rst_i,
TX_RST_WORD_IN => send_rst_word_i,
+ -- delay measurement
+ PING_OUT(2 downto 0) => open,
+ PING_OUT(3) => ping_i,
+ PONG_OUT(2 downto 0) => open,
+ PONG_OUT(3) => pong_i,
+ PONG_CLK_OUT(2 downto 0) => open,
+ PONG_CLK_OUT(3) => pong_clk_i,
-- sync operation
WORD_SYNC_IN => '1',
WORD_SYNC_OUT => word_sync_i,
TX_PCS_RST_IN => tx_pcs_rst_i,
SYNC_TX_PLL_IN => sync_tx_quad_i,
LINK_TX_READY_IN => link_tx_ready_i,
- DESTROY_LINK_IN(2 downto 0) => (others => '0'),
- DESTROY_LINK_IN(3) => destroy_link_i,
+ DISABLE_LINK_IN(2 downto 0) => (others => '0'),
+ DISABLE_LINK_IN(3) => destroy_link_i,
WAP_REQUESTED_IN => wap_requested_i,
--SFP Connection
SD_PRSNT_N_IN(2 downto 0) => (others => '1'),
CTRL_DEBUG => open,
DEBUG_OUT => debug_i
);
-
+
master_clk_i <= link_clock;
THE_MAIN_TX_RST: main_tx_reset_RS
PCSSW <= "01001110"; --SFP2 on B3, AddOn on D1
-- just for testing
- tx_dlm_i <= dlm_send_qq;
- send_dlm_word_i <= std_logic_vector(dlm_tag_ctr);
- enable_dlm_i <= test_reg(31);
- send_rst_i <= test_reg(30);
- destroy_link_i <= test_reg(24); -- ONLY FOR TESTING
- send_rst_word_i <= test_reg(15 downto 8); -- ONLY FOR TESTING
- wap_requested_i <= test_reg(3 downto 0); -- ONLY FOR TESTING
+ tx_dlm_i <= dlm_send_qq;
+ send_dlm_word_i <= std_logic_vector(dlm_tag_ctr);
+ enable_dlm_i <= test_reg(31);
+ send_rst_i <= test_reg(30);
+ tristate_pings_i <= test_reg(25);
+ destroy_link_i <= test_reg(24); -- ONLY FOR TESTING
+ send_rst_word_i <= test_reg(15 downto 8); -- ONLY FOR TESTING
+ wap_requested_i <= test_reg(3 downto 0); -- ONLY FOR TESTING
-- LED feedback
LED_WHITE(1) <= not std_logic(dlm_tag_ctr(7));
-- send on rising edge of signal
tx_rst_x <= not pulse_detect(7) and pulse_detect(6);
+--------------------------------------------------------------------------------------------------------
+--------------------------------------------------------------------------------------------------------
+ THE_FIRST_PLL: entity pll_in200_out120
+ port map(
+ CLK => CLK_CORE_PCLK,
+ CLKOP => clk_120m,
+ LOCK => open
+ );
+
+ THE_SECOND_PLL: entity pll_in120_out624
+ port map(
+ CLK => clk_120m,
+ CLKOP => clk_sample,
+ LOCK => open
+ );
+
+ THE_DDMTD: entity ddmtd
+ port map(
+ AUXCLK => clk_sample,
+ RESET => reset_i,
+ PING_IN => HDR_IO(1),
+ PONG_IN => HDR_IO(3),
+ PING_OUT => ping_stretched_i,
+ PONG_OUT => pong_stretched_i,
+ START_PING_OUT => start_ping_i,
+ START_PONG_OUT => start_pong_i,
+ TOGGLE_OUT => toggle_i,
+ BEAT_OUT => beat_i
+ );
+
+ -- Output registers
+ THE_PING_OR: OFS1P3DX
+ port map(
+ SP => '1',
+ CD => '0',
+ SCLK => master_clk_i,
+ D => ping_i,
+ Q => ping_q
+ );
+
+ THE_PONG_OR: OFS1P3DX
+ port map(
+ SP => '1',
+ CD => '0',
+ SCLK => pong_clk_i,
+ D => pong_i,
+ Q => pong_q
+ );
+
+ THE_PING_STRETCHED_OR: OFS1P3DX
+ port map(
+ SP => '1',
+ CD => '0',
+ SCLK => clk_sample,
+ D => ping_stretched_i,
+ Q => ping_stretched_q
+ );
+
+ THE_PONG_STRETCHED_OR: OFS1P3DX
+ port map(
+ SP => '1',
+ CD => '0',
+ SCLK => clk_sample,
+ D => pong_stretched_i,
+ Q => pong_stretched_q
+ );
+
+ THE_START_PING_OR: OFS1P3DX
+ port map(
+ SP => '1',
+ CD => '0',
+ SCLK => clk_sample,
+ D => start_ping_i,
+ Q => start_ping_q
+ );
+
+ THE_START_PONG_OR: OFS1P3DX
+ port map(
+ SP => '1',
+ CD => '0',
+ SCLK => clk_sample,
+ D => start_pong_i,
+ Q => start_pong_q
+ );
+
+ THE_BEAT_OR: OFS1P3DX
+ port map(
+ SP => '1',
+ CD => '0',
+ SCLK => clk_sample,
+ D => beat_i,
+ Q => beat_q
+ );
+
+ THE_TOGGLE_OR: OFS1P3DX
+ port map(
+ SP => '1',
+ CD => '0',
+ SCLK => clk_sample,
+ D => toggle_i,
+ Q => toggle_q
+ );
+
+HDR_IO(1) <= ping_q when (tristate_pings_i = '0') else 'Z';
+HDR_IO(3) <= pong_q when (tristate_pings_i = '0') else 'Z';
+HDR_IO(5) <= ping_stretched_q;
+HDR_IO(7) <= pong_stretched_q;
+HDR_IO(9) <= beat_q;
+
+HDR_IO(2) <= '0'; -- reserved for testing calibration
+HDR_IO(4) <= '0'; -- reserved for testing calibration
+HDR_IO(6) <= start_ping_q;
+HDR_IO(8) <= start_pong_q;
+HDR_IO(10) <= toggle_q;
+--------------------------------------------------------------------------------------------------------
+--------------------------------------------------------------------------------------------------------
+
end generate;
---------------------------------------------------------------------------
bussci3_tx.unknown <= bussci3_rx.read or bussci3_rx.write when rising_edge(clk_sys);
-- can be used for simple readback on debugging
--- bussci3_tx.data <= phaser_data;
--- bussci3_tx.ack <= bussci3_rx.read or bussci3_rx.write when rising_edge(clk_sys);
--- bussci3_tx.nack <= '0';
--- bussci3_tx.unknown <= '0';
-
+ --bussci3_tx.data <= phaser_data;
+ --bussci3_tx.ack <= bussci3_rx.read or bussci3_rx.write when rising_edge(clk_sys);
+ --bussci3_tx.nack <= '0';
+ --bussci3_tx.unknown <= '0';
---------------------------------------------------------------------------
-- PCSD: GbE
RX_RST_WORD_OUT => send_rst_word_i,
TX_RST_IN => send_rst_i, --'0',
TX_RST_WORD_IN => send_rst_word_i, --x"00",
+ -- delay measurement
+ PING_OUT(2 downto 0) => open,
+ PING_OUT(3) => open,
+ PONG_OUT(2 downto 0) => open,
+ PONG_OUT(3) => open,
+ PONG_CLK_OUT(2 downto 0) => open,
+ PONG_CLK_OUT(3) => open,
-- sync operation
WORD_SYNC_IN => word_sync_i,
WORD_SYNC_OUT => word_sync_i,
TX_PCS_RST_IN => tx_pcs_rst_i,
SYNC_TX_PLL_IN => sync_tx_quad_i,
LINK_TX_READY_IN => link_tx_ready_i,
- DESTROY_LINK_IN => (others => '0'),
+ DISABLE_LINK_IN => (others => '0'),
WAP_REQUESTED_IN => x"0",
--SFP Connection
SD_PRSNT_N_IN(2 downto 0) => (others => '1'),
jspc29 / trb3sc.git / commitdiff