bugs

diff --git a/cts.tex b/cts.tex
index e49029fff5bfc87182bbcc2a89c693c659e0db59..9d78ebdffc0ce622f2a2fa4a08b58cba52f65e26 100644 (file)
--- a/cts.tex
+++ b/cts.tex
@@ -80,8 +80,9 @@ For all registers described in this subsection refer to the Fig.\ref{cts_logic}
   \item [0xA0D9] -- Length of the beam itself. After this time the beam inhibit signal is set till next START BEAM signal - $value*100ns$ 
   \item [0xA0DA] -- use different parts of the START detector for histograms
     \begin{description}
-    \item [Bit 1 -- 0] when '00' inputs 7 - 0 from the Start detector are used, '01' 11 - 4, '10' 15 - 8
-    \item [Bit 3 -- 2] when '00' inputs 23 - 16 from the Start detector are used, '01' 27 - 20, '10' 31 - 24
+    \item [Bit 1 -- 0] when '00' inputs 7 - 0 from the Start detector are used for histogramming, '01' 11 - 4, '10' 15 - 8 
+    \item [Bit 3 -- 2] when '00' inputs 23 - 16 (7-0 from perperdicular stripes) from the Start detector are used for histogramming, '01' 27 - 20, '10' 31 - 24 
+    \item [Bit 7 -- 6] when '00' inputs 7 - 0 from the Start detector are used for trigger logic, '01' 11 - 4, '10' 15 - 8 
     \end{description}
   \item [0xA0DD -- 0xA0DB] Delay the signals with large values  - $value * 5\,ns$
   \item [0xA0E2 -- 0xA0DE] Set width of the signals - $5 + value * 4\,ns$
@@ -242,7 +243,7 @@ For all registers described in this subsection refer to the Fig.\ref{cts_logic}
  \begin{description}
  \item[0] There is a LVL1 busy  based on LVL1 information sent back from the endpoints
  \end{description}
- \item [0xA100 - 0xA100 + 26*500] The memory reserved for the histograms. 500 is number of samples per each histogram. The histograms are created in the SCM FPGA (1) see fig. \ref{ctsbeam}. First 8 is START (first connector) next 8 is also START but perpendicular stripes (second connector). Next 8 is Veto and for the last two the source is selected by 0xA0C2 register.
+ \item [0xA100 - 0xA100 + 26*500] The memory reserved for the histograms. 500 is number of samples per each histogram. The histograms are created in the SCM FPGA (1) see fig. \ref{ctsbeam}.  For the first two the source is selected by 0xA0C2 register next 8 is START next 8 is also START but perpendicular stripes (the source of the start histograms is selected in 0xA0DA register). Next 8 is Veto.
   \end{description}