add option to connect only fast channels from Padiwa to trigger logic.

diff --git a/tdctemplate/config_48_crate_4conn.vhd b/tdctemplate/config_48_crate_4conn.vhd
index 21c6cee9c5cace969a7d133b8a6e63e993d88738..43522d054069a0861a813eec62366c65020d6247 100644 (file)
--- a/tdctemplate/config_48_crate_4conn.vhd
+++ b/tdctemplate/config_48_crate_4conn.vhd
@@ -22,7 +22,7 @@ package config is
 --TDC settings
   constant NUM_TDC_MODULES         : integer range 1 to 4  := 1;  -- number of tdc modules to implement
   constant NUM_TDC_CHANNELS        : integer range 1 to 65 := 49; -- number of tdc channels per module
-  constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6  := 5;  --the nearest power of two, for convenience reasons 
+  constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6  := 6;  --the nearest power of two, for convenience reasons 
   constant DOUBLE_EDGE_TYPE        : integer range 0 to 3  := 3;  --double edge type:  0, 1, 2,  3
   -- 0: single edge only,
   -- 1: same channel,
@@ -33,7 +33,7 @@ package config is
   constant TDC_DATA_FORMAT         : integer := 0;                                                                  
 
   constant EVENT_BUFFER_SIZE       : integer range 9 to 13 := 13; -- size of the event buffer, 2**N
-  constant EVENT_MAX_SIZE          : integer := 4095;             --maximum event size. Should not exceed EVENT_BUFFER_SIZE/2
+  constant EVENT_MAX_SIZE          : integer := 1000;             --maximum event size. Should not exceed EVENT_BUFFER_SIZE/2
 
 --Runs with 120 MHz instead of 100 MHz     
     constant USE_120_MHZ            : integer := c_NO; 
@@ -63,6 +63,8 @@ package config is
     constant TRIG_GEN_OUTPUT_NUM    : integer  := 4;
     constant MONITOR_INPUT_NUM      : integer  := 52;    
    
+    --trigger generation only on 'fast' channels from Padiwa
+    constant TRIG_GEN_FAST_CHANNELS : integer := c_YES;
 ------------------------------------------------------------------------------
 --End of design configuration
 ------------------------------------------------------------------------------

diff --git a/tdctemplate/config_compile_frankfurt.pl b/tdctemplate/config_compile_frankfurt.pl
index c391ae653a0c00e20fe2ad990641dff18b3e2851..3aa417ea48e528a1a8cbdc70c574506196cb30ad 100644 (file)
--- a/tdctemplate/config_compile_frankfurt.pl
+++ b/tdctemplate/config_compile_frankfurt.pl
@@ -3,7 +3,7 @@ lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de";
 lm_license_file_for_par      => "1702\@hadeb05.gsi.de",
 lattice_path                 => '/d/jspc29/lattice/diamond/3.10_x64',
 synplify_path                => '/d/jspc29/lattice/synplify/N-2017.09-1/',
-nodelist_file                => 'nodes_frankfurt.txt',
+nodelist_file                => 'nodes_tdctemplate.txt',
 #Include only necessary lpf files
 #pinout_file                  => 'trb3sc_32pin', #name of pin-out file, if not equal TOPNAME
 pinout_file                  => 'trb3sc_padiwa', #name of pin-out file, if not equal TOPNAME

diff --git a/tdctemplate/nodes_tdctemplate.txt b/tdctemplate/nodes_tdctemplate.txt
new file mode 120000 (symlink)
index 0000000..ac11978
--- /dev/null
+++ b/tdctemplate/nodes_tdctemplate.txt
@@ -0,0 +1 @@
+../scripts/nodes_tdctemplate.txt
\ No newline at end of file

diff --git a/tdctemplate/trb3sc_tdctemplate.prj b/tdctemplate/trb3sc_tdctemplate.prj
index 57026ea695ae1007cd64afc553e6fd819a1a7042..1b040c3b8ccf87a843d47eda6e3de7c05955253f 100644 (file)
--- a/tdctemplate/trb3sc_tdctemplate.prj
+++ b/tdctemplate/trb3sc_tdctemplate.prj
@@ -8,44 +8,94 @@ set_option -part LFE3_150EA
 set_option -package FN1156C
 set_option -speed_grade -8
 set_option -part_companion ""
+#
+## compilation/mapping options
+#set_option -default_enum_encoding sequential
+#set_option -symbolic_fsm_compiler 1
+#set_option -top_module "trb3sc_tdctemplate"
+#set_option -resource_sharing false
+#
+## map options
+#set_option -frequency 120
+#set_option -fanout_limit 100
+#set_option -disable_io_insertion 0
+#set_option -retiming 1
+#set_option -pipe 1
+#set_option -force_gsr false
+#set_option -fix_gated_and_generated_clocks 1
+#set_option -compiler_compatible true
+#
+#set_option -max_parallel_jobs 3
+##set_option -automatic_compile_point 1
+##set_option -continue_on_error 1
+#set_option -resolve_multiple_driver 1
+#
+## simulation options
+#set_option -write_verilog 0
+#set_option -write_vhdl 1
+#
+## automatic place and route (vendor) options
+#set_option -write_apr_constraint 0
+#
+## set result format/file last
+#project -result_format "edif"
+#project -result_file "workdir/trb3sc_tdctemplate.edf"
+#
+##implementation attributes
+#
+#set_option -vlog_std v2001
+#set_option -project_relative_includes 1
 
-# compilation/mapping options
-set_option -default_enum_encoding sequential
-set_option -symbolic_fsm_compiler 1
+
+#compilation/mapping options
 set_option -top_module "trb3sc_tdctemplate"
-set_option -resource_sharing false
 
-# map options
-set_option -frequency 120
-set_option -fanout_limit 100
+# hdl_compiler_options
+set_option -distributed_compile 0
+
+# mapper_without_write_options
+set_option -frequency auto
+set_option -srs_instrumentation 1
+
+# mapper_options
+set_option -write_verilog 0
+set_option -write_vhdl 1
+
+# Lattice XP
+set_option -maxfan 1000
 set_option -disable_io_insertion 0
 set_option -retiming 1
 set_option -pipe 1
-set_option -force_gsr false
-set_option -fixgatedclocks 3
-set_option -fixgeneratedclocks 3
-set_option -compiler_compatible true
+set_option -forcegsr no
+set_option -fix_gated_and_generated_clocks 1
+set_option -rw_check_on_ram 1
+set_option -update_models_cp 0
+set_option -syn_edif_array_rename 1
+set_option -Write_declared_clocks_only 1
 
-set_option -max_parallel_jobs 3
-#set_option -automatic_compile_point 1
-#set_option -continue_on_error 1
-set_option -resolve_multiple_driver 1
+# NFilter
+set_option -no_sequential_opt 0
 
-# simulation options
-set_option -write_verilog 0
-set_option -write_vhdl 1
+# sequential_optimization_options
+set_option -symbolic_fsm_compiler 1
+
+# Compiler Options
+set_option -compiler_compatible 0
+set_option -resource_sharing 1
+set_option -multi_file_compilation_unit 1
 
-# automatic place and route (vendor) options
-set_option -write_apr_constraint 0
+# Compiler Options
+set_option -auto_infer_blackbox 0
+
+# Compiler Options
+set_option -vhdl2008 1
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 1
 
-# set result format/file last
 project -result_format "edif"
 project -result_file "workdir/trb3sc_tdctemplate.edf"
 
-#implementation attributes
-
-set_option -vlog_std v2001
-set_option -project_relative_includes 1
 impl -active "workdir"
 
 ####################

diff --git a/tdctemplate/trb3sc_tdctemplate.vhd b/tdctemplate/trb3sc_tdctemplate.vhd
index 2bbf5811434e1596353b7c49fc5aa3762e451ba4..6350dc37119414ce2919e6ae8c65ef0d116f2fbf 100644 (file)
--- a/tdctemplate/trb3sc_tdctemplate.vhd
+++ b/tdctemplate/trb3sc_tdctemplate.vhd
@@ -114,6 +114,8 @@ architecture trb3sc_arch of trb3sc_tdctemplate is
   signal led               : std_logic_vector(1 downto 0);
   signal debug_clock_reset : std_logic_vector(31 downto 0);
   signal inputs            : std_logic_vector(51 downto 0);
+  signal monitor_inputs_i  : std_logic_vector(MONITOR_INPUT_NUM-1 downto 0);
+  signal trigger_inputs_i  : std_logic_vector(TRIG_GEN_INPUT_NUM-1 downto 0);
 
   --Media Interface
   signal med2int        : med2int_array_t(0 to 0);
@@ -343,6 +345,7 @@ begin
       SPI_CLK_OUT   => spi_clk,
       --Header
       HEADER_IO     => HDR_IO,
+      ADDITIONAL_REG => open,
       --LCD
       LCD_DATA_IN   => lcd_data,
       --ADC
@@ -351,8 +354,8 @@ begin
       ADC_MISO      => ADC_DOUT,
       ADC_CLK       => ADC_CLK,
       --Trigger & Monitor 
-      MONITOR_INPUTS   => inputs(MONITOR_INPUT_NUM-1 downto 0),
-      TRIG_GEN_INPUTS  => inputs(TRIG_GEN_INPUT_NUM-1 downto 0),
+      MONITOR_INPUTS   => monitor_inputs_i(MONITOR_INPUT_NUM-1 downto 0),
+      TRIG_GEN_INPUTS  => trigger_inputs_i(TRIG_GEN_INPUT_NUM-1 downto 0),
       TRIG_GEN_OUTPUTS => trig_gen_out_i,
       --SED
       SED_ERROR_OUT => sed_error_i,
@@ -503,6 +506,7 @@ end generate;
   -- For single edge measurements
   gen_single : if DOUBLE_EDGE_TYPE = 0 or DOUBLE_EDGE_TYPE = 1 or DOUBLE_EDGE_TYPE = 3 generate
     hit_in_i(NUM_TDC_CHANNELS-1 downto 1) <= inputs(NUM_TDC_CHANNELS-2 downto 0);
+--     hit_in_i(NUM_TDC_CHANNELS-1 downto 1) <= INP(NUM_TDC_CHANNELS-2 downto 0);
   end generate;
 
   -- For ToT Measurements
@@ -513,7 +517,19 @@ end generate;
     end generate Gen_Hit_In_Signals;
   end generate;
 
-
+  gen_montrg_inputs_normal : if TRIG_GEN_FAST_CHANNELS = c_NO generate
+    monitor_inputs_i <= inputs(MONITOR_INPUT_NUM-1 downto 0);
+    trigger_inputs_i <= inputs(TRIG_GEN_INPUT_NUM-1 downto 0);
+  end generate;  
+  
+  gen_montrg_inputs_amps : if TRIG_GEN_FAST_CHANNELS = c_YES generate
+    monitor_inputs_i <= trig_gen_out_i & inputs(47 downto 0);
+    gen_chan : for i in 0 to 23 generate
+      trigger_inputs_i(i)    <= inputs(i*2);
+      trigger_inputs_i(i+24) <= inputs(i*2+1);
+    end generate;  
+  end generate;  
+  
 end architecture;