--TDC settings
constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement
constant NUM_TDC_CHANNELS : integer range 1 to 65 := 49; -- number of tdc channels per module
- constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 5; --the nearest power of two, for convenience reasons
+ constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 6; --the nearest power of two, for convenience reasons
constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 3; --double edge type: 0, 1, 2, 3
-- 0: single edge only,
-- 1: same channel,
constant TDC_DATA_FORMAT : integer := 0;
constant EVENT_BUFFER_SIZE : integer range 9 to 13 := 13; -- size of the event buffer, 2**N
- constant EVENT_MAX_SIZE : integer := 4095; --maximum event size. Should not exceed EVENT_BUFFER_SIZE/2
+ constant EVENT_MAX_SIZE : integer := 1000; --maximum event size. Should not exceed EVENT_BUFFER_SIZE/2
--Runs with 120 MHz instead of 100 MHz
constant USE_120_MHZ : integer := c_NO;
constant TRIG_GEN_OUTPUT_NUM : integer := 4;
constant MONITOR_INPUT_NUM : integer := 52;
+ --trigger generation only on 'fast' channels from Padiwa
+ constant TRIG_GEN_FAST_CHANNELS : integer := c_YES;
------------------------------------------------------------------------------
--End of design configuration
------------------------------------------------------------------------------
set_option -package FN1156C
set_option -speed_grade -8
set_option -part_companion ""
+#
+## compilation/mapping options
+#set_option -default_enum_encoding sequential
+#set_option -symbolic_fsm_compiler 1
+#set_option -top_module "trb3sc_tdctemplate"
+#set_option -resource_sharing false
+#
+## map options
+#set_option -frequency 120
+#set_option -fanout_limit 100
+#set_option -disable_io_insertion 0
+#set_option -retiming 1
+#set_option -pipe 1
+#set_option -force_gsr false
+#set_option -fix_gated_and_generated_clocks 1
+#set_option -compiler_compatible true
+#
+#set_option -max_parallel_jobs 3
+##set_option -automatic_compile_point 1
+##set_option -continue_on_error 1
+#set_option -resolve_multiple_driver 1
+#
+## simulation options
+#set_option -write_verilog 0
+#set_option -write_vhdl 1
+#
+## automatic place and route (vendor) options
+#set_option -write_apr_constraint 0
+#
+## set result format/file last
+#project -result_format "edif"
+#project -result_file "workdir/trb3sc_tdctemplate.edf"
+#
+##implementation attributes
+#
+#set_option -vlog_std v2001
+#set_option -project_relative_includes 1
-# compilation/mapping options
-set_option -default_enum_encoding sequential
-set_option -symbolic_fsm_compiler 1
+
+#compilation/mapping options
set_option -top_module "trb3sc_tdctemplate"
-set_option -resource_sharing false
-# map options
-set_option -frequency 120
-set_option -fanout_limit 100
+# hdl_compiler_options
+set_option -distributed_compile 0
+
+# mapper_without_write_options
+set_option -frequency auto
+set_option -srs_instrumentation 1
+
+# mapper_options
+set_option -write_verilog 0
+set_option -write_vhdl 1
+
+# Lattice XP
+set_option -maxfan 1000
set_option -disable_io_insertion 0
set_option -retiming 1
set_option -pipe 1
-set_option -force_gsr false
-set_option -fixgatedclocks 3
-set_option -fixgeneratedclocks 3
-set_option -compiler_compatible true
+set_option -forcegsr no
+set_option -fix_gated_and_generated_clocks 1
+set_option -rw_check_on_ram 1
+set_option -update_models_cp 0
+set_option -syn_edif_array_rename 1
+set_option -Write_declared_clocks_only 1
-set_option -max_parallel_jobs 3
-#set_option -automatic_compile_point 1
-#set_option -continue_on_error 1
-set_option -resolve_multiple_driver 1
+# NFilter
+set_option -no_sequential_opt 0
-# simulation options
-set_option -write_verilog 0
-set_option -write_vhdl 1
+# sequential_optimization_options
+set_option -symbolic_fsm_compiler 1
+
+# Compiler Options
+set_option -compiler_compatible 0
+set_option -resource_sharing 1
+set_option -multi_file_compilation_unit 1
-# automatic place and route (vendor) options
-set_option -write_apr_constraint 0
+# Compiler Options
+set_option -auto_infer_blackbox 0
+
+# Compiler Options
+set_option -vhdl2008 1
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 1
-# set result format/file last
project -result_format "edif"
project -result_file "workdir/trb3sc_tdctemplate.edf"
-#implementation attributes
-
-set_option -vlog_std v2001
-set_option -project_relative_includes 1
impl -active "workdir"
####################
signal led : std_logic_vector(1 downto 0);
signal debug_clock_reset : std_logic_vector(31 downto 0);
signal inputs : std_logic_vector(51 downto 0);
+ signal monitor_inputs_i : std_logic_vector(MONITOR_INPUT_NUM-1 downto 0);
+ signal trigger_inputs_i : std_logic_vector(TRIG_GEN_INPUT_NUM-1 downto 0);
--Media Interface
signal med2int : med2int_array_t(0 to 0);
SPI_CLK_OUT => spi_clk,
--Header
HEADER_IO => HDR_IO,
+ ADDITIONAL_REG => open,
--LCD
LCD_DATA_IN => lcd_data,
--ADC
ADC_MISO => ADC_DOUT,
ADC_CLK => ADC_CLK,
--Trigger & Monitor
- MONITOR_INPUTS => inputs(MONITOR_INPUT_NUM-1 downto 0),
- TRIG_GEN_INPUTS => inputs(TRIG_GEN_INPUT_NUM-1 downto 0),
+ MONITOR_INPUTS => monitor_inputs_i(MONITOR_INPUT_NUM-1 downto 0),
+ TRIG_GEN_INPUTS => trigger_inputs_i(TRIG_GEN_INPUT_NUM-1 downto 0),
TRIG_GEN_OUTPUTS => trig_gen_out_i,
--SED
SED_ERROR_OUT => sed_error_i,
-- For single edge measurements
gen_single : if DOUBLE_EDGE_TYPE = 0 or DOUBLE_EDGE_TYPE = 1 or DOUBLE_EDGE_TYPE = 3 generate
hit_in_i(NUM_TDC_CHANNELS-1 downto 1) <= inputs(NUM_TDC_CHANNELS-2 downto 0);
+-- hit_in_i(NUM_TDC_CHANNELS-1 downto 1) <= INP(NUM_TDC_CHANNELS-2 downto 0);
end generate;
-- For ToT Measurements
end generate Gen_Hit_In_Signals;
end generate;
-
+ gen_montrg_inputs_normal : if TRIG_GEN_FAST_CHANNELS = c_NO generate
+ monitor_inputs_i <= inputs(MONITOR_INPUT_NUM-1 downto 0);
+ trigger_inputs_i <= inputs(TRIG_GEN_INPUT_NUM-1 downto 0);
+ end generate;
+
+ gen_montrg_inputs_amps : if TRIG_GEN_FAST_CHANNELS = c_YES generate
+ monitor_inputs_i <= trig_gen_out_i & inputs(47 downto 0);
+ gen_chan : for i in 0 to 23 generate
+ trigger_inputs_i(i) <= inputs(i*2);
+ trigger_inputs_i(i+24) <= inputs(i*2+1);
+ end generate;
+ end generate;
+
end architecture;