generic (
API_TYPE : integer range 0 to 1 := c_API_PASSIVE;
- INIT_DEPTH : integer range 0 to 6 := 6;--c_FIFO_BRAM;
- REPLY_DEPTH : integer range 0 to 6 := 6;--c_FIFO_SMALL;
+ IBUF_DEPTH : integer range 0 to 6 := 6;--c_FIFO_BRAM;
FIFO_TO_INT_DEPTH : integer range 0 to 6 := 6;--c_FIFO_SMALL;
FIFO_TO_APL_DEPTH : integer range 0 to 6 := 6;--c_FIFO_SMALL;
SBUF_VERSION : integer range 0 to 1 := c_SBUF_FULL;
MUX_SECURE_MODE : integer range 0 to 1 := c_NON_SECURE_MODE;
- IBUF_SECURE_MODE : integer range 0 to 1 := c_NON_SECURE_MODE;
- API_SECURE_MODE_TO_APL : integer range 0 to 1 := c_NON_SECURE_MODE;
- API_SECURE_MODE_TO_INT : integer range 0 to 1 := c_NON_SECURE_MODE;
+ IBUF_SECURE_MODE : integer range 0 to 1 := c_SECURE_MODE;
+ API_SECURE_MODE_TO_APL : integer range 0 to 1 := c_SECURE_MODE;
+ API_SECURE_MODE_TO_INT : integer range 0 to 1 := c_SECURE_MODE;
OBUF_DATA_COUNT_WIDTH : integer range 0 to 7 := std_DATA_COUNT_WIDTH;
- INIT_CAN_SEND_DATA : integer range 0 to 1 := c_YES;
+ INIT_CAN_SEND_DATA : integer range 0 to 1 := c_NO;
REPLY_CAN_SEND_DATA : integer range 0 to 1 := c_YES;
DAT_CHANNEL : integer range 0 to 3 := c_SLOW_CTRL_CHANNEL
);
component trb_net16_iobuf is
generic (
- INIT_DEPTH : integer range 0 to 6 := std_FIFO_DEPTH;
- REPLY_DEPTH : integer range 0 to 6 := std_FIFO_DEPTH;
+ IBUF_DEPTH : integer range 0 to 6 := std_FIFO_DEPTH;
IBUF_SECURE_MODE : integer range 0 to 1 := std_IBUF_SECURE_MODE;
SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION;
OBUF_DATA_COUNT_WIDTH : integer range 2 to 7 := std_DATA_COUNT_WIDTH;
USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE;
- USE_REPLY_CHANNEL : integer range 0 to 1 := c_YES; -- not used yet
INIT_CAN_SEND_DATA : integer range 0 to 1 := c_YES;
REPLY_CAN_SEND_DATA : integer range 0 to 1 := c_YES
);
INT_REPLY_READ_OUT: out std_logic;
-- Status and control port
- STAT_GEN: out std_logic_vector (31 downto 0); -- General Status
- STAT_LOCKED: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control
- STAT_INIT_BUFFER: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control
- STAT_REPLY_BUFFER: out std_logic_vector (31 downto 0); -- General Status
- CTRL_GEN: in std_logic_vector (31 downto 0);
- CTRL_LOCKED: in std_logic_vector (31 downto 0);
- STAT_CTRL_INIT_BUFFER: in std_logic_vector (31 downto 0);
- STAT_CTRL_REPLY_BUFFER: in std_logic_vector (31 downto 0)
+ STAT_GEN: out std_logic_vector (31 downto 0);
+ STAT_IBUF_BUFFER: out std_logic_vector (31 downto 0);
+ CTRL_GEN: in std_logic_vector (31 downto 0);
+ STAT_CTRL_IBUF_BUFFER: in std_logic_vector (31 downto 0)
);
end component;
IOBUF: trb_net16_iobuf
generic map (
- INIT_DEPTH => INIT_DEPTH,
- REPLY_DEPTH => REPLY_DEPTH,
+ IBUF_DEPTH => IBUF_DEPTH,
IBUF_SECURE_MODE => IBUF_SECURE_MODE,
SBUF_VERSION => SBUF_VERSION,
USE_ACKNOWLEDGE => cfg_USE_ACKNOWLEDGE(DAT_CHANNEL),
- USE_REPLY_CHANNEL => cfg_USE_REPLY_CHANNEL(DAT_CHANNEL),
INIT_CAN_SEND_DATA => INIT_CAN_SEND_DATA,
REPLY_CAN_SEND_DATA => REPLY_CAN_SEND_DATA
)
-- Status and control port
STAT_GEN => STAT_GEN,
- STAT_LOCKED => STAT_LOCKED,
- STAT_INIT_BUFFER => buf_STAT_INIT_BUFFER,
- STAT_REPLY_BUFFER => STAT_REPLY_BUFFER,
+ STAT_IBUF_BUFFER => buf_STAT_INIT_BUFFER,
CTRL_GEN => CTRL_GEN,
- CTRL_LOCKED => CTRL_LOCKED,
- STAT_CTRL_INIT_BUFFER => STAT_CTRL_INIT_BUFFER,
- STAT_CTRL_REPLY_BUFFER => STAT_CTRL_REPLY_BUFFER
+ STAT_CTRL_IBUF_BUFFER => STAT_CTRL_INIT_BUFFER
);
-
-STAT_INIT_BUFFER <= buf_STAT_INIT_BUFFER;
+ STAT_INIT_BUFFER <= buf_STAT_INIT_BUFFER;
MPLEX: trb_net16_io_multiplexer
generic map (
HUB_ADDRESS : std_logic_vector(15 downto 0) := x"F003";
--media interfaces
MII_NUMBER : integer range 2 to c_MAX_MII_PER_HUB := 4;
- MII_INIT_DEPTH : hub_iobuf_config_t := std_HUB_INIT_DEPTH;
- MII_REPLY_DEPTH : hub_iobuf_config_t := std_HUB_REPLY_DEPTH;
+ MII_IBUF_DEPTH : hub_iobuf_config_t := std_HUB_IBUF_DEPTH;
-- settings for apis
API_NUMBER : integer range 0 to c_MAX_API_PER_HUB := 0;
API_CHANNELS : hub_api_config_t := (3,3,3,3,3,3,3,3);
signal HUB_CTRL_GEN : std_logic_vector (31 downto 0);
signal IOBUF_STAT_GEN : std_logic_vector ((MII_NUMBER*2**(c_MUX_WIDTH-1) + API_NUMBER + TRG_NUMBER)*32-1 downto 0);
- signal IOBUF_STAT_LOCKED : std_logic_vector ((MII_NUMBER*2**(c_MUX_WIDTH-1) + API_NUMBER + TRG_NUMBER)*32-1 downto 0);
- signal IOBUF_STAT_INIT_BUFFER : std_logic_vector ((MII_NUMBER*2**(c_MUX_WIDTH-1) + API_NUMBER + TRG_NUMBER)*32-1 downto 0);
- signal IOBUF_STAT_REPLY_BUFFER : std_logic_vector ((MII_NUMBER*2**(c_MUX_WIDTH-1) + API_NUMBER + TRG_NUMBER)*32-1 downto 0);
+ signal IOBUF_IBUF_BUFFER : std_logic_vector ((MII_NUMBER*2**(c_MUX_WIDTH-1) + API_NUMBER + TRG_NUMBER)*32-1 downto 0);
signal IOBUF_CTRL_GEN : std_logic_vector ((MII_NUMBER*2**(c_MUX_WIDTH-1) + API_NUMBER + TRG_NUMBER)*32-1 downto 0);
- signal IOBUF_CTRL_LOCKED : std_logic_vector ((MII_NUMBER*2**(c_MUX_WIDTH-1) + API_NUMBER + TRG_NUMBER)*32-1 downto 0);
- signal IOBUF_STAT_CTRL_INIT_BUFFER : std_logic_vector ((MII_NUMBER*2**(c_MUX_WIDTH-1) + API_NUMBER + TRG_NUMBER)*32-1 downto 0);
- signal IOBUF_STAT_CTRL_REPLY_BUFFER : std_logic_vector ((MII_NUMBER*2**(c_MUX_WIDTH-1) + API_NUMBER + TRG_NUMBER)*32-1 downto 0);
+ signal IOBUF_CTRL_IBUF_BUFFER : std_logic_vector ((MII_NUMBER*2**(c_MUX_WIDTH-1) + API_NUMBER + TRG_NUMBER)*32-1 downto 0);
+
component trb_net16_hub_logic is
generic (
component trb_net16_iobuf is
generic (
- INIT_DEPTH : integer range 0 to 6 := 6;
- REPLY_DEPTH : integer range 0 to 6 := 6;
- IBUF_SECURE_MODE : integer range 0 to 1 := c_NO;
+ IBUF_DEPTH : integer range 0 to 6 := c_FIFO_BRAM;--std_FIFO_DEPTH;
+ IBUF_SECURE_MODE : integer range 0 to 1 := c_NO;--std_IBUF_SECURE_MODE;
SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION;
OBUF_DATA_COUNT_WIDTH : integer range 2 to 7 := std_DATA_COUNT_WIDTH;
USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE;
- USE_REPLY_CHANNEL : integer range 0 to 1 := c_YES; -- not used yet
+ USE_VENDOR_CORES : integer range 0 to 1 := c_YES;
INIT_CAN_SEND_DATA : integer range 0 to 1 := c_YES;
REPLY_CAN_SEND_DATA : integer range 0 to 1 := c_YES
);
INT_REPLY_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0);
INT_REPLY_READ_OUT: out std_logic;
-- Status and control port
- STAT_GEN: out std_logic_vector (31 downto 0); -- General Status
- STAT_LOCKED: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control
- STAT_INIT_BUFFER: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control
- STAT_REPLY_BUFFER: out std_logic_vector (31 downto 0); -- General Status
- CTRL_GEN: in std_logic_vector (31 downto 0);
- CTRL_LOCKED: in std_logic_vector (31 downto 0);
- STAT_CTRL_INIT_BUFFER: in std_logic_vector (31 downto 0);
- STAT_CTRL_REPLY_BUFFER: in std_logic_vector (31 downto 0)
+ STAT_GEN: out std_logic_vector (31 downto 0);
+ STAT_IBUF_BUFFER: out std_logic_vector (31 downto 0);
+ CTRL_GEN: in std_logic_vector (31 downto 0);
+ STAT_CTRL_IBUF_BUFFER: in std_logic_vector (31 downto 0)
);
end component;
gen_iobuf: if HUB_USED_CHANNELS(k) = 1 generate
IOBUF: trb_net16_iobuf
generic map (
- INIT_DEPTH => calc_depth(i,MII_INIT_DEPTH, API_FIFO_TO_APL_DEPTH, MII_NUMBER, API_NUMBER, c_MUX_WIDTH, HUB_CTRL_DEPTH),
- REPLY_DEPTH => calc_depth(i,MII_REPLY_DEPTH, API_FIFO_TO_INT_DEPTH, MII_NUMBER, API_NUMBER, c_MUX_WIDTH, HUB_CTRL_DEPTH),
+ IBUF_DEPTH => calc_depth(i,MII_IBUF_DEPTH, API_FIFO_TO_APL_DEPTH, MII_NUMBER, API_NUMBER, c_MUX_WIDTH, HUB_CTRL_DEPTH),
IBUF_SECURE_MODE => IBUF_SECURE_MODE
)
port map (
-- Status and control port
STAT_GEN => IOBUF_STAT_GEN((i+1)*32-1 downto i*32),
- STAT_LOCKED => IOBUF_STAT_LOCKED((i+1)*32-1 downto i*32),
- STAT_INIT_BUFFER => IOBUF_STAT_INIT_BUFFER((i+1)*32-1 downto i*32),
- STAT_REPLY_BUFFER => IOBUF_STAT_REPLY_BUFFER((i+1)*32-1 downto i*32),
+ STAT_IBUF_BUFFER => IOBUF_IBUF_BUFFER((i+1)*32-1 downto i*32),
CTRL_GEN => IOBUF_CTRL_GEN((i+1)*32-1 downto i*32),
- CTRL_LOCKED => IOBUF_CTRL_LOCKED((i+1)*32-1 downto i*32),
- STAT_CTRL_INIT_BUFFER => IOBUF_STAT_CTRL_INIT_BUFFER((i+1)*32-1 downto i*32),
- STAT_CTRL_REPLY_BUFFER => IOBUF_STAT_CTRL_REPLY_BUFFER((i+1)*32-1 downto i*32)
+ STAT_CTRL_IBUF_BUFFER => IOBUF_CTRL_IBUF_BUFFER((i+1)*32-1 downto i*32)
);
+
end generate;
gen_trmbuf: if HUB_USED_CHANNELS(k) = 0 generate
IOBUF : trb_net16_term_buf
- IOBUF_CTRL_GEN <= (others => '0');
- IOBUF_CTRL_LOCKED <= (others => '0');
- IOBUF_STAT_CTRL_INIT_BUFFER <= (others => '0');
- IOBUF_STAT_CTRL_REPLY_BUFFER <= (others => '0');
constant c_MAX_TRG_PER_HUB : integer := 8;
constant c_MAX_POINTS_PER_HUB : integer := 18;
- constant std_HUB_INIT_DEPTH : hub_iobuf_config_t :=( 6,6,6,6, --MII 0
+ constant std_HUB_IBUF_DEPTH : hub_iobuf_config_t :=( 6,6,6,6, --MII 0
6,6,6,6,
6,6,6,6,
6,6,6,6,
6,6,6,6,
6,6,6,6,
6,6,6,6); --MII 15
- constant std_HUB_REPLY_DEPTH : hub_iobuf_config_t:=( 6,6,6,6, --MII 0
- 6,6,6,6,
- 6,6,6,6,
- 6,6,6,6,
- 6,6,6,6,
- 6,6,6,6,
- 6,6,6,6,
- 6,6,6,6,
- 6,6,6,6,
- 6,6,6,6,
- 6,6,6,6,
- 6,6,6,6,
- 6,6,6,6,
- 6,6,6,6,
- 6,6,6,6,
- 6,6,6,6); --MII 15
function calc_point_number (MII_NUMBER : integer;
CHANNEL : integer;
OBUF_DATA_COUNT_WIDTH : integer range 2 to 7 := std_DATA_COUNT_WIDTH;
USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE;
USE_VENDOR_CORES : integer range 0 to 1 := c_YES;
- USE_REPLY_CHANNEL : integer range 0 to 1 := c_YES; -- not used yet
INIT_CAN_SEND_DATA : integer range 0 to 1 := c_YES;
REPLY_CAN_SEND_DATA : integer range 0 to 1 := c_YES
);
constant c_DATA_WIDTH : integer := 16;
constant c_NUM_WIDTH : integer := 2;
- constant c_MUX_WIDTH : integer := 1; --!!!
+ constant c_MUX_WIDTH : integer := 3; --!!!
--assigning channel names
end generate;
end generate;
- gen_XILINX_CORES : if USE_VENDOR_CORES = c_YES generate
- gen_FIFO1 : if DEPTH = 1 generate
- fifo:xilinx_fifo_18x16
- port map (
- clk => CLK,
- rd_en => READ_ENABLE_IN,
- wr_en => WRITE_ENABLE_IN,
- din => din,
- rst => RESET,
- dout => dout,
- full => FULL_OUT,
- empty => EMPTY_OUT
- );
- end generate;
-
- gen_FIFO2 : if DEPTH = 2 generate
- fifo:xilinx_fifo_18x32
- port map (
- clk => CLK,
- rd_en => READ_ENABLE_IN,
- wr_en => WRITE_ENABLE_IN,
- din => din,
- rst => RESET,
- dout => dout,
- full => FULL_OUT,
- empty => EMPTY_OUT
- );
- end generate;
-
-
- gen_FIFO3 : if DEPTH = 3 generate
- fifo:xilinx_fifo_18x64
- port map (
- clk => CLK,
- rd_en => READ_ENABLE_IN,
- wr_en => WRITE_ENABLE_IN,
- din => din,
- rst => RESET,
- dout => dout,
- full => FULL_OUT,
- empty => EMPTY_OUT
- );
- end generate;
- end generate;
+-- gen_XILINX_CORES : if USE_VENDOR_CORES = c_YES generate
+-- gen_FIFO1 : if DEPTH = 1 generate
+-- fifo:xilinx_fifo_18x16
+-- port map (
+-- clk => CLK,
+-- rd_en => READ_ENABLE_IN,
+-- wr_en => WRITE_ENABLE_IN,
+-- din => din,
+-- rst => RESET,
+-- dout => dout,
+-- full => FULL_OUT,
+-- empty => EMPTY_OUT
+-- );
+-- end generate;
+--
+-- gen_FIFO2 : if DEPTH = 2 generate
+-- fifo:xilinx_fifo_18x32
+-- port map (
+-- clk => CLK,
+-- rd_en => READ_ENABLE_IN,
+-- wr_en => WRITE_ENABLE_IN,
+-- din => din,
+-- rst => RESET,
+-- dout => dout,
+-- full => FULL_OUT,
+-- empty => EMPTY_OUT
+-- );
+-- end generate;
+--
+--
+-- gen_FIFO3 : if DEPTH = 3 generate
+-- fifo:xilinx_fifo_18x64
+-- port map (
+-- clk => CLK,
+-- rd_en => READ_ENABLE_IN,
+-- wr_en => WRITE_ENABLE_IN,
+-- din => din,
+-- rst => RESET,
+-- dout => dout,
+-- full => FULL_OUT,
+-- empty => EMPTY_OUT
+-- );
+-- end generate;
+-- end generate;
end architecture;
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
--- (c) Copyright 1995-2005 Xilinx, Inc. --
+-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file xilinx_fifo_18x16.vhd when simulating
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
--- The synopsys directives "translate_off/translate_on" specified
--- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity
+-- The synthesis directives "translate_off/translate_on" specified
+-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--- synopsys translate_off
+-- synthesis translate_off
Library XilinxCoreLib;
--- synopsys translate_on
+-- synthesis translate_on
ENTITY xilinx_fifo_18x16 IS
port (
clk: IN std_logic;
END xilinx_fifo_18x16;
ARCHITECTURE xilinx_fifo_18x16_a OF xilinx_fifo_18x16 IS
--- synopsys translate_off
+-- synthesis translate_off
component wrapped_xilinx_fifo_18x16
port (
clk: IN std_logic;
end component;
-- Configuration specification
- for all : wrapped_xilinx_fifo_18x16 use entity XilinxCoreLib.sync_fifo_v5_0(behavioral)
+ for all : wrapped_xilinx_fifo_18x16 use entity XilinxCoreLib.sync_fifo_v4_2(behavioral)
generic map(
c_read_data_width => 18,
c_has_wr_ack => 0,
c_memory_type => 0,
c_write_data_width => 18,
c_has_rd_err => 0);
--- synopsys translate_on
+-- synthesis translate_on
BEGIN
--- synopsys translate_off
+-- synthesis translate_off
U0 : wrapped_xilinx_fifo_18x16
port map (
clk => clk,
dout => dout,
full => full,
empty => empty);
--- synopsys translate_on
+-- synthesis translate_on
END xilinx_fifo_18x16_a;
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
--- (c) Copyright 1995-2005 Xilinx, Inc. --
+-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file xilinx_fifo_18x32.vhd when simulating
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
--- The synopsys directives "translate_off/translate_on" specified
--- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity
+-- The synthesis directives "translate_off/translate_on" specified
+-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--- synopsys translate_off
+-- synthesis translate_off
Library XilinxCoreLib;
--- synopsys translate_on
+-- synthesis translate_on
ENTITY xilinx_fifo_18x32 IS
port (
clk: IN std_logic;
END xilinx_fifo_18x32;
ARCHITECTURE xilinx_fifo_18x32_a OF xilinx_fifo_18x32 IS
--- synopsys translate_off
+-- synthesis translate_off
component wrapped_xilinx_fifo_18x32
port (
clk: IN std_logic;
c_memory_type => 0,
c_write_data_width => 18,
c_has_rd_err => 0);
--- synopsys translate_on
+-- synthesis translate_on
BEGIN
--- synopsys translate_off
+-- synthesis translate_off
U0 : wrapped_xilinx_fifo_18x32
port map (
clk => clk,
dout => dout,
full => full,
empty => empty);
--- synopsys translate_on
+-- synthesis translate_on
END xilinx_fifo_18x32_a;
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
--- (c) Copyright 1995-2005 Xilinx, Inc. --
+-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file xilinx_fifo_18x64.vhd when simulating
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
--- The synopsys directives "translate_off/translate_on" specified
--- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity
+-- The synthesis directives "translate_off/translate_on" specified
+-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--- synopsys translate_off
+-- synthesis translate_off
Library XilinxCoreLib;
--- synopsys translate_on
+-- synthesis translate_on
ENTITY xilinx_fifo_18x64 IS
port (
clk: IN std_logic;
END xilinx_fifo_18x64;
ARCHITECTURE xilinx_fifo_18x64_a OF xilinx_fifo_18x64 IS
--- synopsys translate_off
+-- synthesis translate_off
component wrapped_xilinx_fifo_18x64
port (
clk: IN std_logic;
c_memory_type => 0,
c_write_data_width => 18,
c_has_rd_err => 0);
--- synopsys translate_on
+-- synthesis translate_on
BEGIN
--- synopsys translate_off
+-- synthesis translate_off
U0 : wrapped_xilinx_fifo_18x64
port map (
clk => clk,
dout => dout,
full => full,
empty => empty);
--- synopsys translate_on
+-- synthesis translate_on
END xilinx_fifo_18x64_a;
jspc29 / trbnet.git / commitdiff