attribute syn_keep of trg_win_end_tdc : signal is true;
attribute syn_hier : string;
- attribute syn_hier of Channel_200 : architecture is "firm";
+ attribute syn_hier of Channel_200 : architecture is "fixed";
begin -- Channel_200
-- accept trigger if it is longer than 100 ns
if RESET_TDC = '1' then
trg_pulse_tdc(i) <= '0';
- elsif trg_length(i) = to_unsigned(20, 5) then
+ elsif trg_length(i) = to_unsigned(15, 5) then
trg_pulse_tdc(i) <= '1';
else
trg_pulse_tdc(i) <= '0';
-- SD_RXD_N_IN => SERDES_INT_RX(3),
-- SD_TXD_P_OUT => SERDES_INT_TX(2),
-- SD_TXD_N_OUT => SERDES_INT_TX(3),
- SD_REFCLK_P_IN => open,
- SD_REFCLK_N_IN => open,
+-- SD_REFCLK_P_IN => open,
+-- SD_REFCLK_N_IN => open,
SD_PRSNT_N_IN => FPGA5_COMM(0),
SD_LOS_IN => FPGA5_COMM(0),
SD_TXDIS_OUT => FPGA5_COMM(2),