]> jspc29.x-matter.uni-frankfurt.de Git - tdc.git/commitdiff
Fix placement of logic in regions. Fix detection of length of reference time signal.
authorJan Michel <j.michel@gsi.de>
Fri, 2 Feb 2018 10:48:38 +0000 (11:48 +0100)
committerJan Michel <j.michel@gsi.de>
Fri, 2 Feb 2018 10:48:38 +0000 (11:48 +0100)
releases/tdc_v2.3/Channel_200.vhd
releases/tdc_v2.3/TriggerHandler.vhd
releases/tdc_v2.3/trb3_periph_ADA.vhd

index db10ded64a35ecb0749fd8a37b24dd3561c29aab..e5026078768f6a7e0ebde1bcc5e4d306702c678b 100644 (file)
@@ -172,7 +172,7 @@ architecture Channel_200 of Channel_200 is
   attribute syn_keep of trg_win_end_tdc : signal is true;
 
   attribute syn_hier : string;
-  attribute syn_hier of Channel_200 : architecture is "firm";
+  attribute syn_hier of Channel_200 : architecture is "fixed";
   
 begin  -- Channel_200
 
index 7ea901fc017d461d6eca1eefe6f42727492fa540..f0271f5df335dc2f4056f7f1ea9fbe0b4c16700a 100644 (file)
@@ -106,7 +106,7 @@ begin  -- architecture behavioral
         -- accept trigger if it is longer than 100 ns
         if RESET_TDC = '1' then
           trg_pulse_tdc(i) <= '0';
-        elsif trg_length(i) = to_unsigned(20, 5) then
+        elsif trg_length(i) = to_unsigned(15, 5) then
           trg_pulse_tdc(i) <= '1';
         else
           trg_pulse_tdc(i) <= '0';
index 98442ba10d9cc35c0cfbb62f0b754cc886a99bed..6d03c533d0f635628f486827d19a2690956ddf8c 100644 (file)
@@ -229,8 +229,8 @@ begin
 --       SD_RXD_N_IN        => SERDES_INT_RX(3),
 --       SD_TXD_P_OUT       => SERDES_INT_TX(2),
 --       SD_TXD_N_OUT       => SERDES_INT_TX(3),
-      SD_REFCLK_P_IN     => open,
-      SD_REFCLK_N_IN     => open,
+--       SD_REFCLK_P_IN     => open,
+--       SD_REFCLK_N_IN     => open,
       SD_PRSNT_N_IN      => FPGA5_COMM(0),
       SD_LOS_IN          => FPGA5_COMM(0),
       SD_TXDIS_OUT       => FPGA5_COMM(2),