fixed the problem with the stretcher not working

diff --git a/testbench/tb.vhd b/testbench/tb.vhd
index f605ae848b48c65e6ab098826411cd40486652c3..db6d28ee7573936424009529db945389d3f49f3a 100644 (file)
--- a/testbench/tb.vhd
+++ b/testbench/tb.vhd
@@ -33,17 +33,18 @@ end component;
 
 
 signal CLK : std_logic := '1';
--- signal RESET : std_logic := '1';
 signal inputs : std_logic_vector(23 downto 0);
 
 signal BUS_RX : CTRLBUS_RX;
 signal BUS_TX : CTRLBUS_TX;
+signal reset_i:std_logic:='1';
 
 
 begin
 
--- RESET<= '0' after 500 ns;
-CLK <= not CLK after 5 ns;                                                             -- makes a frequency of 100MHz
+
+CLK <= not CLK after 5 ns;  -- makes a frequency of 100MHz
+reset_i<='0' after 100 ns; 
 
 PROC_INIT_REGISTERS : process begin                                                    -- Define the Values for the Registers here
   BUS_RX.write <= '0';
@@ -66,15 +67,15 @@ PROC_INIT_REGISTERS : process begin
   wait until rising_edge(CLK); wait for 1 ns;
   BUS_RX.write <= '1'; BUS_RX.addr <= x"0101"; BUS_RX.data <= x"00000000";            -- 
   wait until rising_edge(CLK); wait for 1 ns;
-  BUS_RX.write <= '1'; BUS_RX.addr <= x"0102"; BUS_RX.data <= x"00000001";            -- 
+  BUS_RX.write <= '1'; BUS_RX.addr <= x"0102"; BUS_RX.data <= x"00000000";            -- 
   wait until rising_edge(CLK); wait for 1 ns;
-  BUS_RX.write <= '1'; BUS_RX.addr <= x"0103"; BUS_RX.data <= x"00000002";            -- 
+  BUS_RX.write <= '1'; BUS_RX.addr <= x"0103"; BUS_RX.data <= x"00000000";            -- 
   wait until rising_edge(CLK); wait for 1 ns;
-  BUS_RX.write <= '1'; BUS_RX.addr <= x"0104"; BUS_RX.data <= x"00000003";            -- 
+  BUS_RX.write <= '1'; BUS_RX.addr <= x"0104"; BUS_RX.data <= x"00000000";            -- 
   wait until rising_edge(CLK); wait for 1 ns;
-  BUS_RX.write <= '1'; BUS_RX.addr <= x"0105"; BUS_RX.data <= x"00000004";            -- 
+  BUS_RX.write <= '1'; BUS_RX.addr <= x"0105"; BUS_RX.data <= x"00000000";            -- 
   wait until rising_edge(CLK); wait for 1 ns;
-  BUS_RX.write <= '1'; BUS_RX.addr <= x"0106"; BUS_RX.data <= x"00000005";            -- 
+  BUS_RX.write <= '1'; BUS_RX.addr <= x"0106"; BUS_RX.data <= x"00000000";            -- 
   wait until rising_edge(CLK); wait for 1 ns;
   BUS_RX.write <= '1'; BUS_RX.addr <= x"0107"; BUS_RX.data <= x"00000005";            -- 
   wait until rising_edge(CLK); wait for 1 ns;
@@ -107,27 +108,34 @@ PROC_INIT_REGISTERS : process begin
   
   
   ---------------------------------------------------   Stretch Registers --------------------------------------------------
-  BUS_RX.write <= '1'; BUS_RX.addr <= x"0200"; BUS_RX.data <= x"00010008";            -- 
+  -- First number sets the Stretch type,
+  -- 0: no stretch, the signal will be 1 clock cyclus long,
+  -- 1: signal will get enlagred by the number of clock beats set on the end
+  -- 2: signal will get enlaged to # set on the end times 10 us
+  -- 3: signal will get enlaged to # set on the end times 10 ms
+  
+  
+  BUS_RX.write <= '1'; BUS_RX.addr <= x"0200"; BUS_RX.data <= x"00010001";            -- 1
   wait until rising_edge(CLK); wait for 1 ns;
-  BUS_RX.write <= '1'; BUS_RX.addr <= x"0201"; BUS_RX.data <= x"00010008";            -- 
+  BUS_RX.write <= '1'; BUS_RX.addr <= x"0201"; BUS_RX.data <= x"00010002";            -- 2
   wait until rising_edge(CLK); wait for 1 ns;
-  BUS_RX.write <= '1'; BUS_RX.addr <= x"0202"; BUS_RX.data <= x"00010006";            -- 
+  BUS_RX.write <= '1'; BUS_RX.addr <= x"0202"; BUS_RX.data <= x"00010003";            -- 3
   wait until rising_edge(CLK); wait for 1 ns;
-  BUS_RX.write <= '1'; BUS_RX.addr <= x"0203"; BUS_RX.data <= x"00010006";            -- 
+  BUS_RX.write <= '1'; BUS_RX.addr <= x"0203"; BUS_RX.data <= x"00030002";            -- 4
   wait until rising_edge(CLK); wait for 1 ns;
-  BUS_RX.write <= '1'; BUS_RX.addr <= x"0204"; BUS_RX.data <= x"00010006";            -- 
+  BUS_RX.write <= '1'; BUS_RX.addr <= x"0204"; BUS_RX.data <= x"00030001";            -- 5
   wait until rising_edge(CLK); wait for 1 ns;
-  BUS_RX.write <= '1'; BUS_RX.addr <= x"0205"; BUS_RX.data <= x"00010008";            -- 
+  BUS_RX.write <= '1'; BUS_RX.addr <= x"0205"; BUS_RX.data <= x"00000002";            -- 6
   wait until rising_edge(CLK); wait for 1 ns;
-  BUS_RX.write <= '1'; BUS_RX.addr <= x"0206"; BUS_RX.data <= x"00010000";            -- 
+  BUS_RX.write <= '1'; BUS_RX.addr <= x"0206"; BUS_RX.data <= x"00000000";            -- 7
   wait until rising_edge(CLK); wait for 1 ns;
-  BUS_RX.write <= '1'; BUS_RX.addr <= x"0207"; BUS_RX.data <= x"00000000";            -- 
+  BUS_RX.write <= '1'; BUS_RX.addr <= x"0207"; BUS_RX.data <= x"00000000";            -- 8
   wait until rising_edge(CLK); wait for 1 ns;
-  BUS_RX.write <= '1'; BUS_RX.addr <= x"0208"; BUS_RX.data <= x"00020001";            -- 
+  BUS_RX.write <= '1'; BUS_RX.addr <= x"0208"; BUS_RX.data <= x"00000000";            -- 9
   wait until rising_edge(CLK); wait for 1 ns;
-  BUS_RX.write <= '1'; BUS_RX.addr <= x"0209"; BUS_RX.data <= x"00030001";            -- 
+  BUS_RX.write <= '1'; BUS_RX.addr <= x"0209"; BUS_RX.data <= x"00000000";            -- 10
   wait until rising_edge(CLK); wait for 1 ns;
-  BUS_RX.write <= '1'; BUS_RX.addr <= x"020A"; BUS_RX.data <= x"00010014";            -- 
+  BUS_RX.write <= '1'; BUS_RX.addr <= x"020A"; BUS_RX.data <= x"00010000";            -- 11
   wait until rising_edge(CLK); wait for 1 ns;
 --   BUS_RX.write <= '1'; BUS_RX.addr <= x"020B"; BUS_RX.data <= x"0000000E";            -- 
 --   wait until rising_edge(CLK); wait for 1 ns;
@@ -151,27 +159,27 @@ PROC_INIT_REGISTERS : process begin
 --   wait until rising_edge(CLK); wait for 1 ns;
 
  ---------------------------------------------------   Coin Registers --------------------------------------------------
-  BUS_RX.write <= '1'; BUS_RX.addr <= x"0300"; BUS_RX.data <= x"00010100";            -- 0
+  BUS_RX.write <= '1'; BUS_RX.addr <= x"0300"; BUS_RX.data <= x"00000000";            -- 0
   wait until rising_edge(CLK); wait for 1 ns;
-  BUS_RX.write <= '1'; BUS_RX.addr <= x"0301"; BUS_RX.data <= x"00000100";            -- 1
+  BUS_RX.write <= '1'; BUS_RX.addr <= x"0301"; BUS_RX.data <= x"00000000";            -- 1
   wait until rising_edge(CLK); wait for 1 ns;
-  BUS_RX.write <= '1'; BUS_RX.addr <= x"0302"; BUS_RX.data <= x"00030100";            -- 2
+  BUS_RX.write <= '1'; BUS_RX.addr <= x"0302"; BUS_RX.data <= x"00000000";            -- 2
   wait until rising_edge(CLK); wait for 1 ns;
-  BUS_RX.write <= '1'; BUS_RX.addr <= x"0303"; BUS_RX.data <= x"00020100";            -- 3
+  BUS_RX.write <= '1'; BUS_RX.addr <= x"0303"; BUS_RX.data <= x"00000000";            -- 3
   wait until rising_edge(CLK); wait for 1 ns;
-  BUS_RX.write <= '1'; BUS_RX.addr <= x"0304"; BUS_RX.data <= x"00050100";            -- 4
+  BUS_RX.write <= '1'; BUS_RX.addr <= x"0304"; BUS_RX.data <= x"00000000";            -- 4
   wait until rising_edge(CLK); wait for 1 ns;
-  BUS_RX.write <= '1'; BUS_RX.addr <= x"0305"; BUS_RX.data <= x"00040100";            -- 5
+  BUS_RX.write <= '1'; BUS_RX.addr <= x"0305"; BUS_RX.data <= x"00000000";            -- 5
   wait until rising_edge(CLK); wait for 1 ns;  
-  BUS_RX.write <= '1'; BUS_RX.addr <= x"0306"; BUS_RX.data <= x"00070100";            -- 6
+  BUS_RX.write <= '1'; BUS_RX.addr <= x"0306"; BUS_RX.data <= x"00000000";            -- 6
   wait until rising_edge(CLK); wait for 1 ns;
-  BUS_RX.write <= '1'; BUS_RX.addr <= x"0307"; BUS_RX.data <= x"00060100";            -- 7
+  BUS_RX.write <= '1'; BUS_RX.addr <= x"0307"; BUS_RX.data <= x"00000000";            -- 7
   wait until rising_edge(CLK); wait for 1 ns; 
-  BUS_RX.write <= '1'; BUS_RX.addr <= x"0308"; BUS_RX.data <= x"00090100";            -- 8
+  BUS_RX.write <= '1'; BUS_RX.addr <= x"0308"; BUS_RX.data <= x"00000000";            -- 8
   wait until rising_edge(CLK); wait for 1 ns;
   BUS_RX.write <= '1'; BUS_RX.addr <= x"0309"; BUS_RX.data <= x"00080100";            -- 9
   wait until rising_edge(CLK); wait for 1 ns; 
-  BUS_RX.write <= '1'; BUS_RX.addr <= x"030A"; BUS_RX.data <= x"000B0100";            -- 10
+  BUS_RX.write <= '1'; BUS_RX.addr <= x"030A"; BUS_RX.data <= x"00080100";            -- 10
   wait until rising_edge(CLK); wait for 1 ns;
   BUS_RX.write <= '1'; BUS_RX.addr <= x"030B"; BUS_RX.data <= x"000A0100";            -- 11
   wait until rising_edge(CLK); wait for 1 ns;
@@ -180,21 +188,21 @@ PROC_INIT_REGISTERS : process begin
   
   
  ---------------------------------------------------   Merge Registers --------------------------------------------------  
-  BUS_RX.write <= '1'; BUS_RX.addr <= x"0018"; BUS_RX.data <= x"0000000F";                                                
+  BUS_RX.write <= '1'; BUS_RX.addr <= x"0018"; BUS_RX.data <= x"00000001";                    -- ...0000001                            
   wait until rising_edge(CLK); wait for 1 ns;
-  BUS_RX.write <= '1'; BUS_RX.addr <= x"0019"; BUS_RX.data <= x"000000F0";            
+  BUS_RX.write <= '1'; BUS_RX.addr <= x"0019"; BUS_RX.data <= x"00000002";                    -- ...0000010
   wait until rising_edge(CLK); wait for 1 ns;
-  BUS_RX.write <= '1'; BUS_RX.addr <= x"001A"; BUS_RX.data <= x"00000F00";            
+  BUS_RX.write <= '1'; BUS_RX.addr <= x"001A"; BUS_RX.data <= x"00000004";                    -- ...0000100
   wait until rising_edge(CLK); wait for 1 ns;
-  BUS_RX.write <= '1'; BUS_RX.addr <= x"001B"; BUS_RX.data <= x"0000F000";            
+  BUS_RX.write <= '1'; BUS_RX.addr <= x"001B"; BUS_RX.data <= x"00000008";                    -- ...0001000
   wait until rising_edge(CLK); wait for 1 ns;
-  BUS_RX.write <= '1'; BUS_RX.addr <= x"001C"; BUS_RX.data <= x"000F0000";            
+  BUS_RX.write <= '1'; BUS_RX.addr <= x"001C"; BUS_RX.data <= x"00000010";                    -- ...0010000
   wait until rising_edge(CLK); wait for 1 ns;
-  BUS_RX.write <= '1'; BUS_RX.addr <= x"001D"; BUS_RX.data <= x"00F00000";            
+  BUS_RX.write <= '1'; BUS_RX.addr <= x"001D"; BUS_RX.data <= x"00000020";                    -- ...0100000
   wait until rising_edge(CLK); wait for 1 ns;
-  BUS_RX.write <= '1'; BUS_RX.addr <= x"001E"; BUS_RX.data <= x"0F000000";            
+  BUS_RX.write <= '1'; BUS_RX.addr <= x"001E"; BUS_RX.data <= x"00000000";            
   wait until rising_edge(CLK); wait for 1 ns;
-  BUS_RX.write <= '1'; BUS_RX.addr <= x"001F"; BUS_RX.data <= x"F0000000";            
+  BUS_RX.write <= '1'; BUS_RX.addr <= x"001F"; BUS_RX.data <= x"00000000";            
   wait until rising_edge(CLK); wait for 1 ns; 
   
   
@@ -208,34 +216,34 @@ end process;
 PROC_INPUTS : process begin     -- Simulates the Inputs by the detector
   inputs <= (others => '0');
   wait for 500 ns;
-  wait for 24 ns;
-  inputs <= x"000001";
-  wait for 27 ns;
-  inputs <= x"8AB400";
-  wait for 33 ns;
-  inputs <= x"00F44F";
-  wait for 14 ns;
-  inputs <= x"00C4CF";
-  wait for 16 ns;                                                                          -- too short to detect
-  inputs <= x"FFFFFF";
-  wait for 18 ns;
-  inputs <= x"000001";
-  wait for 27 ns;
-  inputs <= x"FFFFFF";
-  wait for 18 ns;
-  inputs <= x"000001";
-  wait for 27 ns;
+--   wait for 24 ns;
+--   inputs <= x"000001";
+--   wait for 27 ns;
+--   inputs <= x"8AB400";
+--   wait for 33 ns;
+--   inputs <= x"00F44F";
+--   wait for 14 ns;
+--   inputs <= x"00C4CF";
+--   wait for 16 ns;                                                                          
+--   inputs <= x"FFFFFF";
+--   wait for 18 ns;
+--   inputs <= x"000001";
+--   wait for 27 ns;
   inputs <= x"FFFFFF";
-  wait for 18 ns;
-  inputs <= x"000001";
-  wait for 27 ns;
-  inputs <= x"8AB400";
-  wait for 33 ns;
-  inputs <= x"00F44F";
-  wait for 14 ns;
-  inputs <= x"00C4CF";
-  wait for 26 ns;                                                                          -- too short to detect
+  wait for 70 ns;
   inputs <= x"000000";
+  wait for 20000 ns;
+--   inputs <= x"FFFFFF";
+--   wait for 45 ns;
+--   inputs <= x"000001";
+--   wait for 27 ns;
+--   inputs <= x"8AB400";
+--   wait for 33 ns;
+--   inputs <= x"00F44F";
+--   wait for 14 ns;
+--   inputs <= x"00C4CF";
+--   wait for 26 ns;                                                                         
+--   inputs <= x"000000";
 end process;
 
 
@@ -246,7 +254,7 @@ THE_LOGIC : trigger_logic
     )
   port map(
     CLK => CLK,
-    RESET => '0',
+    RESET => reset_i,
     BUS_RX => BUS_RX,
     BUS_TX => open,
     INPUT  => inputs,

diff --git a/trigger_delay.vhd b/trigger_delay.vhd
index 6019637e8d43b49c04c16f4cd9ad95c9acfbe228..6fe218f79dd2cf659c8e0f916317698f539f1f2e 100644 (file)
--- a/trigger_delay.vhd
+++ b/trigger_delay.vhd
@@ -13,7 +13,7 @@ entity trg_delay is
   signal_in     : in std_logic;
   delay_time    : in std_logic_vector (7 downto 0);
   reg_onswitch  : in std_logic;
---   reset_i       : in std_logic;
+  reset_i       : in std_logic;
   processed_signal   : out std_logic
   );
 end trg_delay;
@@ -21,11 +21,11 @@ end trg_delay;
 architecture behave of trg_delay is   
   
  signal from_shift_reg: std_logic;
- signal reset_i:std_logic:='1';
+--  signal reset_i:std_logic:='1';
  
 begin
 
-reset_i<='0' after 100ns;
+-- reset_i<='0' after 100ns;
 
 PROC_ENABLEDELAY: process begin
 wait until rising_edge(clk_in);

diff --git a/trigger_edgedetect.vhd b/trigger_edgedetect.vhd
index b14658e95383b29234f010e3b9b0c61be06d4d27..ac3e45a7acafa0aa948c0ced2e28a73823b155da 100644 (file)
--- a/trigger_edgedetect.vhd
+++ b/trigger_edgedetect.vhd
@@ -34,7 +34,7 @@ begin
 detect_step1: process is
 begin 
   wait until rising_edge(clk_in);
-  for i in 0 to 31 loop
+  for i in 0 to CHANNELS-1 loop
     temp_save(i)<=signals(i);
   end loop;
 end process;
@@ -44,7 +44,7 @@ end process;
 detect_step2: process is
 begin 
   wait until rising_edge(clk_in);
-  for i in 0 to 31 loop
+  for i in 0 to CHANNELS-1 loop
     if reg_inhalt(i)='0' then
       processed_signals(i)<=signals(i);      
     elsif signals(i)='1' and temp_save(i)='0' then       --

diff --git a/trigger_enable.vhd b/trigger_enable.vhd
index 4b21a6c7bf2d7621aea3a6ce2a7164d778eda301..f3d1bb975ad306e3eff6bdffb24e37135ac562d3 100644 (file)
--- a/trigger_enable.vhd
+++ b/trigger_enable.vhd
@@ -29,7 +29,7 @@ begin
 enable: process(signals) is
 begin
 --    wait until rising_edge(clk_in);
-  for i in 0 to 31 loop
+  for i in 0 to CHANNELS-1 loop
     if reg_inhalt(i) = '0' then
       processed_signals(i) <= '0';
     else 

diff --git a/trigger_inverter.vhd b/trigger_inverter.vhd
index 4cb288adb76d9400b5b19e813efe17f8a3cd9130..989e70fac958e08d7edcf6cc4b8d4c8df9013b38 100644 (file)
--- a/trigger_inverter.vhd
+++ b/trigger_inverter.vhd
@@ -27,7 +27,7 @@ begin
 
 invert: process(signals) is                                          -- Ungetaktet
   begin
-  for i in 0 to 31 loop
+  for i in 0 to CHANNELS-1 loop
     if reg_inhalt(i) = '1' then
       processed_signals(i) <= not signals(i);
     else 

diff --git a/trigger_logic.vhd b/trigger_logic.vhd
index 2d5ba47d7b0912f709620231152efbb6ffcfb1a5..1aef9fe27dfe1418bba476ab20514a7bb51240bf 100644 (file)
--- a/trigger_logic.vhd
+++ b/trigger_logic.vhd
@@ -7,8 +7,8 @@ library work;
   
 entity trigger_logic is
   generic(
-    INPUTS  : integer := 32;          -- Doppel definiert ( auch in tb ??)
-    OUTPUTS : integer := 32
+    INPUTS  : integer := 24;          -- Doppel definiert ( auch in tb ??)
+    OUTPUTS : integer := 8
     );
   port(
     CLK      : in std_logic;
@@ -28,8 +28,8 @@ end entity;
 
 architecture arch of trigger_logic is
 
-signal CHANNELS : integer ;
-signal CHANNELS_OUT : integer ;
+constant CHANNELS : integer := INPUTS + OUTPUTS;
+constant CHANNELS_OUT : integer := OUTPUTS ;
 
 --Registers
 signal reg_enable1 : std_logic_vector(CHANNELS-1 downto 0):=(others => '0');
@@ -97,7 +97,7 @@ signal det_2_delay: std_logic_vector(CHANNELS-1 downto 0);
 signal delay_2_str: std_logic_vector(CHANNELS-1 downto 0);
 signal str_2_cion : std_logic_vector(CHANNELS-1 downto 0);
 signal coin_2_mer : std_logic_vector(CHANNELS-1 downto 0);
-signal mer_2_out  : std_logic_vector(CHANNELS_OUT-1 downto 0);
+signal mer_2_out  : std_logic_vector(7 downto 0):= x"00";
 
 
 signal address_i : integer range 0 to 255;
@@ -114,11 +114,15 @@ begin
 
 
 ---------------------------------------------------------------------------
-CHANNELS     <= INPUTS + OUTPUTS;
-CHANNELS_OUT <= OUTPUTS;
+-- CHANNELS     <= INPUTS + OUTPUTS;
+-- CHANNELS_OUT <= OUTPUTS;
 address_i <= to_integer(unsigned(BUS_RX.addr(7 downto 0)));
-in_2_enb  <= INPUT & mer_2_out;
--- in_2_enb  <= INPUT(CHANNELS-1 downto 9) & mer_2_out;
+
+
+
+in_2_enb  <= mer_2_out & INPUT;
+OUTPUT    <= mer_2_out;
+
 
 PROC_REGS : process begin
   wait until rising_edge(CLK);
@@ -203,7 +207,7 @@ PROC_REGS : process begin
 --         when x"0A" =>    reg_edgedetect3  <= BUS_RX.data;
 --         when x"0B" =>    reg_edgedetect4  <= BUS_RX.data;
         when x"0C" =>    reg_delay1       <= BUS_RX.data;
---         when x"0D" =>    reg_delay2       <= BUS_RX.data;      
+--         when x"0D" =>    reg_delay2       <= BUS_RX.data;        
 --         when x"0E" =>    reg_delay3       <= BUS_RX.data;
 --         when x"0F" =>    reg_delay4       <= BUS_RX.data;
         when x"10" =>    reg_stretch1     <= BUS_RX.data;
@@ -260,9 +264,9 @@ end process;
 ---------------------------------------------------------------------------
 
 THE_ENABLE : entity work.trg_enable
--- generic map(
---     CHANNELS         => CHANNELS
---     )
+generic map(
+    CHANNELS         => CHANNELS
+    )
   port map(
   clk_in           => CLK,
   signals          => in_2_enb,
@@ -272,9 +276,9 @@ THE_ENABLE : entity work.trg_enable
   
   
 THE_INVERTER : entity work.trg_inverter
--- generic map(
---     CHANNELS         => CHANNELS
---     )
+generic map(
+    CHANNELS         => CHANNELS
+    )
   port map(
   clk_in           => CLK,
   signals          => enb_2_inv,
@@ -303,7 +307,7 @@ THE_DELAY: entity work.trg_delay
   signal_in       => det_2_delay(i),
   reg_onswitch    => reg_delay1(i),
   delay_time      => delay_time(i), 
---   reset_i         => RESET,
+  reset_i         => RESET,
   processed_signal=> delay_2_str(i)
   );
 end generate;  

diff --git a/trigger_merge.vhd b/trigger_merge.vhd
index c586a090f61e993b3b55dab571d0629f783605ef..2519a76bdf0d017b827e0d8dd70a52283938e5dd 100644 (file)
--- a/trigger_merge.vhd
+++ b/trigger_merge.vhd
@@ -21,13 +21,13 @@ end trg_merge;
   
 architecture behave of trg_merge is 
 
-signal merged_signal : std_logic_vector(31 downto 0);
-signal merged_signal_int : integer range 0 to 1022;
+-- signal merged_signal : std_logic_vector(31 downto 0);
+-- signal merged_signal_int : integer range 0 to 1022;
   
   
   
 begin
-merged_signal_int <= to_integer(unsigned(merged_signal(31 downto 0)));
+-- merged_signal_int <= to_integer(unsigned(merged_signal(31 downto 0)));
 
 -- PROC_combineChannels: process begin
 -- wait until rising_edge(clk_in);
@@ -37,24 +37,63 @@ merged_signal_int <= to_integer(unsigned(merged_signal(31 downto 0)));
 --   else
 --     merged_signal(i) <= '0';
 --   end if;
+--   
 --   if merged_signal_int > 0 then                                                                       -- 
 --     processed_signal <= '1';
 --   end if;
+--   
 -- end loop;
 -- 
 -- end process;
-PROC_combineChannels: process begin
-wait until rising_edge(clk_in);
-for i in 0 to 31 loop
-  if signals(i)='1' and reg_inhalt(i)='1' then
-     processed_signal <= '1';
-  else
-    processed_signal <= '0';
-  end if;
-end loop;
+processed_signal <= or_all (signals and reg_inhalt);
 
-end process;
+
+-- PROC_combineChannels: process begin                  --sehr falsch
+-- wait until rising_edge(clk_in);
+-- for i in 0 to 31 loop
+--   if signals(i)='1' and reg_inhalt(i)='1' then
+--      processed_signal <= '1';
+--   else
+--     processed_signal <= '0';
+--   end if;
+-- end loop;
+-- end process;
 
 
 
 end behave;
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

diff --git a/trigger_strech.vhd b/trigger_strech.vhd
deleted file mode 100644 (file)
index f494780..0000000
--- a/trigger_strech.vhd
+++ /dev/null
@@ -1,133 +0,0 @@
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.numeric_std.all;
-  
-library work;
-  use work.trb_net_std.all;
-  
-  
-entity trg_stretch is
-  port(
-  clk_in      : in std_logic;
-  signal_in     : in std_logic;
-  stretch_type    : in std_logic_vector (1 downto 0);
-  stretch_time    : in std_logic_vector (9 downto 0);
-  processed_signal   : out std_logic
-    );
-end trg_stretch;
-  
-  
-  
- 
-  
-architecture behave of trg_stretch is 
-
-signal stretch_type_int : integer range 0 to 5;
-signal stretch_time_int : integer range 0 to 1022;
-signal timer_10 : unsigned(11 downto 0):= x"000";         
-signal timer_11 : unsigned(11 downto 0):= x"000";
-signal pulse_10 : std_logic;                                            -- every 10 us
-signal pulse_11 : std_logic;                                            -- every 10 ms
-signal output : std_logic:='0';
-signal tester : unsigned(31 downto 0):= x"00000000";
-signal downcounter : integer range 0 to 1022;
-signal bessererTest : std_logic;
-
-
-begin
-  processed_signal<=output;
-  stretch_time_int <= to_integer(unsigned(stretch_time(9 downto 0)));                                         -- umschreiben passt noch nicht
-  stretch_type_int <= to_integer(unsigned(stretch_type(1 downto 0)));
---   output <= '1';
---   bessererTest <= '1';
-
--- PROC_STRETCH_1: process begin
---  wait until rising_edge(clk_in);
---   if signal_in='1' then
---     output<='1';
---     downcounter<=stretch_time_int;
---   elsif signal_in='0' then
---     if stretch_type_int = 0 then 
---       output <= '0';
---     end if;
---     if stretch_type_int = 1 then
---       tester<= tester +1 ;
---       if downcounter> 0 then
---         downcounter <= downcounter -1;
---       else 
---         output<='0';
---       end if;
---     end if; 
---     if stretch_type_int= 2 then
---       if downcounter > 0 and pulse_10='1' then
---         downcounter<= downcounter -1 ;
---       else
---         output<='0';
---       end if;
---     end if;
---     if stretch_type_int = 3 then
---       if downcounter>0 and pulse_11='1' then
---         downcounter<= downcounter -1 ;
---       else
---         output<='0';
---       end if;
---     end if;
---   end if;
--- end process;
-
-PROC_STRETCH_1: process begin
- wait until rising_edge(clk_in);
-  if signal_in='1' then
-    output<='1';
-    downcounter<=stretch_time_int;
-  elsif signal_in='0' then
-    if stretch_type_int = 0 then 
-      output <= '0';
-    elsif stretch_type_int = 1 then
-      tester<= tester +1 ;
-      if downcounter> 0 then
-        downcounter <= downcounter -1;
-      else 
-        output<='0';
-      end if;
-    elsif stretch_type_int= 2 then
-      if downcounter > 0 and pulse_10='1' then
-        downcounter<= downcounter -1 ;
-      else
-        output<='0';
-      end if;
-    elsif stretch_type_int = 3 then
-      if downcounter>0 and pulse_11='1' then
-        downcounter<= downcounter -1 ;
-      else
-        output<='0';
-      end if;
-    end if;
-  end if;
-end process;
-
-
-PROC_PULSEGENERATOR: process begin
-  wait until rising_edge (clk_in);
-  if timer_10=x"3E8" then 
-    pulse_10<='1';
-    timer_10<=x"000" ;
-  else   
-    timer_10 <= timer_10+1;
-    pulse_10<='0';
-  end if;
-  if timer_11= x"3E8"then
-    pulse_11<='1';
-    timer_11<=x"000";
-  elsif pulse_10='1' then  
-    timer_11<=timer_11+1;
-    pulse_11<='0';
-    else 
-    pulse_11<='0';
-  end if; 
-end process;
-  
-
-
-
-end behave;

diff --git a/trigger_stretch.vhd b/trigger_stretch.vhd
new file mode 100644 (file)
index 0000000..0d0d9c4
--- /dev/null
+++ b/trigger_stretch.vhd
@@ -0,0 +1,191 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.numeric_std.all;
+  
+library work;
+  use work.trb_net_std.all;
+  
+  
+entity trg_stretch is
+  port(
+  clk_in      : in std_logic;
+  signal_in     : in std_logic;
+  stretch_type    : in std_logic_vector (1 downto 0);
+  stretch_time    : in std_logic_vector (9 downto 0);
+  processed_signal   : out std_logic
+    );
+end trg_stretch;
+  
+  
+  
+ 
+  
+architecture behave of trg_stretch is 
+
+signal stretch_type_int : integer range 0 to 5;
+signal stretch_time_int : integer range 0 to 1022;
+signal timer_10 : unsigned(11 downto 0):= x"000";         
+signal timer_11 : unsigned(11 downto 0):= x"000";
+signal timer_type1 : unsigned(11 downto 0):= x"000";
+signal timer_type2 : unsigned(19 downto 0):= x"00000";
+signal pulse_10 : std_logic;                                            -- every 10 us
+signal pulse_11 : std_logic;                                            -- every 10 ms
+signal output : std_logic:='0';
+signal tester : unsigned(31 downto 0):= x"00000000";
+signal downcounter : integer range 0 to 1022;
+signal bessererTest : std_logic;
+
+
+begin
+  processed_signal<=output;                                           --unnoetig ?
+  stretch_time_int <= to_integer(unsigned(stretch_time(9 downto 0)));       
+  stretch_type_int <= to_integer(unsigned(stretch_type(1 downto 0)));
+--   output <= '1';
+--   bessererTest <= '1';
+
+-- PROC_STRETCH_1: process begin
+--  wait until rising_edge(clk_in);
+--   if signal_in='1' then  
+--     output<='1';
+--     downcounter<=stretch_time_int;
+--   elsif signal_in='0' then
+--     if stretch_type_int = 0 then 
+--       output <= '0';
+--     end if;
+--     if stretch_type_int = 1 then
+--       tester<= tester +1 ;
+--       if downcounter> 0 then
+--         downcounter <= downcounter -1;
+--       else 
+--         output<='0';
+--       end if;
+--     end if; 
+--     if stretch_type_int= 2 then
+--       if downcounter > 0 and pulse_10='1' then
+--         downcounter<= downcounter -1 ;
+--       else
+--         output<='0';
+--       end if;
+--     end if;
+--     if stretch_type_int = 3 then
+--       if downcounter>0 and pulse_11='1' then
+--         downcounter<= downcounter -1 ;
+--       else
+--         output<='0';
+--       end if;
+--     end if;
+--   end if;
+-- end process;
+
+PROC_STRETCH_1: process begin
+ wait until rising_edge(clk_in);
+  if signal_in='1' then
+    output<='1';
+    downcounter<= stretch_time_int +1;
+    timer_type1<= x"000";
+    timer_type2<= x"00000";
+  elsif output='1' then
+  
+      case stretch_type_int is 
+      when 0 => output<= '0';
+
+      when 1 => 
+        if downcounter> 1 then
+          downcounter <= downcounter -1;
+        else 
+          output<='0';
+        end if;
+      
+      when 2 =>
+        if downcounter > 1 then 
+          if timer_type1<1000 then
+            timer_type1<= timer_type1+1;
+          else 
+            downcounter<= downcounter-1;
+            timer_type1<= x"000";
+          end if;
+        else
+          output<='0';
+        end if;
+        
+        
+       when 3 =>
+        if downcounter > 1 then
+          if timer_type2<1000000 then
+            timer_type2<= timer_type2+1;
+          else
+            downcounter<= downcounter -1 ;
+            timer_type2<=x"00000";
+            tester<= tester +1 ;
+          end if;
+        else
+          output<='0';
+        end if;
+        
+        
+        
+      when others => output<='0';
+      
+      end case;
+    end if;
+  end process;
+  
+--     if stretch_type_int = 0 then 
+--       output <= '0';
+      
+--     elsif stretch_type_int = 1 then  -- counts down with every rising edge
+--       
+--       
+--       
+--     elsif stretch_type_int= 2 then    
+--                                                                       -- counts down every 1000 edges 
+--       if downcounter > 0 then 
+--           if timer_type1<1000 then
+--             timer_type1<= timer_type1+1;
+--           else 
+--             downcounter<= downcounter-1;
+--           end if;
+--       else
+--         output<='0';
+--       end if;
+--       
+--     elsif stretch_type_int = 3 then
+--       if downcounter>0 then
+--         if timer_type2<1000000 then
+--           timer_type2<= timer_type2+1;
+--         else
+--           downcounter<= downcounter -1 ;
+--           tester<= tester +1 ;
+--         end if;
+--       else
+--         output<='0';
+--       end if;
+--     end if;
+--   end if;
+-- end process;
+-- 
+-- 
+-- PROC_PULSEGENERATOR: process begin
+-- --   wait until rising_edge (clk_in);
+--   if timer_10=x"3E8" then 
+--     pulse_10<='1';
+--     timer_10<=x"000" ;
+--   else   
+--     timer_10 <= timer_10+1;
+--     pulse_10<='0';
+--   end if;
+--   if timer_11= x"3E8"then
+--     pulse_11<='1';
+--     timer_11<=x"000";
+--   elsif pulse_10='1' then  
+--     timer_11<=timer_11+1;
+--     pulse_11<='0';
+--     else 
+--     pulse_11<='0';
+--   end if; 
+-- end process;
+--   
+
+
+
+end behave;