hub nobkpl first working version

diff --git a/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd b/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd
index 30ebef43835b05e441b4482ac21747a5a32758a0..61d2bfc9131b3dac75404b85a4543941b619d978 100644 (file)
--- a/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd
+++ b/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd
@@ -11,7 +11,6 @@ use work.med_sync_define_RS.all;
 
 entity med_ecp3_sfp_sync_all_RS is
   generic(
-    SERDES_NUM         : integer := 3;
     SIM_MODE           : integer := 0;
     IS_MODE            : int_array_t(0 to 3) := (c_IS_UNUSED, c_IS_UNUSED, c_IS_UNUSED, c_IS_UNUSED);
     IS_WAP_ZERO        : integer := 1
@@ -257,8 +256,6 @@ begin
 -------------------------------------------------      
 -- Serdes
 -------------------------------------------------      
--- include this for certain designs (placement!)
---  gen_pcs3: if SERDES_NUM = 3 generate -- needed for LPF constraints, should be changed
   THE_SERDES : entity work.serdes_sync_all_RS
     port map(
       hdinp_ch0            => hdinp(0),
@@ -291,7 +288,7 @@ begin
       rx_cdr_lol_ch0_s     => rx_cdr_lol(0),
       tx_div2_mode_ch0_c   => '0',
       rx_div2_mode_ch0_c   => '0',
-      
+      --
       hdinp_ch1            => hdinp(1),
       hdinn_ch1            => hdinn(1),
       hdoutp_ch1           => hdoutp(1),
@@ -322,7 +319,7 @@ begin
       rx_cdr_lol_ch1_s     => rx_cdr_lol(1),
       tx_div2_mode_ch1_c   => '0',
       rx_div2_mode_ch1_c   => '0',
-
+      --
       hdinp_ch2            => hdinp(2),
       hdinn_ch2            => hdinn(2),
       hdoutp_ch2           => hdoutp(2),
@@ -353,7 +350,7 @@ begin
       rx_cdr_lol_ch2_s     => rx_cdr_lol(2),
       tx_div2_mode_ch2_c   => '0',
       rx_div2_mode_ch2_c   => '0',
-      
+      --
       hdinp_ch3            => hdinp(3),
       hdinn_ch3            => hdinn(3),
       hdoutp_ch3           => hdoutp(3),
@@ -384,7 +381,7 @@ begin
       rx_cdr_lol_ch3_s     => rx_cdr_lol(3),
       tx_div2_mode_ch3_c   => '0',
       rx_div2_mode_ch3_c   => '0',      
-      
+      --
       SCI_WRDATA           => sci_data_in_i,
       SCI_RDDATA           => sci_data_out_i,
       SCI_ADDR             => sci_addr_i,
@@ -403,7 +400,6 @@ begin
       serdes_rst_qd_c      => '0', -- was wrong
       tx_sync_qd_c         => SYNC_TX_PLL_IN
     );
---  end generate;
     
 gen_control : for i in 0 to 3 generate   
   gen_used_control : if (IS_MODE(i) = c_IS_SLAVE) or (IS_MODE(i) = c_IS_MASTER) generate