for testing: SCI bug workaround added

diff --git a/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd b/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd
index 42879e14ec2be74cb9cd98ad82971888d992d2eb..f769ac6e7abbe81ee7fabfed60b863193553d08a 100644 (file)
--- a/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd
+++ b/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd
@@ -103,6 +103,11 @@ architecture med_ecp3_sfp_sync_all_RS_arch of med_ecp3_sfp_sync_all_RS is
   signal sci_write_i        : std_logic;
 
   signal wa_position_i      : std_logic_vector(15 downto 0) := x"FFFF";
+  signal wap_requested_i    : std_logic_vector(15 downto 0);
+  signal wap_req_i          : std_logic_vector(3 downto 0);
+  signal wap_req_all        : std_logic;
+--  signal wap_req_all_q      : std_logic;
+  signal wap_req_all_q      : std_logic_vector(2 downto 0);
   
   signal stat_rx_control_i  : std_logic_vector(4*32-1 downto 0);
   signal stat_tx_control_i  : std_logic_vector(4*32-1 downto 0);
@@ -139,12 +144,9 @@ architecture med_ecp3_sfp_sync_all_RS_arch of med_ecp3_sfp_sync_all_RS is
   signal word_sync_sel      : std_logic;
 
   signal link_active_i      : std_logic_vector(3 downto 0);
-
-  signal wap_requested_i    : std_logic_vector(15 downto 0);
   
   signal rx_index_i         : std_logic_vector(3 downto 0);
   signal dlm_result_i       : std_logic_vector(4*32-1 downto 0);
-
   
   signal quad_mode : integer range 0 to 100;
 
@@ -466,6 +468,7 @@ gen_control : for i in 0 to 3 generate
         TX_PLL_LOL_IN      => TX_PLL_LOL_IN,
         WA_POSITION_IN     => wa_position_i(i*4+3 downto i*4),
         WAP_REQUESTED_IN   => wap_requested_i(i*4+3 downto i*4),
+        WAP_REQ_OUT        => wap_req_i(i),
         -- control signals to SerDes
         RX_SERDES_RST      => rx_serdes_rst(i),
         RX_PCS_RST         => rx_pcs_rst(i),
@@ -509,6 +512,7 @@ gen_control : for i in 0 to 3 generate
     rx_serdes_rst(i)           <= '1'; -- keep in reset
     rx_pcs_rst(i)              <= '1'; -- keep in reset
     rx_index_i(i)              <= '0';
+    wap_req_i(i)               <= '0';
     MEDIA_MED2INT(i).dataready <= '0';
     MEDIA_MED2INT(i).tx_read   <= '1';
     MEDIA_MED2INT(i).stat_op   <= x"0007";
@@ -537,6 +541,20 @@ end generate;
   RX_DLM_OUT     <= rx_dlm_i;
   DLM_RESULT_OUT <= dlm_result_i;
 
+  wap_req_all <= wap_req_i(0) or wap_req_i(1) or wap_req_i(2) or wap_req_i(3);
+
+--  SYNC_REQ_0: entity work.signal_sync 
+--  generic map( WIDTH => 1 )
+--  port map(
+--    RESET    => RESET,
+--    CLK0     => CLK_REF_FULL, 
+--    CLK1     => SYSCLK,
+--    D_IN(0)  => wap_req_all,
+--    D_OUT(0) => wap_req_all_q
+--  );
+  
+  wap_req_all_q(2 downto 0) <= wap_req_all_q(1 downto 0) & wap_req_all when rising_edge(SYSCLK);
+  
   THE_SCI_READER : entity work.sci_reader_RS
     port map(
       CLK         => SYSCLK,
@@ -550,6 +568,9 @@ end generate;
       SCI_WR      => sci_write_i,
       -- WAP
       WA_POS_OUT  => wa_position_i,
+--      WA_REQ_IN   => wap_req_all_q,
+      WA_REQ_IN   => wap_req_all_q(2),
+      WA_ACK_OUT  => open,
       --Slowcontrol
       BUS_RX      => BUS_RX,
       BUS_TX      => BUS_TX,

diff --git a/media_interfaces/sync/main_rx_reset_RS.vhd b/media_interfaces/sync/main_rx_reset_RS.vhd
index f2b2edac8a7fb41e2cba64443804863451fd1bb2..56593795a82b97c8f70c321e818b98d259017f9c 100644 (file)
--- a/media_interfaces/sync/main_rx_reset_RS.vhd
+++ b/media_interfaces/sync/main_rx_reset_RS.vhd
@@ -13,7 +13,6 @@ entity main_rx_reset_RS is
     LOS_IN            : in  std_logic;\r
     SD_LOS_IN         : in  std_logic;\r
     WAP_ZERO_IN       : in  std_logic;\r
-    WAP_ACK_IN        : in  std_logic;\r
     -- outputs\r
     WAP_REQ_OUT       : out std_logic;\r
     RX_SERDES_RST_OUT : out std_logic;\r
@@ -75,7 +74,6 @@ begin
       RX_SERDES_RST_OUT <= '1';\r
       RX_PCS_RST_OUT    <= '1';\r
       LINK_RX_READY_OUT <= '0';\r
-      WAP_REQ_OUT       <= '0';\r
 \r
       rx_sm         <= powerup;\r
       STATE_OUT     <= x"f";\r
@@ -95,7 +93,6 @@ begin
           RX_SERDES_RST_OUT <= '0'; -- needed for RX_LOS to be active\r
           RX_PCS_RST_OUT    <= '1';\r
           LINK_RX_READY_OUT <= '0';\r
-          WAP_REQ_OUT       <= '0';\r
 --          if( (pll_lol_s = '1') or (los_s = '1') or (sd_los_s = '1') ) then\r
           if( (pll_lol_s = '1') or (sd_los_s = '1') ) then\r
             cnt <= (others => '0');\r
@@ -113,7 +110,6 @@ begin
           RX_SERDES_RST_OUT <= '1';\r
           RX_PCS_RST_OUT    <= '1';\r
           LINK_RX_READY_OUT <= '0';\r
-          WAP_REQ_OUT       <= '0';\r
           if( cnt = Tshort ) then\r
             cnt <= (others => '0');\r
             rx_sm <= WAIT_CDR_LOCK;\r
@@ -126,7 +122,6 @@ begin
           RX_SERDES_RST_OUT <= '0';\r
           RX_PCS_RST_OUT    <= '1';\r
           LINK_RX_READY_OUT <= '0';\r
-          WAP_REQ_OUT       <= '0';\r
           if( cnt = Tcdr ) then\r
             cnt <= (others => '0');\r
             rx_sm <= TEST_CDR;\r
@@ -139,7 +134,6 @@ begin
           RX_SERDES_RST_OUT <= '0';\r
           RX_PCS_RST_OUT    <= '1';\r
           LINK_RX_READY_OUT <= '0';\r
-          WAP_REQ_OUT       <= '0';\r
           if( cdr_lol_s = '1' ) then\r
             cnt <= (others => '0');\r
             rx_sm <= APPLY_CDR_RST;\r
@@ -157,7 +151,6 @@ begin
           RX_SERDES_RST_OUT <= '0';\r
           RX_PCS_RST_OUT    <= '1';\r
           LINK_RX_READY_OUT <= '0';\r
-          WAP_REQ_OUT       <= '0';\r
           if( cnt = Tshort ) then\r
             cnt <= (others => '0');\r
             rx_sm <= WAIT_RXPCS_LOCK;\r
@@ -170,7 +163,6 @@ begin
           RX_SERDES_RST_OUT <= '0';\r
           RX_PCS_RST_OUT    <= '0';\r
           LINK_RX_READY_OUT <= '0';\r
-          WAP_REQ_OUT       <= '1';\r
           if( cnt = Tviol ) then\r
             cnt <= (others => '0');\r
             rx_sm <= TEST_RXPCS;\r
@@ -183,7 +175,6 @@ begin
           RX_SERDES_RST_OUT <= '0';\r
           RX_PCS_RST_OUT    <= '0';\r
           LINK_RX_READY_OUT <= '0';\r
-          WAP_REQ_OUT       <= '1';\r
           if( (lsm_s = '0') or (cv_s = '1') ) then\r
             cnt <= (others => '0');\r
             rx_sm <= APPLY_RXPCS_RST;\r
@@ -201,21 +192,30 @@ begin
           RX_SERDES_RST_OUT <= '0';\r
           RX_PCS_RST_OUT    <= '0';\r
           LINK_RX_READY_OUT <= '0';\r
-          WAP_REQ_OUT       <= '0';\r
           cnt <= (others => '0');\r
-          if( wap_zero_s = '1' ) then\r
-            rx_sm <= NORMAL_OP;\r
+          if( cnt = Tshort ) then\r
+            cnt <= (others => '0');\r
+            if( wap_zero_s = '1' ) then\r
+              rx_sm <= NORMAL_OP;\r
+            else\r
+--              rx_sm <= APPLY_RXPCS_RST; -- DOESNT WORK\r
+              rx_sm <= APPLY_CDR_RST;\r
+            end if;\r
           else\r
---            rx_sm <= APPLY_RXPCS_RST; -- DOESNT WORK\r
-            rx_sm <= APPLY_CDR_RST;\r
+            cnt <= cnt + 1;  \r
           end if;\r
+--          if( wap_zero_s = '1' ) then\r
+--            rx_sm <= NORMAL_OP;\r
+--          else\r
+----            rx_sm <= APPLY_RXPCS_RST; -- DOESNT WORK\r
+--            rx_sm <= APPLY_CDR_RST;\r
+--          end if;\r
      \r
         when NORMAL_OP =>\r
           STATE_OUT <= x"8";\r
           RX_SERDES_RST_OUT <= '0';\r
           RX_PCS_RST_OUT    <= '0';\r
           LINK_RX_READY_OUT <= '1';\r
-          WAP_REQ_OUT       <= '0';\r
           cnt <= (others => '0');\r
           if( (lsm_s = '0') or (cv_s = '1') ) then -- DANGEROUS\r
             rx_sm <= APPLY_RXPCS_RST;      \r
@@ -227,7 +227,6 @@ begin
           RX_SERDES_RST_OUT <= '0';\r
           RX_PCS_RST_OUT    <= '0';\r
           LINK_RX_READY_OUT <= '0';\r
-          WAP_REQ_OUT       <= '0';\r
           rx_sm <= POWERUP;\r
 \r
       end case;\r
@@ -243,4 +242,6 @@ begin
     end if;\r
   end process rx_reset_proc;\r
 \r
+  WAP_REQ_OUT <= '1' when ((rx_sm = WAIT_RXPCS_LOCK) or (rx_sm = TEST_RXPCS)) else '0';\r
+  \r
 end architecture;\r

diff --git a/media_interfaces/sync/med_sync_control_RS.vhd b/media_interfaces/sync/med_sync_control_RS.vhd
index 86f6b66c53a14f184894582c44c160f94942f5e6..9ea5a1fa29d94dfbb91a32b58f69b6c5c25aca58 100644 (file)
--- a/media_interfaces/sync/med_sync_control_RS.vhd
+++ b/media_interfaces/sync/med_sync_control_RS.vhd
@@ -32,6 +32,7 @@ entity med_sync_control_RS is
     TX_PLL_LOL_IN      : in  std_logic; -- wired'or from all QUADs
     WA_POSITION_IN     : in  std_logic_vector(3 downto 0); -- WordAlignment Position
     WAP_REQUESTED_IN   : in  std_logic_vector(3 downto 0); -- TESTTESTTEST
+    WAP_REQ_OUT        : out std_logic;
     -- control signals to SerDes
     RX_SERDES_RST      : out std_logic; -- reset RX (SerDes + CDR)
     RX_PCS_RST         : out std_logic; -- reset RX (PCS)
@@ -139,6 +140,7 @@ begin
       SD_LOS_IN         => SFP_LOS_IN,
       WAP_ZERO_IN       => is_wap_zero_i,
       -- outputs
+      WAP_REQ_OUT       => WAP_REQ_OUT,
       RX_SERDES_RST_OUT => rx_serdes_rst_i, -- CLK_REF based
       RX_PCS_RST_OUT    => rx_pcs_rst_i, -- CLK_REF based
       LINK_RX_READY_OUT => link_rx_ready_i, --LINK_RX_READY_OUT, -- CLK_REF based

diff --git a/media_interfaces/sync/med_sync_define_RS.vhd b/media_interfaces/sync/med_sync_define_RS.vhd
index 0f8570b64c9d265e7f4a5a27a639c0ce9ba968d6..d616d68f4261a2c35ac0f8298eb6ee1abebfa90b 100644 (file)
--- a/media_interfaces/sync/med_sync_define_RS.vhd
+++ b/media_interfaces/sync/med_sync_define_RS.vhd
@@ -37,6 +37,7 @@ component main_rx_reset_RS is
     SD_LOS_IN         : in  std_logic;\r
     WAP_ZERO_IN       : in  std_logic;\r
     -- outputs\r
+    WAP_REQ_OUT       : out std_logic;\r
     RX_SERDES_RST_OUT : out std_logic;\r
     RX_PCS_RST_OUT    : out std_logic;\r
     LINK_RX_READY_OUT : out std_logic;\r

diff --git a/media_interfaces/sync/sci_reader_RS.vhd b/media_interfaces/sync/sci_reader_RS.vhd
index 0dfe76614508643b89cb5acc06c06dac72a4986b..2ea0f3f4d1840173d41cf01ba9d3e2456d2bb1ad 100644 (file)
--- a/media_interfaces/sync/sci_reader_RS.vhd
+++ b/media_interfaces/sync/sci_reader_RS.vhd
@@ -13,7 +13,6 @@ entity sci_reader_RS is
   port(
     CLK              : in std_logic;
     RESET            : in std_logic;
-    
     --SCI
     SCI_WRDATA       : out std_logic_vector(7 downto 0);
     SCI_RDDATA       : in  std_logic_vector(7 downto 0);
@@ -21,32 +20,40 @@ entity sci_reader_RS is
     SCI_SEL          : out std_logic_vector(4 downto 0);
     SCI_RD           : out std_logic;
     SCI_WR           : out std_logic;
-    
+    -- WAP stuff
     WA_POS_OUT       : out std_logic_vector(15 downto 0);
-    
+    WA_REQ_IN        : in  std_logic;
+    WA_ACK_OUT       : out std_logic;
     --Slowcontrol
     BUS_RX           : in  CTRLBUS_RX;
     BUS_TX           : out CTRLBUS_TX;    
-    
     MEDIA_STATUS_REG_IN : in std_logic_vector(255 downto 0) := (others => '0');
     DEBUG_OUT        : out std_logic_vector(31 downto 0)
-    );
+  );
 end entity;
 
 
 
 architecture sci_reader_arch of sci_reader_RS is
 
-signal sci_reg_i  : std_logic;
 type sci_ctrl is (IDLE, SCTRL, SCTRL_WAIT, SCTRL_WAIT2, SCTRL_FINISH, GET_WA, GET_WA_WAIT, GET_WA_WAIT2, GET_WA_FINISH);
+
 signal sci_state         : sci_ctrl;
 signal sci_timer         : unsigned(12 downto 0) := (others => '0');
+
+signal sci_reg_i         : std_logic;
 signal wa_position       : std_logic_vector(15 downto 0);
 signal next_sci_wr       : std_logic;
+--signal wap_req_q         : std_logic_vector(2 downto 0);
 
 begin
 
-WA_POS_OUT <= wa_position;
+--  THE_SYNC_PROC: process( CLK )
+--  begin
+--    if( rising_edge(CLK) ) then
+--      wap_req_q(2 downto 0) <= wap_req_q(1 downto 0) & WA_REQ_IN;
+--    end if;
+--  end process THE_SYNC_PROC;
 
 -------------------------------------------------      
 -- SCI
@@ -56,88 +63,90 @@ WA_POS_OUT <= wa_position;
   BUS_TX.rack    <= '0';
   BUS_TX.wack    <= '0';
 
-PROC_SCI_CTRL: process 
-  variable cnt : integer range 0 to 4 := 0;
-begin
-  wait until rising_edge(CLK);
-  BUS_TX.ack <= '0';
-  BUS_TX.nack <= '0';
-  
-  SCI_WR <= next_sci_wr;
+  PROC_SCI_CTRL: process 
+    variable cnt : integer range 0 to 4 := 0;
+  begin
+    wait until rising_edge(CLK);
+    BUS_TX.ack <= '0';
+    BUS_TX.nack <= '0';
+   
+    SCI_WR <= next_sci_wr;
+   
+    case sci_state is
+      when IDLE =>
+        SCI_SEL     <= (others => '0');
+        sci_reg_i   <= '0';
+        SCI_RD      <= '0';
+        next_sci_wr <= '0';
+        sci_timer   <= sci_timer + 1;
+        if( (BUS_RX.read = '1') or (BUS_RX.write = '1') ) then
+          SCI_SEL(0)    <= not BUS_RX.addr(6) and not BUS_RX.addr(7) and not BUS_RX.addr(8);
+          SCI_SEL(1)    <=     BUS_RX.addr(6) and not BUS_RX.addr(7) and not BUS_RX.addr(8);
+          SCI_SEL(2)    <= not BUS_RX.addr(6) and     BUS_RX.addr(7) and not BUS_RX.addr(8);
+          SCI_SEL(3)    <=     BUS_RX.addr(6) and     BUS_RX.addr(7) and not BUS_RX.addr(8);
+          SCI_SEL(4)    <= not BUS_RX.addr(6) and not BUS_RX.addr(7) and     BUS_RX.addr(8);
+          sci_reg_i     <=     BUS_RX.addr(6) and not BUS_RX.addr(7) and     BUS_RX.addr(8);
+          SCI_ADDR      <= BUS_RX.addr(5 downto 0);
+          SCI_WRDATA    <= BUS_RX.data(7 downto 0);
+          SCI_RD        <= BUS_RX.read  and not (BUS_RX.addr(6) and not BUS_RX.addr(7) and     BUS_RX.addr(8));
+          next_sci_wr   <= BUS_RX.write and not (BUS_RX.addr(6) and not BUS_RX.addr(7) and     BUS_RX.addr(8));
+          sci_state     <= SCTRL;
+--        elsif( (sci_timer(sci_timer'left) = '1') and (wap_req_q(2) = '1') ) then
+        elsif( (sci_timer(sci_timer'left) = '1') and (WA_REQ_IN = '1') ) then
+          sci_timer     <= (others => '0');
+          sci_state     <= GET_WA;
+        end if;      
+      when SCTRL =>
+        if( sci_reg_i = '1' ) then
+          BUS_TX.data   <= MEDIA_STATUS_REG_IN(32*(to_integer(unsigned(BUS_RX.addr(3 downto 0))))+31 downto 32*(to_integer(unsigned(BUS_RX.addr(3 downto 0)))));
+          BUS_TX.ack    <= '1';
+          next_sci_wr   <= '0';
+          SCI_RD        <= '0';
+          sci_state     <= IDLE;
+        else
+          sci_state     <= SCTRL_WAIT;
+        end if;
+      when SCTRL_WAIT   =>
+        sci_state       <= SCTRL_WAIT2;
+      when SCTRL_WAIT2  =>
+        sci_state       <= SCTRL_FINISH;
+      when SCTRL_FINISH =>
+        BUS_TX.data(7 downto 0) <= SCI_RDDATA;
+        BUS_TX.ack      <= '1';
+        next_sci_wr     <= '0';
+         SCI_RD          <= '0';
+        sci_state       <= IDLE;
+      when GET_WA =>
+        if( ((cnt = 4) and (FPGA_TYPE = 3)) or ((cnt = 2) and (FPGA_TYPE = 5)) ) then
+          cnt           := 0;
+          sci_state     <= IDLE;
+        else
+          sci_state     <= GET_WA_WAIT;
+          if( FPGA_TYPE = 3 ) then
+            SCI_ADDR      <= "100010";--'0' & x"22"; --for ECP3
+          elsif( FPGA_TYPE = 5 ) then
+            SCI_ADDR      <= "110010";--'0' & x"32"; --for ECP5
+          end if;  
+          SCI_SEL       <= (others => '0');
+          SCI_SEL(cnt)  <= '1';
+          SCI_RD        <= '1';
+        end if;
+      when GET_WA_WAIT  =>
+        sci_state       <= GET_WA_WAIT2;
+      when GET_WA_WAIT2 =>
+        sci_state       <= GET_WA_FINISH;
+      when GET_WA_FINISH =>
+        wa_position(cnt*4+3 downto cnt*4) <= SCI_RDDATA(3 downto 0);
+        sci_state       <= GET_WA;
+        cnt             := cnt + 1;
+    end case;
   
-  case sci_state is
-    when IDLE =>
-      SCI_SEL     <= (others => '0');
-      sci_reg_i   <= '0';
-      SCI_RD      <= '0';
-      next_sci_wr <= '0';
-      sci_timer   <= sci_timer + 1;
-      if BUS_RX.read = '1' or BUS_RX.write = '1' then
-        SCI_SEL(0)    <= not BUS_RX.addr(6) and not BUS_RX.addr(7) and not BUS_RX.addr(8);
-        SCI_SEL(1)    <=     BUS_RX.addr(6) and not BUS_RX.addr(7) and not BUS_RX.addr(8);
-        SCI_SEL(2)    <= not BUS_RX.addr(6) and     BUS_RX.addr(7) and not BUS_RX.addr(8);
-        SCI_SEL(3)    <=     BUS_RX.addr(6) and     BUS_RX.addr(7) and not BUS_RX.addr(8);
-        SCI_SEL(4)    <= not BUS_RX.addr(6) and not BUS_RX.addr(7) and     BUS_RX.addr(8);
-        sci_reg_i     <=     BUS_RX.addr(6) and not BUS_RX.addr(7) and     BUS_RX.addr(8);
-        SCI_ADDR      <= BUS_RX.addr(5 downto 0);
-        SCI_WRDATA    <= BUS_RX.data(7 downto 0);
-        SCI_RD        <= BUS_RX.read  and not (BUS_RX.addr(6) and not BUS_RX.addr(7) and     BUS_RX.addr(8));
-        next_sci_wr   <= BUS_RX.write and not (BUS_RX.addr(6) and not BUS_RX.addr(7) and     BUS_RX.addr(8));
-        sci_state     <= SCTRL;
---      elsif sci_timer(sci_timer'left) = '1' then
---        sci_timer     <= (others => '0');
---        sci_state     <= GET_WA;
-      end if;      
-    when SCTRL =>
-      if sci_reg_i = '1' then
-        BUS_TX.data   <= MEDIA_STATUS_REG_IN(32*(to_integer(unsigned(BUS_RX.addr(3 downto 0))))+31 downto 32*(to_integer(unsigned(BUS_RX.addr(3 downto 0)))));
-        BUS_TX.ack    <= '1';
-        next_sci_wr   <= '0';
-        SCI_RD        <= '0';
-        sci_state     <= IDLE;
-      else
-        sci_state     <= SCTRL_WAIT;
-      end if;
-    when SCTRL_WAIT   =>
-      sci_state       <= SCTRL_WAIT2;
-    when SCTRL_WAIT2  =>
-      sci_state       <= SCTRL_FINISH;
-    when SCTRL_FINISH =>
-      BUS_TX.data(7 downto 0) <= SCI_RDDATA;
-      BUS_TX.ack      <= '1';
-      next_sci_wr     <= '0';
-      SCI_RD          <= '0';
-      sci_state       <= IDLE;
-    
-    when GET_WA =>
-      if (cnt = 4 and FPGA_TYPE = 3) or (cnt = 2 and FPGA_TYPE = 5) then
-        cnt           := 0;
-        sci_state     <= IDLE;
-      else
-        sci_state     <= GET_WA_WAIT;
-        if FPGA_TYPE = 3 then
-          SCI_ADDR      <= "100010";--'0' & x"22"; --for ECP3
-        elsif FPGA_TYPE = 5 then
-          SCI_ADDR      <= "110010";--'0' & x"32"; --for ECP5
-        end if;  
-        SCI_SEL       <= (others => '0');
-        SCI_SEL(cnt)  <= '1';
-        SCI_RD        <= '1';
-      end if;
-    when GET_WA_WAIT  =>
-      sci_state       <= GET_WA_WAIT2;
-    when GET_WA_WAIT2 =>
-      sci_state       <= GET_WA_FINISH;
-    when GET_WA_FINISH =>
-      wa_position(cnt*4+3 downto cnt*4) <= SCI_RDDATA(3 downto 0);
-      sci_state       <= GET_WA;
-      cnt             := cnt + 1;
-  end case;
-  
-  if (BUS_RX.read = '1' or BUS_RX.write = '1') and sci_state /= IDLE then
-    BUS_TX.nack <= '1'; BUS_TX.ack <= '0';
-  end if;
-  
-end process;
+    if( ((BUS_RX.read = '1') or (BUS_RX.write = '1')) and (sci_state /= IDLE) ) then
+      BUS_TX.nack <= '1'; 
+      BUS_TX.ack <= '0';
+    end if;
+  end process PROC_SCI_CTRL;
+
+  WA_POS_OUT <= wa_position;
 
 end architecture;