);
end component;
+component error_check is
+port(
+ RXCLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+
+ DATA1_IN : in std_logic_vector(15 downto 0);
+ DATA1_WR_EN_IN : in std_logic;
+ DATA2_IN : in std_logic_vector(15 downto 0);
+ DATA2_VALID_IN : in std_logic
+
+ );
+end component;
+
signal clk : std_logic := '1';
signal clk251 : std_logic := '1';
);
+err_check1 : error_check
+port map(
+ RXCLK_IN => clk,
+ RESET_IN => reset,
+
+ DATA_TX_IN => data1
+ DATA_TX_DATA_READY_IN => dataready1,
+ DATA_TX_READ_IN => read1,
+ DATA_RX_IN => rxdata1,
+ DATA_RX_VALID_IN => rxdataready1
+
+ );
+
+err_check2 : error_check
+port map(
+ RXCLK_IN => clk,
+ RESET_IN => reset,
+
+ DATA_TX_IN => data2
+ DATA_TX_DATA_READY_IN => dataready2,
+ DATA_TX_READ_IN => read2,
+ DATA_RX_IN => rxdata2,
+ DATA_RX_VALID_IN => rxdataready2
+
+ );
+
-- --Data 1 input
-- process
-- begin