*** empty log message ***

diff --git a/testbenches/tb_trb_net16_rxtx_control.vhd b/testbenches/tb_trb_net16_rxtx_control.vhd
index ef841c1d808b14e3e364988cf5fd2c95770b8d1c..90578b69db496dedfb89deb1f620c3b78b9d6b1c 100644 (file)
--- a/testbenches/tb_trb_net16_rxtx_control.vhd
+++ b/testbenches/tb_trb_net16_rxtx_control.vhd
@@ -99,6 +99,19 @@ architecture arch of rxtxtb is
       );
   end component;
 
+component error_check is
+port(
+       RXCLK_IN             : in  std_logic;
+       RESET_IN             : in  std_logic;
+
+       DATA1_IN             : in  std_logic_vector(15 downto 0);
+       DATA1_WR_EN_IN       : in  std_logic;
+       DATA2_IN             : in  std_logic_vector(15 downto 0);
+       DATA2_VALID_IN       : in  std_logic
+
+  );
+end component;
+
 
   signal clk                     : std_logic := '1';
   signal clk251                  : std_logic := '1';
@@ -554,6 +567,32 @@ THE_ERROR : error_generator
       );
 
 
+err_check1 : error_check
+port map(
+       RXCLK_IN             => clk,
+       RESET_IN             => reset,
+
+       DATA_TX_IN            => data1
+       DATA_TX_DATA_READY_IN => dataready1,
+       DATA_TX_READ_IN       => read1,
+       DATA_RX_IN            => rxdata1,
+       DATA_RX_VALID_IN      => rxdataready1
+
+  );
+
+err_check2 : error_check
+port map(
+       RXCLK_IN             => clk,
+       RESET_IN             => reset,
+
+       DATA_TX_IN            => data2
+       DATA_TX_DATA_READY_IN => dataready2,
+       DATA_TX_READ_IN       => read2,
+       DATA_RX_IN            => rxdata2,
+       DATA_RX_VALID_IN      => rxdataready2
+
+  );
+
 -- --Data 1 input
 --   process
 --     begin