Longer delay lines, IF

diff --git a/amps2/padiwa_amps2.prj b/amps2/padiwa_amps2.prj
index 745b9d9d5441fba697d50d11dbdaefcf4f4ed8d9..1ac8a31a1478fb4054777055b7406f84431e9800 100644 (file)
--- a/amps2/padiwa_amps2.prj
+++ b/amps2/padiwa_amps2.prj
@@ -33,7 +33,7 @@ add_file -vhdl -lib work "../source/Amps2_TempSensor_UID.vhd"
 add_file -vhdl -lib work "../../vhdlbasics/machxo3/flash/flashram.vhd"
 add_file -vhdl -lib work "../../vhdlbasics/machxo3/flash/flash.vhd"
 add_file -verilog -lib work "../../vhdlbasics/machxo3/flash/efb_define_def.v"
-add_file -verilog -lib work "../../vhdlbasics/machxo3/flash/UFM_WB.v"
+add_file -verilog -lib work "../../vhdlbasics/machxo3/flash/UFM_WB_16bit.v"
 add_file -vhdl -lib work "../../vhdlbasics/machxo3/flash/generic_flash_ctrl.vhd"
 
 

diff --git a/amps2/padiwa_amps2.vhd b/amps2/padiwa_amps2.vhd
index 08ba7ec3cd944ae970c7bbaeca79b81c3d2916bc..9d40c3376f9d298871ff896a83a032e2ad6bad0e 100644 (file)
--- a/amps2/padiwa_amps2.vhd
+++ b/amps2/padiwa_amps2.vhd
@@ -41,7 +41,7 @@ end entity;
 \r
 \r
 architecture arch of padiwa_amps2 is\r
-  constant DELAYDEPTH : integer := 16;\r
+  constant DELAYDEPTH : integer := 64;\r
 \r
   attribute NOM_FREQ : string;\r
   attribute NOM_FREQ of clk_source : label is "133.00";\r
@@ -130,9 +130,9 @@ architecture arch of padiwa_amps2 is
   signal temperature_i_s  : std_logic_vector(11 downto 0);\r
   signal comp_setting_s   : std_logic_vector(15 downto 0);\r
 \r
-  signal delayed_inputs   : std_logic_vector(127 downto 0);\r
+  signal delayed_inputs   : std_logic_vector(511 downto 0);\r
   signal selected_delay   : std_logic_vector(8 downto 1);\r
-  signal delayselect      : integer range 0 to 15;\r
+  signal delayselect      : integer range 0 to 63;\r
 \r
   \r
   component OSCH\r
@@ -314,6 +314,7 @@ THE_IO_REG : process begin
         when x"30" => spi_tx_data <= std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,16));\r
         when x"31" => spi_tx_data <= std_logic_vector(to_unsigned(VERSION_NUMBER_TIME/2**16,16));\r
         when x"32" => spi_tx_data <= x"0000";\r
+        when x"ff" => spi_tx_data <= x"0200"; --version\r
         when others => null;\r
       end case;\r
     end if;\r

diff --git a/pinout/padiwa_amps2.lpf b/pinout/padiwa_amps2.lpf
index b3bfbc1d07a87b7771c6f86251f350590007a83d..92b1ef48240fa3e789400fc3c897bce72bb283b2 100644 (file)
--- a/pinout/padiwa_amps2.lpf
+++ b/pinout/padiwa_amps2.lpf
@@ -148,12 +148,12 @@ LOCATE COMP  "TMP_ALERT"    SITE "A8";
 IOBUF PORT  "TMP_ALERT" IO_TYPE=LVTTL33 PULLMODE=UP;
 
 
-UGROUP "StretchA" BBOX 1 16
+UGROUP "StretchA" BBOX 1 32
   BLKNAME THE_STRETCHER/Stretcher_A_1
   ;
 LOCATE UGROUP "StretchA" SITE "R25C6";  
   
-UGROUP "StretchB" BBOX 1 16
+UGROUP "StretchB" BBOX 1 32
   BLKNAME THE_STRETCHER/Stretcher_B_1
   ;
 LOCATE UGROUP "StretchB" SITE "R2C6";  

diff --git a/source/Stretcher.vhd b/source/Stretcher.vhd
index da8fe703bc48792540fd1306975ca6863ccb6067..861b06ef62a00192d725d2c85b78845e5f0d5c02 100644 (file)
--- a/source/Stretcher.vhd
+++ b/source/Stretcher.vhd
@@ -5,7 +5,7 @@
 -- File       : Stretcher.vhd
 -- Author     : cugur@gsi.de
 -- Created    : 2012-11-07
--- Last update: 2016-01-20
+-- Last update: 2018-02-01
 -------------------------------------------------------------------------------
 -- Description: Jan's counting
 -------------------------------------------------------------------------------
@@ -18,7 +18,7 @@ use ieee.numeric_std.all;
 entity Stretcher is
   generic (
     CHANNEL : integer range 1 to 64 := 1;
-    DEPTH   : integer range 1 to 32 := 3);
+    DEPTH   : integer range 1 to 64 := 3);
   port (
     PULSE_IN  : in  std_logic_vector(CHANNEL-1 downto 0);
     PULSE_OUT : out std_logic_vector(CHANNEL*DEPTH-1 downto 0));

diff --git a/source/Stretcher_A.vhd b/source/Stretcher_A.vhd
index 335c123214aad8317f2463d610cf0d8a55bf655a..525ec65cc6a06cff089f1547397d4b2a4ec6aba5 100644 (file)
--- a/source/Stretcher_A.vhd
+++ b/source/Stretcher_A.vhd
@@ -5,7 +5,7 @@
 -- File       : Stretcher_A.vhd
 -- Author     : Cahit Ugur  <c.ugur@gsi.de>
 -- Created    : 2014-11-24
--- Last update: 2016-01-20
+-- Last update: 2018-02-01
 -------------------------------------------------------------------------------
 -- Description: Jan's counting
 -------------------------------------------------------------------------------
@@ -23,7 +23,7 @@ use ieee.numeric_std.all;
 entity Stretcher_A is
   generic (
     CHANNEL : integer range 1 to 64;
-    DEPTH   : integer range 1 to 32 := 3);
+    DEPTH   : integer range 1 to 64 := 3);
   port (
     PULSE_IN  : in  std_logic_vector(CHANNEL*DEPTH-1 downto 0);
     PULSE_OUT : out std_logic_vector(CHANNEL*DEPTH-1 downto 0));

diff --git a/source/Stretcher_B.vhd b/source/Stretcher_B.vhd
index a2d01aacdcccd649b10c6acbe307da1f053c2ca7..842d3333cf2f95abf2e864fedb03ac87ea43ff26 100644 (file)
--- a/source/Stretcher_B.vhd
+++ b/source/Stretcher_B.vhd
@@ -5,7 +5,7 @@
 -- File       : Stretcher_B.vhd
 -- Author     : Cahit Ugur  <c.ugur@gsi.de>
 -- Created    : 2014-11-24
--- Last update: 2016-01-20
+-- Last update: 2018-02-01
 -------------------------------------------------------------------------------
 -- Description: Jan's counting
 -------------------------------------------------------------------------------
@@ -23,7 +23,7 @@ use ieee.numeric_std.all;
 entity Stretcher_B is
   generic (
     CHANNEL : integer range 1 to 64;
-    DEPTH   : integer range 1 to 32 := 3);
+    DEPTH   : integer range 1 to 64 := 3);
   port (
     PULSE_IN  : in  std_logic_vector(CHANNEL*DEPTH-1 downto 0);
     PULSE_OUT : out std_logic_vector(CHANNEL*DEPTH-1 downto 0));