-- APL Transmitter port
APL_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word "application to network"
APL_PACKET_NUM_OUT: out std_logic_vector (1 downto 0);
- APL_WRITE_OUT: out std_logic; -- Data word is valid and should be transmitted
- APL_FIFO_FULL_IN: in std_logic; -- Stop transfer, the fifo is full
+ APL_DATAREADY_OUT : out std_logic; -- Data word is valid and should be transmitted
+ APL_READ_IN : in std_logic; -- Stop transfer, the fifo is full
APL_SHORT_TRANSFER_OUT: out std_logic; --
APL_DTYPE_OUT: out std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr
APL_ERROR_PATTERN_OUT: out std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr
-- address <= x"0008";
-- reghigh <= x"DEAD";
-- reglow <= x"AFFE";
- address <= x"AD01";
- reghigh <= x"000B";
- reglow <= x"000D";
+ address <= x"0001";
+ reghigh <= x"0000";
+ reglow <= x"0000";
process(current_state)
begin
end process;
APL_READ_OUT <= '1'; --just read, do not check
- APL_DTYPE_OUT <= "1111";
+ APL_DTYPE_OUT <= "1000";
APL_ERROR_PATTERN_OUT <= x"12345678";
APL_TARGET_ADDRESS_OUT <= TARGET_ADDRESS;
--APL_DATA_OUT <= reg_counter;
end generate;
- SENDER_CTRL: process (current_state, APL_FIFO_FULL_IN, reg_counter, APL_RUN_IN, RESET, packet_counter, buf_APL_SEND_OUT)
+ SENDER_CTRL: process (current_state, APL_READ_IN, reg_counter, APL_RUN_IN, RESET, packet_counter, buf_APL_SEND_OUT)
begin -- process
next_APL_SEND_OUT <= buf_APL_SEND_OUT;
next_state <= MY_ERROR;
if current_state = IDLE then
if reg_counter = TRANSFER_LENGTH then
next_state <= WAITING;
- elsif APL_FIFO_FULL_IN = '1' then
+ elsif APL_READ_IN = '0' then
next_state <= IDLE;
else
next_APL_SEND_OUT <= buf_APL_SEND_OUT;
next_state <= WAITING;
else
next_state <= RUNNING;
- if APL_FIFO_FULL_IN = '0' then
+ if APL_READ_IN = '1' then
next_counter <= reg_counter +1;
end if;
end if;
APL_DATA_OUT(15 downto 0) <= buf_APL_DATA_OUT;
APL_PACKET_NUM_OUT <= packet_counter;
-APL_WRITE_OUT <= buf_APL_WRITE_OUT;
+APL_DATAREADY_OUT <= buf_APL_WRITE_OUT;
CLK_REG: process(CLK)
-- APL Transmitter port
APL_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word "application to network"
APL_PACKET_NUM_OUT: out std_logic_vector (1 downto 0);
- APL_WRITE_OUT: out std_logic; -- Data word is valid and should be transmitted
- APL_FIFO_FULL_IN: in std_logic; -- Stop transfer, the fifo is full
+ APL_DATAREADY_OUT : out std_logic; -- Data word is valid and should be transmitted
+ APL_READ_IN : in std_logic; -- Stop transfer, the fifo is full
APL_SHORT_TRANSFER_OUT: out std_logic; --
APL_DTYPE_OUT: out std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr
APL_ERROR_PATTERN_OUT: out std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr
current_TYPE_IN <= APL_TYP_IN when (APL_PACKET_NUM_IN = "00" and RESET = '0')
else saved_PACKET_TYPE_IN;
- SENDER_CTRL: process (current_state, APL_FIFO_FULL_IN, reg_counter, APL_RUN_IN, RESET, APL_TYP_IN,
+ SENDER_CTRL: process (current_state, APL_READ_IN, reg_counter, APL_RUN_IN, RESET, APL_TYP_IN,
packet_counter, buf_APL_SEND_OUT, current_TYPE_IN, APL_DATAREADY_IN, APL_PACKET_NUM_IN)
begin -- process
next_APL_SEND_OUT <= buf_APL_SEND_OUT;
-- IDLE
-------------------------------------------------------------------------
if current_state = IDLE then
- if APL_FIFO_FULL_IN = '1' or reg_counter = PREFILL_LENGTH then
+ if APL_READ_IN = '0' or reg_counter = PREFILL_LENGTH then
next_state <= RUNNING;
next_APL_SEND_OUT <= '0';
else
next_state <= WAITING;
else
next_state <= RUNNING;
- if APL_FIFO_FULL_IN = '0' then
+ if APL_READ_IN = '1' then
next_counter <= reg_counter +1;
end if;
end if;
APL_DATA_OUT(15 downto 0) <= buf_APL_DATA_OUT;
APL_PACKET_NUM_OUT <= packet_counter;
-APL_WRITE_OUT <= buf_APL_WRITE_OUT;
+APL_DATAREADY_OUT <= buf_APL_WRITE_OUT;
APL_SEND_OUT <= buf_APL_SEND_OUT;
CLK_REG: process(CLK)
API_TYPE : integer range 0 to 1 := c_API_PASSIVE;
FIFO_TO_INT_DEPTH : integer range 1 to 6 := 1;--std_FIFO_DEPTH;
FIFO_TO_APL_DEPTH : integer range 1 to 6 := 1;--std_FIFO_DEPTH;
- USE_REPLY_CHANNEL : integer range 0 to 1 := std_USE_REPLY_CHANNEL;
FORCE_REPLY : integer range 0 to 1 := std_FORCE_REPLY;
SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION;
USE_VENDOR_CORES : integer range 0 to 1 := c_YES;
-- APL Transmitter port
APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word "application to network"
APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- APL_WRITE_IN : in std_logic; -- Data word is valid and should be transmitted
- APL_FIFO_FULL_OUT : out std_logic; -- Stop transfer, the fifo is full
+ APL_DATAREADY_IN : in std_logic; -- Data word is valid and should be transmitted
+ APL_READ_OUT : out std_logic; -- Stop transfer, the fifo is full
APL_SHORT_TRANSFER_IN : in std_logic; --
APL_DTYPE_IN : in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr
APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr
-- the ports with master or slave in their name are to be mapped by the active api
-- to the init respectivly the reply path and vice versa in the passive api.
-- lets define: the "master" path is the path that I send data on.
+ -- master_data_out and slave_data_in are only used in active API for termination
INT_MASTER_DATAREADY_OUT : out std_logic;
INT_MASTER_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
INT_MASTER_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
signal master_start, master_end, slave_start, slave_end : std_logic;
signal master_running, slave_running : std_logic;
+ signal buf_INT_MASTER_PACKET_NUM_OUT : std_logic_vector(1 downto 0);
+ signal buf_INT_MASTER_DATAREADY_OUT : std_logic;
+
+ signal next_fifo_was_not_empty, fifo_was_not_empty : std_logic;
+
begin
---------------------------------------
-- termination for active api
STAT_FIFO_TO_INT(2 downto 0) <= fifo_to_int_data_in(2 downto 0);
STAT_FIFO_TO_INT(3) <= fifo_to_int_write;
+ STAT_FIFO_TO_INT(5 downto 4) <= buf_INT_MASTER_PACKET_NUM_OUT;
+ STAT_FIFO_TO_INT(6) <= buf_INT_MASTER_DATAREADY_OUT;
+ STAT_FIFO_TO_INT(7) <= INT_MASTER_READ_IN;
STAT_FIFO_TO_INT(10 downto 8) <= fifo_to_int_data_out(2 downto 0);
STAT_FIFO_TO_INT(11) <= fifo_to_int_read;
STAT_FIFO_TO_INT(14) <= fifo_to_int_full;
STAT_FIFO_TO_INT(19) <= fifo_to_apl_read;
STAT_FIFO_TO_INT(20) <= fifo_to_apl_empty;
STAT_FIFO_TO_INT(21) <= fifo_to_apl_write;
- STAT_FIFO_TO_INT(7 downto 4) <= (others => '0');
- STAT_FIFO_TO_INT(13 downto 12) <= (others => '0');
- STAT_FIFO_TO_INT(25 downto 22) <= (others => '0');
+ STAT_FIFO_TO_INT(12) <= fifo_to_int_read_before;
+ STAT_FIFO_TO_INT(13) <= '0';
+ STAT_FIFO_TO_INT(23 downto 22) <= next_INT_MASTER_PACKET_NUM_OUT;
+ STAT_FIFO_TO_INT(24) <= next_INT_MASTER_DATAREADY_OUT;
+ STAT_FIFO_TO_INT(25) <= '0';
STAT_FIFO_TO_INT(28 downto 26) <= state_bits_to_int;
STAT_FIFO_TO_INT(31 downto 29) <= state_bits_to_apl;
---------------------------------------
COMB_READ_IN => '1',
COMB_DATA_IN => next_INT_MASTER_DATA_OUT,
COMB_PACKET_NUM_IN => next_INT_MASTER_PACKET_NUM_OUT,
- SYN_DATAREADY_OUT => INT_MASTER_DATAREADY_OUT,
+ SYN_DATAREADY_OUT => buf_INT_MASTER_DATAREADY_OUT,
SYN_DATA_OUT => INT_MASTER_DATA_OUT,
- SYN_PACKET_NUM_OUT => INT_MASTER_PACKET_NUM_OUT,
+ SYN_PACKET_NUM_OUT => buf_INT_MASTER_PACKET_NUM_OUT,
SYN_READ_IN => INT_MASTER_READ_IN
);
-
+
process(CLK)
begin
if rising_edge(CLK) then
end process;
end generate;
gen_int_nonsbuf : if SECURE_MODE_TO_INT = 0 generate
- INT_MASTER_DATAREADY_OUT <= next_INT_MASTER_DATAREADY_OUT;
+ buf_INT_MASTER_DATAREADY_OUT <= next_INT_MASTER_DATAREADY_OUT;
INT_MASTER_DATA_OUT <= next_INT_MASTER_DATA_OUT;
- INT_MASTER_PACKET_NUM_OUT <= next_INT_MASTER_PACKET_NUM_OUT;
+ buf_INT_MASTER_PACKET_NUM_OUT <= next_INT_MASTER_PACKET_NUM_OUT;
sbuf_free <= INT_MASTER_READ_IN;
end generate;
-
+INT_MASTER_PACKET_NUM_OUT <= buf_INT_MASTER_PACKET_NUM_OUT;
+INT_MASTER_DATAREADY_OUT <= buf_INT_MASTER_DATAREADY_OUT;
---------------------------------------
-- a sbuf (to_apl direction)
---------------------------------------
-- current_combined_trailer <= combined_trailer_F3;
current_data <= fifo_to_int_data_out;
when others =>
- current_combined_header <= "0000000000000" & TYPE_HDR;
+ current_combined_header <= "0000000000000" & TYPE_HDR;
current_registered_trailer <= "0000000000000" & TYPE_TRM;
-- current_combined_trailer <= "0000000000000" & TYPE_TRM;
current_data <= "0000000000000" & TYPE_DAT;
fifo_to_int_read <= '0';
master_start <= '0';
master_end <= '0';
+ next_fifo_was_not_empty <= fifo_was_not_empty or not fifo_to_int_empty;
case state_to_int is
when INACTIVE =>
end if;
end if;
when IDLE =>
+ next_fifo_was_not_empty <= '0';
if APL_SEND_IN = '1' then
master_start <= '1';
if APL_SHORT_TRANSFER_IN = '1' then
when RUNNING =>
fifo_to_int_read <= not fifo_to_int_empty and sbuf_free and or_all(master_counter);
next_INT_MASTER_DATAREADY_OUT <= sbuf_free and (fifo_to_int_read_before or not or_all(master_counter));
- if APL_SEND_IN = '0' then -- terminate the transfer
+ if APL_SEND_IN = '0' and fifo_was_not_empty = '1' then -- terminate the transfer
update_registered_trailer <= '1';
if fifo_to_int_empty = '1' and master_counter = "11" and sbuf_free = '1' then
next_state_to_int <= SEND_TRAILER; -- immediate stop
reg_INT_SLAVE_READ_OUT <= '0';
send_trm_wrong_addr <= '0';
sequence_counter <= (others => '0');
+ fifo_was_not_empty <= '0';
else
state_to_apl <= next_state_to_apl;
state_to_int <= next_state_to_int;
reg_INT_SLAVE_READ_OUT <= next_INT_SLAVE_READ_OUT;
send_trm_wrong_addr <= next_send_trm_wrong_addr;
sequence_counter <= next_sequence_counter;
+ fifo_was_not_empty <= next_fifo_was_not_empty;
end if;
end if;
end process;
-- connect Transmitter port
fifo_to_int_data_in <= APL_DATA_IN;
fifo_to_int_packet_num_in <= APL_PACKET_NUM_IN;
- fifo_to_int_write <= (APL_WRITE_IN and not fifo_to_int_full);
- APL_FIFO_FULL_OUT <= fifo_to_int_full; -- APL has to stop writing
+ fifo_to_int_write <= (APL_DATAREADY_IN and not fifo_to_int_full);
+ APL_READ_OUT <= not fifo_to_int_full; -- APL has to stop writing
-- connect receiver
fifo_to_apl_data_in <= INT_SLAVE_DATA_IN;
-- APL Transmitter port
APL_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word "application to network"
APL_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- APL_WRITE_IN: in std_logic; -- Data word is valid and should be transmitted
- APL_FIFO_FULL_OUT: out std_logic; -- Stop transfer, the fifo is full
+ APL_DATAREADY_IN: in std_logic; -- Data word is valid and should be transmitted
+ APL_READ_OUT: out std_logic; -- Stop transfer, the fifo is full
APL_SHORT_TRANSFER_IN: in std_logic; --
APL_DTYPE_IN: in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr
APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr
API_TYPE : integer range 0 to 1 := c_API_ACTIVE;
FIFO_TO_INT_DEPTH : integer range 1 to 6 := 1;--std_FIFO_DEPTH;
FIFO_TO_APL_DEPTH : integer range 1 to 6 := 1;--std_FIFO_DEPTH;
- USE_REPLY_CHANNEL : integer range 0 to 1 := std_USE_REPLY_CHANNEL;
FORCE_REPLY : integer range 0 to 1 := std_FORCE_REPLY;
SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION;
USE_VENDOR_CORES : integer range 0 to 1 := c_YES;
-- APL Transmitter port
APL_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word "application to network"
APL_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- APL_WRITE_IN: in std_logic; -- Data word is valid and should be transmitted
- APL_FIFO_FULL_OUT: out std_logic; -- Stop transfer, the fifo is full
+ APL_DATAREADY_IN: in std_logic; -- Data word is valid and should be transmitted
+ APL_READ_OUT: out std_logic; -- Stop transfer, the fifo is full
APL_SHORT_TRANSFER_IN: in std_logic; --
APL_DTYPE_IN: in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr
APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr
API_TYPE => API_TYPE,
FIFO_TO_INT_DEPTH => FIFO_TO_INT_DEPTH,
FIFO_TO_APL_DEPTH => FIFO_TO_APL_DEPTH,
- USE_REPLY_CHANNEL => cfg_USE_REPLY_CHANNEL(DAT_CHANNEL),
FORCE_REPLY => cfg_FORCE_REPLY(DAT_CHANNEL),
SBUF_VERSION => SBUF_VERSION
)
-- APL Transmitter port
APL_DATA_IN => APL_DATA_IN,
APL_PACKET_NUM_IN => APL_PACKET_NUM_IN,
- APL_WRITE_IN => APL_WRITE_IN,
- APL_FIFO_FULL_OUT => APL_FIFO_FULL_OUT,
+ APL_DATAREADY_IN => APL_DATAREADY_IN,
+ APL_READ_OUT => APL_READ_OUT,
APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN,
APL_DTYPE_IN => APL_DTYPE_IN,
APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN,
API_TYPE => API_TYPE,
FIFO_TO_INT_DEPTH => FIFO_TO_INT_DEPTH,
FIFO_TO_APL_DEPTH => FIFO_TO_APL_DEPTH,
- USE_REPLY_CHANNEL => cfg_USE_REPLY_CHANNEL(DAT_CHANNEL),
FORCE_REPLY => cfg_FORCE_REPLY(DAT_CHANNEL),
SBUF_VERSION => SBUF_VERSION
)
-- APL Transmitter port
APL_DATA_IN => APL_DATA_IN,
APL_PACKET_NUM_IN => APL_PACKET_NUM_IN,
- APL_WRITE_IN => APL_WRITE_IN,
- APL_FIFO_FULL_OUT => APL_FIFO_FULL_OUT,
+ APL_DATAREADY_IN => APL_DATAREADY_IN,
+ APL_READ_OUT => APL_READ_OUT,
APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN,
APL_DTYPE_IN => APL_DTYPE_IN,
APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN,
api_stat_fifo_to_int <= buf_api_stat_fifo_to_int;
STAT_api_control_signals(2 downto 0) <= APL_DATA_IN(2 downto 0);
-STAT_api_control_signals(3) <= APL_WRITE_IN;
+STAT_api_control_signals(3) <= APL_DATAREADY_IN;
STAT_api_control_signals(4) <= APL_SEND_IN;
STAT_api_control_signals(7 downto 5) <= (others => '0');
STAT_api_control_signals(10 downto 8) <= apl_to_buf_INIT_DATA(2 downto 0);
--API: interfaces
APL_DATA_IN : in std_logic_vector (VAL(API_NUMBER*c_DATA_WIDTH) downto 0);
APL_PACKET_NUM_IN : in std_logic_vector (VAL(API_NUMBER*c_NUM_WIDTH) downto 0);
- APL_WRITE_IN : in std_logic_vector (VAL(API_NUMBER) downto 0);
- APL_FIFO_FULL_OUT : out std_logic_vector (VAL(API_NUMBER) downto 0);
+ APL_DATAREADY_IN : in std_logic_vector (VAL(API_NUMBER) downto 0);
+ APL_READ_OUT : out std_logic_vector (VAL(API_NUMBER) downto 0);
APL_SHORT_TRANSFER_IN : in std_logic_vector (VAL(API_NUMBER) downto 0);
APL_DTYPE_IN : in std_logic_vector (VAL(API_NUMBER*4) downto 0);
APL_ERROR_PATTERN_IN : in std_logic_vector (VAL(API_NUMBER*32) downto 0);
signal HC_DATA_IN : std_logic_vector (c_DATA_WIDTH-1 downto 0);
signal HC_PACKET_NUM_IN : std_logic_vector (c_NUM_WIDTH-1 downto 0);
- signal HC_WRITE_IN : std_logic;
- signal HC_FIFO_FULL_OUT : std_logic;
+ signal HC_DATAREADY_IN : std_logic;
+ signal HC_READ_OUT : std_logic;
signal HC_SHORT_TRANSFER_IN : std_logic;
signal HC_DTYPE_IN : std_logic_vector (3 downto 0);
signal HC_ERROR_PATTERN_IN : std_logic_vector (31 downto 0);
API_TYPE : integer range 0 to 1 := c_API_ACTIVE;
FIFO_TO_INT_DEPTH : integer range 1 to 6 := 1;--std_FIFO_DEPTH;
FIFO_TO_APL_DEPTH : integer range 1 to 6 := 1;--std_FIFO_DEPTH;
- USE_REPLY_CHANNEL : integer range 0 to 1 := std_USE_REPLY_CHANNEL;
FORCE_REPLY : integer range 0 to 1 := std_FORCE_REPLY;
SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION;
USE_VENDOR_CORES : integer range 0 to 1 := c_YES;
-- APL Transmitter port
APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word "application to network"
APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- APL_WRITE_IN : in std_logic; -- Data word is valid and should be transmitted
- APL_FIFO_FULL_OUT : out std_logic; -- Stop transfer, the fifo is full
+ APL_DATAREADY_IN : in std_logic; -- Data word is valid and should be transmitted
+ APL_READ_OUT : out std_logic; -- Stop transfer, the fifo is full
APL_SHORT_TRANSFER_IN : in std_logic; --
APL_DTYPE_IN : in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr
APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr
-- Port to API
API_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
API_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- API_WRITE_OUT : out std_logic;
- API_FIFO_FULL_IN : in std_logic;
+ API_DATAREADY_OUT : out std_logic;
+ API_READ_IN : in std_logic;
API_SHORT_TRANSFER_OUT : out std_logic;
API_DTYPE_OUT : out std_logic_vector (3 downto 0);
API_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);
-- APL Transmitter port
APL_DATA_IN => HC_DATA_IN(c_DATA_WIDTH-1 downto 0),
APL_PACKET_NUM_IN => HC_PACKET_NUM_IN(c_NUM_WIDTH-1 downto 0),
- APL_WRITE_IN => HC_WRITE_IN,
- APL_FIFO_FULL_OUT => HC_FIFO_FULL_OUT,
+ APL_DATAREADY_IN => HC_DATAREADY_IN,
+ APL_READ_OUT => HC_READ_OUT,
APL_SHORT_TRANSFER_IN => HC_SHORT_TRANSFER_IN,
APL_DTYPE_IN => HC_DTYPE_IN(3 downto 0),
APL_ERROR_PATTERN_IN => HC_ERROR_PATTERN_IN(31 downto 0),
-- APL Transmitter port
APL_DATA_IN => APL_DATA_IN((aploffset+1)*c_DATA_WIDTH-1 downto aploffset * c_DATA_WIDTH),
APL_PACKET_NUM_IN => APL_PACKET_NUM_IN((aploffset+1)*c_NUM_WIDTH-1 downto aploffset * c_NUM_WIDTH),
- APL_WRITE_IN => APL_WRITE_IN(aploffset),
- APL_FIFO_FULL_OUT => APL_FIFO_FULL_OUT(aploffset),
+ APL_DATAREADY_IN => APL_DATAREADY_IN(aploffset),
+ APL_READ_OUT => APL_READ_OUT(aploffset),
APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN(aploffset),
APL_DTYPE_IN => APL_DTYPE_IN((aploffset+1)*4-1 downto aploffset*4),
APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN((aploffset+1)*32-1 downto aploffset*32),
-- APL Transmitter port
APL_DATA_IN => APL_DATA_IN((aploffset+1)*c_DATA_WIDTH-1 downto aploffset * c_DATA_WIDTH),
APL_PACKET_NUM_IN => APL_PACKET_NUM_IN((aploffset+1)*c_NUM_WIDTH-1 downto aploffset * c_NUM_WIDTH),
- APL_WRITE_IN => APL_WRITE_IN(aploffset),
- APL_FIFO_FULL_OUT => APL_FIFO_FULL_OUT(aploffset),
+ APL_DATAREADY_IN => APL_DATAREADY_IN(aploffset),
+ APL_READ_OUT => APL_READ_OUT(aploffset),
APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN(aploffset),
APL_DTYPE_IN => APL_DTYPE_IN((aploffset+1)*4-1 downto aploffset*4),
APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN((aploffset+1)*32-1 downto aploffset*32),
-- Port to API
API_DATA_OUT => HC_DATA_IN,
API_PACKET_NUM_OUT => HC_PACKET_NUM_IN,
- API_WRITE_OUT => HC_WRITE_IN,
- API_FIFO_FULL_IN => HC_FIFO_FULL_OUT,
+ API_DATAREADY_OUT => HC_DATAREADY_IN,
+ API_READ_IN => HC_READ_OUT,
API_SHORT_TRANSFER_OUT => HC_SHORT_TRANSFER_IN,
API_DTYPE_OUT => HC_DTYPE_IN,
API_ERROR_PATTERN_OUT => HC_ERROR_PATTERN_IN,
--8x CTRL, 8x STAT
-
+ buf_HUB_STAT_GEN(0) <= MED_DATA_IN(14);
+ buf_HUB_STAT_GEN(1) <= buf_to_hub_REPLY_DATA(14);
+ buf_HUB_STAT_GEN(2) <= buf_to_hub_REPLY_DATAREADY(0);
+ buf_HUB_STAT_GEN(31 downto 3) <= (others => '0');
HUB_STAT_GEN <= buf_HUB_STAT_GEN;
HUB_STAT_CHANNEL <= buf_HUB_STAT_CHANNEL;
signal REPLY_MUX_reading : std_logic_vector(POINT_NUMBER-1 downto 0);
- type state_type is (IDLE, SENDING_DATA, SENDING_REPLY_TRM);
+ type state_type is (SENDING_DATA, SENDING_REPLY_TRM);
signal current_state, next_state : state_type;
signal packet_counter : std_logic_vector(1 downto 0);
signal data_counter : std_logic_vector(7 downto 0);
begin
REPLY_HEADER_OUT <= (others => '0');
-STAT(7 downto 0) <= (others => '0');
-STAT(15 downto 8) <= data_counter;
+STAT(0) <= got_trm(0);
+STAT(1) <= got_trm(1);
+STAT(2) <= REPLY_POOL_DATAREADY;
+STAT(3) <= REPLY_DATAREADY_IN(0);
+STAT(4) <= buf_REPLY_READ_OUT(0);
+STAT(5) <= comb_REPLY_muxed_DATA(14);
+
+STAT(6) <= REPLY_DATA_IN(14);
+STAT(7) <= REPLY_DATA_IN(30);
+STAT(8) <= REPLY_DATA_IN(46);
+
+
+STAT(15 downto 9) <= (others => '0');
+--STAT(15 downto 8) <= data_counter;
STAT_POINTS_locked(POINT_NUMBER-1 downto 0) <= not got_trm;
STAT_POINTS_locked(31 downto POINT_NUMBER) <= (others => '0');
STAT_ERRORBITS <= REPLY_combined_trm_F1 & REPLY_combined_trm_F2;
init_arbiter_ENABLE <= not init_locked;
--Datapool for Init-Channel
- INIT_muxed_DATAREADY <= or_all(INIT_DATAREADY_IN) and not init_locked and INIT_muxed_READ;
+ INIT_muxed_DATAREADY <= or_all(INIT_DATAREADY_IN and buf_INIT_READ_OUT) and not init_locked and INIT_muxed_READ;
INIT_POOL_READ <= and_all(INIT_READ_IN or init_has_read_from_pool or locking_point or not real_activepoints);
INIT_READ_OUT <= buf_INIT_READ_OUT;
send_reply_trm <= and_all(got_trm);
get_locked <= INIT_muxed_DATAREADY;
next_locked <= (get_locked or locked) and not release_locked;
- next_locking_point <= (buf_INIT_READ_OUT and INIT_DATAREADY_IN) when (locked = '0' and REPLY_POOL_DATAREADY = '0') else locking_point;
+ next_locking_point <= (INIT_DATAREADY_IN) when (locked = '0' and REPLY_POOL_DATAREADY = '0') else locking_point;
+ --buf_INIT_READ_OUT and
get_init_locked <= '1' when saved_INIT_TYPE = TYPE_TRM and INIT_muxed_PACKET_NUM = "11" else '0';
release_init_locked <= release_locked;
gen_got_trm : process(CLK)
begin
if rising_edge(CLK) then
- if RESET = '1' or send_reply_trm = '1' then
+ if RESET = '1' or send_reply_trm = '1' or locked = '0' then
got_trm <= (others => '0');
else
got_trm <= got_trm or locking_point or reading_trmF2 or not real_activepoints;
STAT(7) <= fifo_empty_m;
STAT(8) <= fifo_full_a;
STAT(9) <= fifo_full_m;
--- STAT(10)<= last_fifo_rd_en_m;
+ STAT(10)<= fifo_dout_m(14);
+ STAT(11)<= fifo_dout_a(14);
+ STAT(12)<= fifo_din_a(14);
-- STAT(11)<= last_fifo_rd_en_a;
STAT(14) <= reg_RX_DV;
STAT(15) <= reg_RX_ER;
-- Port to API
API_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
API_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- API_WRITE_OUT : out std_logic;
- API_FIFO_FULL_IN : in std_logic;
+ API_DATAREADY_OUT : out std_logic;
+ API_READ_IN : in std_logic;
API_SHORT_TRANSFER_OUT : out std_logic;
API_DTYPE_OUT : out std_logic_vector (3 downto 0);
API_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);
signal buf_API_PACKET_NUM_OUT, next_API_PACKET_NUM_OUT : std_logic_vector(1 downto 0);
signal buf_API_DATA_OUT, next_API_DATA_OUT : std_logic_vector(15 downto 0);
signal buf_API_SHORT_TRANSFER_OUT, next_API_SHORT_TRANSFER_OUT : std_logic;
- signal buf_API_WRITE_OUT, next_API_WRITE_OUT : std_logic;
+ signal buf_API_DATAREADY_OUT, next_API_DATAREADY_OUT : std_logic;
signal buf_DAT_DATA_OUT : std_logic_vector(REGISTER_WIDTH-1 downto 0);
signal buf_DAT_READ_ENABLE_OUT, next_DAT_READ_ENABLE_OUT : std_logic;
signal next_REGISTERS_OUT_write_enable : std_logic_vector(2**(NUM_CTRL_REGS)-1 downto 0);
signal reg_enable_pattern : std_logic_vector(2**(NUM_CTRL_REGS)-1 downto 0);
-
signal state_bits : std_logic_vector(2 downto 0);
signal ADR_DATAREADY_IN : std_logic;
API_DATAREADY_OUT => ADR_DATAREADY_OUT,
API_PACKET_NUM_OUT=> ADR_PACKET_NUM_OUT,
API_READ_IN => ADR_READ_IN,
- RAM_DATA_IN => RAM_DATA_IN,
- RAM_DATA_OUT => RAM_DATA_OUT,
- RAM_ADDR_IN => RAM_ADDR_IN,
- RAM_WR_IN => RAM_WR_IN,
+ RAM_DATA_IN => IDRAM_DATA_IN,
+ RAM_DATA_OUT => IDRAM_DATA_OUT,
+ RAM_ADDR_IN => IDRAM_ADDR_IN,
+ RAM_WR_IN => IDRAM_WR_IN,
ADDRESS_REJECTED => ADR_REJECTED,
ADDRESS_OUT => MY_ADDRESS_OUT
);
- RAM_DATA_IN <= (others => '0');
- RAM_WR_IN <= '0';
buf_DAT_ADDR_OUT <= address;
buf_DAT_DATA_OUT <= saved_Reg_high & saved_Reg_low;
fsm : process(current_state,
- API_DATA_IN, API_PACKET_NUM_IN, API_TYP_IN, API_DATAREADY_IN, API_FIFO_FULL_IN, API_RUN_IN,
+ API_DATA_IN, API_PACKET_NUM_IN, API_TYP_IN, API_DATAREADY_IN, API_READ_IN, API_RUN_IN,
HDR_F1, HDR_F2, HDR_F3, address, saved_Reg_high, saved_Reg_low, saved_operation,
buf_API_SEND_OUT, buf_API_PACKET_NUM_OUT, buf_API_DATA_OUT, buf_API_SHORT_TRANSFER_OUT,
REGISTERS_IN, buf_REGISTERS_OUT, reg_enable_pattern, DAT_NO_MORE_DATA_IN,
ADR_READ_IN <= '0';
buf_API_READ_OUT <= '1';
next_API_SEND_OUT <= buf_API_SEND_OUT;
- next_API_WRITE_OUT <= '0';
+ next_API_DATAREADY_OUT <= '0';
next_API_PACKET_NUM_OUT <= buf_API_PACKET_NUM_OUT;
next_API_DATA_OUT <= buf_API_DATA_OUT;
next_API_SHORT_TRANSFER_OUT <= buf_API_SHORT_TRANSFER_OUT;
next_REGISTERS_OUT_write_enable <= (others => '0');
next_DAT_READ_ENABLE_OUT <= '0';
next_DAT_WRITE_ENABLE_OUT <= '0';
- buf_API_ERROR_PATTERN_OUT(0) <= '1';
+
regnum := conv_integer(address(NUM_STAT_REGS-1 downto 0));
end if;
if API_PACKET_NUM_IN = "11" then
next_HDR_F3 <= API_DATA_IN;
+ next_API_PACKET_NUM_OUT <= "11";
case API_DATA_IN(3 downto 0) is
when c_read_register_type => next_state <= ONE_READ;
when c_write_register_type => next_state <= ONE_WRITE;
end if;
when ADDRESS_ACK =>
- ADR_READ_IN <= not API_FIFO_FULL_IN;
+ ADR_READ_IN <= API_READ_IN;
next_API_SEND_OUT <= '1';
- next_API_WRITE_OUT <= ADR_DATAREADY_OUT;
+ next_API_DATAREADY_OUT <= ADR_DATAREADY_OUT;
next_API_DATA_OUT <= ADR_DATA_OUT;
next_API_PACKET_NUM_OUT <= ADR_PACKET_NUM_OUT;
- if ADR_PACKET_NUM_OUT = "11" and not API_FIFO_FULL_IN = '1' then
+ if ADR_PACKET_NUM_OUT = "11" and API_READ_IN = '1' then
next_state <= SEND_REPLY_DATA_finish;
end if;
when REG_READ =>
next_API_SEND_OUT <= '1';
- if API_FIFO_FULL_IN = '1' then
- next_API_WRITE_OUT <= '0';
+ if API_READ_IN = '0' then
+ next_API_DATAREADY_OUT <= '0';
else
- next_API_WRITE_OUT <= '1';
+ next_API_DATAREADY_OUT <= '1';
if buf_API_PACKET_NUM_OUT = "11" then
next_API_PACKET_NUM_OUT <= "01";
next_API_DATA_OUT <= address;
next_API_PACKET_NUM_OUT <= "01";
next_API_DATA_OUT <= address;
next_API_SEND_OUT <= '1';
- next_API_WRITE_OUT <= '1';
+ next_API_DATAREADY_OUT <= '1';
end if;
if buf_API_PACKET_NUM_OUT = "01" then
next_API_PACKET_NUM_OUT <= "10";
next_API_DATA_OUT <= DAT_DATA_IN(31 downto 16);
- next_API_WRITE_OUT <= '1';
+ next_API_DATAREADY_OUT <= '1';
elsif buf_API_PACKET_NUM_OUT = "10" then
next_API_PACKET_NUM_OUT <= "11";
next_API_DATA_OUT <= DAT_DATA_IN(15 downto 0);
- next_API_WRITE_OUT <= '1';
+ next_API_DATAREADY_OUT <= '1';
next_state <= SEND_REPLY_DATA_finish;
end if;
if RESET = '1' then
current_state <= IDLE;
buf_API_SEND_OUT <= '0';
- buf_API_WRITE_OUT <= '0';
+ buf_API_DATAREADY_OUT <= '0';
buf_API_PACKET_NUM_OUT <= "11";
buf_DAT_READ_ENABLE_OUT <= '0';
buf_DAT_WRITE_ENABLE_OUT <= '0';
buf_API_DATA_OUT <= (others => '0');
buf_API_PACKET_NUM_OUT <= (others => '0');
saved_operation <= "0000";
+ saved_Reg_high <= (others => '0');
+ saved_Reg_low <= (others => '0');
else
current_state <= next_state;
HDR_F1 <= next_HDR_F1;
HDR_F2 <= next_HDR_F2;
HDR_F3 <= next_HDR_F3;
buf_API_SEND_OUT <= next_API_SEND_OUT;
- buf_API_WRITE_OUT <= next_API_WRITE_OUT;
+ buf_API_DATAREADY_OUT <= next_API_DATAREADY_OUT;
buf_API_PACKET_NUM_OUT <= next_API_PACKET_NUM_OUT;
buf_API_DATA_OUT <= next_API_DATA_OUT;
buf_API_SHORT_TRANSFER_OUT <= next_API_SHORT_TRANSFER_OUT;
end generate;
end generate;
- buf_API_ERROR_PATTERN_OUT(31 downto 1) <= (others => '0');
+ buf_API_ERROR_PATTERN_OUT(31 downto 0) <= (others => '0');
API_READ_OUT <= buf_API_READ_OUT;
API_SEND_OUT <= buf_API_SEND_OUT;
- API_WRITE_OUT <= buf_API_WRITE_OUT;
+ API_DATAREADY_OUT <= buf_API_DATAREADY_OUT;
API_PACKET_NUM_OUT <= buf_API_PACKET_NUM_OUT;
API_DATA_OUT <= buf_API_DATA_OUT;
API_SHORT_TRANSFER_OUT <= buf_API_SHORT_TRANSFER_OUT;
DAT_ADDR_OUT <= buf_DAT_ADDR_OUT;
REGISTERS_OUT <= buf_REGISTERS_OUT;
- STAT(0) <= ADR_REJECTED;
- STAT(1) <= ADR_READ_IN;
- STAT(2) <= ADR_DATAREADY_OUT;
- STAT(3) <= ADR_DATAREADY_IN;
- STAT(31 downto 4) <= (others => '0');
+STAT(2 downto 0) <= state_bits;
+ STAT(4 downto 3) <= next_API_PACKET_NUM_OUT;
+ STAT(5) <= next_API_DATAREADY_OUT;
+ STAT(14 downto 6) <= next_API_DATA_OUT(8 downto 0);
+ STAT(31 downto 15) <= (others => '0');
process(current_state)
begin
constant ILLEGAL_ADDRESS : std_logic_vector(15 downto 0) := x"0000";
constant BROADCAST_ADDRESS : std_logic_vector(15 downto 0) := x"ffff";
+--command definitions
constant LINK_STARTUP_WORD : std_logic_vector(15 downto 0) := x"e110";
+ constant SET_ADDRESS : std_logic_vector( 7 downto 0) := x"AD";
+ constant ACK_ADDRESS : std_logic_vector(15 downto 0) := x"AADD";
+ constant READ_ID : std_logic_vector(15 downto 0) := x"5B1D";
+
+--common registers
+ constant std_COMSTATREG : integer := 2;
+ constant std_COMCTRLREG : integer := 1;
+
+--RegIO operation dtype
+ constant c_network_control_type : std_logic_vector(3 downto 0) := x"F";
+ constant c_read_register_type : std_logic_vector(3 downto 0) := x"8";
+ constant c_write_register_type : std_logic_vector(3 downto 0) := x"9";
+ constant c_read_multiple_type : std_logic_vector(3 downto 0) := x"A";
+ constant c_write_multiple_type : std_logic_vector(3 downto 0) := x"B";
+
- constant SET_ADDRESS : std_logic_vector(7 downto 0) := x"AD";
- constant ACK_ADDRESS : std_logic_vector(15 downto 0) := x"5ADD";
-
+--function declarations
function and_all (arg : std_logic_vector)
return std_logic;
function or_all (arg : std_logic_vector)
jspc29 / trbnet.git / commitdiff