Padiwa Usb slow-control running

diff --git a/.gitignore b/.gitignore
index 8d45df142b699790c09cd5c477e004510fe17bb2..30702dffcae28e2667a5f29072f75307ff6b57b0 100644 (file)
--- a/.gitignore
+++ b/.gitignore
@@ -21,3 +21,4 @@ reportview.xml
 .kateproject.d
 */project/
 */project2/
+design

diff --git a/pulser/design/padiwa.ldf b/pulser/design/padiwa.ldf
index 0621c387318da485f3b7f1b3bb0390bf9e296292..d3880bdd01f6bfd5d4c6d283a56219924ad1cb08 100644 (file)
--- a/pulser/design/padiwa.ldf
+++ b/pulser/design/padiwa.ldf
@@ -2,9 +2,9 @@
 <BaliProject version="3.0" title="padiwa" device="LCMXO2-4000HC-6FTG256C" default_implementation="pulser">
     <Options/>
     <Implementation title="pulser" dir="pulser" description="pulser" synthesis="synplify" default_strategy="Strategy1">
-        <Options def_top="panda_dirc_wasa"/>
+        <Options def_top="panda_dirc_wasa" top="padiwa_pulser"/>
         <Source name="../padiwa_pulser.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
+            <Options top_module="padiwa_pulser"/>
         </Source>
         <Source name="../lcd_config.vhd" type="VHDL" type_short="VHDL">
             <Options/>
@@ -33,7 +33,7 @@
         <Source name="../../../trbnet/trb_net_std.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="../../pinout/padiwa_amps.lpf" type="Logic Preference" type_short="LPF">
+        <Source name="../../pinout/panda_dirc_wasa1.lpf" type="Logic Preference" type_short="LPF">
             <Options/>
         </Source>
     </Implementation>

diff --git a/pulser/padiwa_pulser.vhd b/pulser/padiwa_pulser.vhd
index 4c4b8dd1768e94b6b2fe5fdf5097366f39db6cbf..5308020d50c45d603c61bf29155ffa2d5dfe7295 100644 (file)
--- a/pulser/padiwa_pulser.vhd
+++ b/pulser/padiwa_pulser.vhd
@@ -52,6 +52,10 @@ signal bus_read     : std_logic;
 signal bus_write    : std_logic;
 signal bus_ready    : std_logic;
 
+signal register_1   : std_logic_vector(31 downto 0);
+signal register_2   : std_logic_vector(15 downto 0);
+
+
 begin
 
 ---------------------------------------------------------------------------
@@ -96,17 +100,36 @@ THE_UART : entity work.uart_sctrl
     );
 
 
-PROC_REGISTERS : process begin
+    
+---------------------------------------------------------------------------
+-- Registers
+---------------------------------------------------------------------------    
+PROC_WRITE_REGISTERS : process begin
   wait until rising_edge(clk_osc);
   if bus_write= '1' then
     if uart_addr = x"01" then
-      lcd_data_i(31 downto 0) <= uart_rx_data;
+      register_1 <= uart_rx_data;
+    elsif uart_addr = x"02" then
+      register_2 <= uart_rx_data(15 downto 0);
+    end if;
+  end if;
+end process;
+    
+
+PROC_READ_REGISTERS : process begin
+  wait until rising_edge(clk_osc);
+  bus_ready <= '0';
+  if bus_read = '1' then
+    bus_ready <= '1';
+    if uart_addr = x"01" then
+      uart_tx_data <= register_1;
     elsif uart_addr = x"02" then
-      lcd_data_i(79 downto 64) <= uart_rx_data(15 downto 0);
+      uart_tx_data <= x"0000" & register_2;
     end if;
   end if;
 end process;
 
+
 ---------------------------------------------------------------------------
 -- LCD
 ---------------------------------------------------------------------------    
@@ -127,7 +150,13 @@ THE_LCD : entity work.lcd
     );    
 
 
-    
+
+lcd_data_i(31 downto 0)    <= register_1;
+lcd_data_i(63 downto 32)   <= (others => '0');
+lcd_data_i(79 downto 64)   <= register_2;
+lcd_data_i(87 downto 80)   <= uart_addr;
+lcd_data_i(127 downto 96)  <= uart_rx_data(31 downto 0);
+lcd_data_i(255 downto 128) <= (others => '0');    
 
     
 

diff --git a/pulser/padiwa_pulser_constraints.lpf b/pulser/padiwa_pulser_constraints.lpf
new file mode 100644 (file)
index 0000000..e699a3f
--- /dev/null
+++ b/pulser/padiwa_pulser_constraints.lpf
@@ -0,0 +1,2 @@
+FREQUENCY NET clk_i_c  133 MHz;
+

diff --git a/source/lcd.vhd b/source/lcd.vhd
index 71f2c39f03c4d590b76f8a9d0c75eff535f95370..2ddd34887e327b11d5d01bc26aeeec514acf3a3b 100644 (file)
--- a/source/lcd.vhd
+++ b/source/lcd.vhd
@@ -154,6 +154,11 @@ constant fontram : fontram_t := (
     x"80", x"01", x"00", x"00", x"00", x"03", x"80", x"03", x"80", x"01", x"80", x"01", x"80", x"03", x"80", x"03", \r
     x"00", x"03", x"00", x"03", x"80", x"03", x"80", x"01", others => x"00");\r
 \r
+  attribute syn_romstyle : string;\r
+  attribute syn_romstyle of fontram : constant is "block_rom";\r
+   \r
+    \r
+    \r
   type initdc_t   is array (0 to 15) of std_logic;\r
   constant initdc   : initdc_t   := ('0','1','0','1','0','0','1','1','1','1','0','1','1','1','1','0');\r
 \r

diff --git a/source/uart_sctrl.vhd b/source/uart_sctrl.vhd
index 380b7586b65ce8efdcf8cba4b6914ef03f66a7d2..d4ef19b48fa73f0ebcf5d69d0f599d6105592712 100644 (file)
--- a/source/uart_sctrl.vhd
+++ b/source/uart_sctrl.vhd
@@ -39,7 +39,7 @@ signal rx_ready  : std_logic;
 signal tx_send   : std_logic;
 signal tx_ready  : std_logic;
 
-type   rx_state_t is (IDLE,GET_ADDR,GET_BYTE0,GET_BYTE1,GET_BYTE2,GET_BYTE3,DO_WRITE,DO_READ,SEND_BYTE0,SEND_BYTE1,SEND_BYTE2);
+type   rx_state_t is (IDLE,GET_ADDR,GET_BYTE0,GET_BYTE1,GET_BYTE2,GET_BYTE3,DO_WRITE,DO_READ,SEND_BYTE0,SEND_BYTE1,SEND_BYTE2,SEND_BYTE3,SEND_TERM);
 signal state     : rx_state_t;
 signal addr      : std_logic_vector(7 downto 0) := (others => '0');
 signal word      : std_logic_vector(31 downto 0) := (others => '0');
@@ -77,10 +77,12 @@ PROC_RX : process begin
   READ_OUT  <= '0';
   WRITE_OUT <= '0';
   tx_send   <= '0';
+  timer     <= timer + 1;
   case state is
     when IDLE =>
       cmd_rd <= '0';
       cmd_wr <= '0';
+      timer  <= (others => '0');
       if rx_ready = '1' then
         state <= GET_ADDR;
         if rx_data = x"52" then
@@ -131,7 +133,13 @@ PROC_RX : process begin
       if READY_IN = '1' then
         word <= DATA_IN;
         tx_send <= '1';
-        tx_data <= DATA_IN(31 downto 24);
+        tx_data <= x"52";
+        state   <= SEND_BYTE3;
+      end if;
+    when SEND_BYTE3=>
+      if tx_ready = '1' then
+        tx_send <= '1';
+        tx_data <= word(31 downto 24);
         state   <= SEND_BYTE2;
       end if;
     when SEND_BYTE2=>
@@ -150,9 +158,15 @@ PROC_RX : process begin
       if tx_ready = '1' then
         tx_send <= '1';
         tx_data <= word(7 downto 0);
+        state   <= SEND_TERM;
+      end if;
+    when SEND_TERM=>
+      if tx_ready = '1' then
+        tx_send <= '1';
+        tx_data <= x"0a";
         state   <= IDLE;
       end if;
-  
+    
   end case;
 
   if RESET = '1' or timeout = '1' then

diff --git a/source/uart_trans.vhd b/source/uart_trans.vhd
index 8b5afbb104fdf44f4f3913984674f91a60dcb2d8..c062f8160115bd2b41227e2c59e81d36dd156bf3 100644 (file)
--- a/source/uart_trans.vhd
+++ b/source/uart_trans.vhd
@@ -68,9 +68,10 @@ DEBUG(3) <= '0';
   sync_output : process begin
     wait until rising_edge(CLK);
     TX <= symbol;
-    READY <= ready_sig;
   end process;
   
+  READY <= ready_sig and not SEND;
+  
 ----------------------------
 -- Generate Serial Clock
 ----------------------------