--TDC settings
constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement
- constant NUM_TDC_CHANNELS : integer range 1 to 65 := 5; -- number of tdc channels per module
+ constant NUM_TDC_CHANNELS : integer range 1 to 65 := 33; -- number of tdc channels per module
constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 5; --the nearest power of two, for convenience reasons
- constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 3; --double edge type: 0, 1, 2, 3
+ constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 1; --double edge type: 0, 1, 2, 3
-- 0: single edge only,
-- 1: same channel,
-- 2: alternating channels,
------------------------------------------------------------------------------
type data_t is array (0 to 1023) of std_logic_vector(7 downto 0);
- constant LCD_DATA : data_t;
+ constant LCD_DATA : data_t := (others => (others => '0'));
------------------------------------------------------------------------------
--Select settings by configuration
nodelist_file => 'nodelist_frankfurt.txt',
par_options => '../../base/trb3_periph.p2t',
-
+pinout_file => 'trb3_periph_ada',
#Include only necessary lpf files
#pinout_file => '', #name of pin-out file, if not equal TOPNAME
firefox_open => 0,
twr_number_of_errors => 20,
+Familyname => 'LatticeECP3',
+Devicename => 'LFE3-150EA',
+Package => 'FPBGA672',
+Speedgrade => '8',
# LOCATE COMP "INN_46" SITE "AB26"; #"DQLR_17" DQLR1_5 #179
LOCATE COMP "INP_47" SITE "W21"; #"DQLR_18" DQSLR1_T #181
# LOCATE COMP "INN_47" SITE "W20"; #"DQLR_19" DQSLR1_C #183
-LOCATE COMP "OUT_H_SDO" SITE "AA24"; #"DQLR_20" DQLR1_6 #185
+LOCATE COMP "DAC_OUT_H_SDO" SITE "AA24"; #"DQLR_20" DQLR1_6 #185
# LOCATE COMP "OUT_H_SDOb" SITE "AA23"; #"DQLR_21" DQLR1_7 #187
-LOCATE COMP "IN_H_SDI" SITE "AD26"; #"DQLR_22" DQLR1_8 #189
+LOCATE COMP "DAC_IN_H_SDI" SITE "AD26"; #"DQLR_22" DQLR1_8 #189
# LOCATE COMP "IN_H_SDIbD" SITE "AD25"; #"DQLR_23" DQLR1_9 #191
LOCATE COMP "INP_60" SITE "R25"; #"DQLR_24" DQLR2_0 #170
# LOCATE COMP "INN_62" SITE "U26"; #"DQLR_29" DQLR2_5 #180
LOCATE COMP "INP_63" SITE "V21"; #"DQLR_30" DQSLR2_T #182
# LOCATE COMP "INN_63" SITE "V22"; #"DQLR_31" DQSLR2_C #184
-LOCATE COMP "OUT_H_SCK" SITE "U24"; #"DQLR_32" DQLR2_6 #186
+LOCATE COMP "DAC_OUT_H_SCK" SITE "U24"; #"DQLR_32" DQLR2_6 #186
# LOCATE COMP "OUT_H_SCKb" SITE "V24"; #"DQLR_33" DQLR2_7 #188
-LOCATE COMP "OUT_H_CS" SITE "U23"; #"DQLR_34" DQLR2_8 #190
+LOCATE COMP "DAC_OUT_H_CS" SITE "U23"; #"DQLR_34" DQLR2_8 #190
# LOCATE COMP "OUT_H_CSb" SITE "U22"; #"DQLR_35" DQLR2_9 #192
# LOCATE COMP "DQUL_0" SITE "B2"; #"DQUL_0" DQUL0_0 #74
# LOCATE COMP "DQUL_1" SITE "B3"; #"DQUL_1" DQUL0_1 #76
-LOCATE COMP "OUT_L_SDO" SITE "D4"; #"DQUL_2" DQUL0_2 #78
+LOCATE COMP "DAC_OUT_L_SDO" SITE "D4"; #"DQUL_2" DQUL0_2 #78
# LOCATE COMP "OUT_L_SDOb" SITE "E4"; #"DQUL_3" DQUL0_3 #80
-LOCATE COMP "OUT_L_SCK" SITE "C3"; #"DQUL_4" DQUL0_4 #82
+LOCATE COMP "DAC_OUT_L_SCK" SITE "C3"; #"DQUL_4" DQUL0_4 #82
# LOCATE COMP "OUT_L_SCKb" SITE "D3"; #"DQUL_5" DQUL0_5 #84
-LOCATE COMP "IN_L_SDI" SITE "G5"; #"DQUL_6" DQSUL0_T #86
+LOCATE COMP "DAC_IN_L_SDI" SITE "G5"; #"DQUL_6" DQSUL0_T #86
# LOCATE COMP "IN_L_SDIb" SITE "G6"; #"DQUL_7" DQSUL0_C #88
# LOCATE COMP "DQUL_8" SITE "E3"; #"DQUL_8" DQUL0_6 #90
# LOCATE COMP "DQUL_9" SITE "F4"; #"DQUL_9" DQUL0_7 #92
-LOCATE COMP "OUT_L_CS" SITE "H6"; #"DQUL_10" DQUL0_8 #94
+LOCATE COMP "DAC_OUT_L_CS" SITE "H6"; #"DQUL_10" DQUL0_8 #94
# LOCATE COMP "OUT_L_CSb" SITE "J6"; #"DQUL_11" DQUL0_9 #96
# LOCATE COMP "DQUL_12" SITE "G2"; #"DQUL_12" DQUL1_0 #73
DEFINE PORT GROUP "INP_group" "INP*" ;
IOBUF GROUP "INP_group" IO_TYPE=LVDS25 DIFFRESISTOR=100;
-#DEFINE PORT GROUP "IN_group" "IN_*" ;
-#IOBUF GROUP "IN_group" IO_TYPE=LVDS25 DIFFRESISTOR=100;
+DEFINE PORT GROUP "IN_group" "DAC_IN_*" ;
+IOBUF GROUP "IN_group" IO_TYPE=LVDS25 DIFFRESISTOR=100;
-DEFINE PORT GROUP "OUT_group" "OUT_*" ;
+DEFINE PORT GROUP "OUT_group" "DAC_OUT_*" ;
IOBUF GROUP "OUT_group" IO_TYPE=LVDS25;
#################################################################