individual serdes placement for each project

diff --git a/base/cbmtof.lpf b/base/cbmtof.lpf
index ce8f9c78e08a91ac44e0aea1be83219f680f4739..106afc9fe5ae2c5738df31ec6bf4d729d0caf4de 100644 (file)
--- a/base/cbmtof.lpf
+++ b/base/cbmtof.lpf
@@ -13,8 +13,13 @@ FREQUENCY PORT CLK_OSC 200 MHz;
 FREQUENCY PORT CLK_EXT 200 MHz;
 #FREQUENCY PORT CLK_CM_* 125 MHz;
 
-MULTICYCLE FROM CLKNET "clk_100_i_c" TO CLKNET "CLK_OSC_c" 2 X ;
-#MULTICYCLE FROM CLKNET "CLK_OSC_c" TO CLKNET "clk_100_i_c" 1 X ;
+#MULTICYCLE FROM CLKNET "clk_100_i_c" TO CLKNET "CLK_OSC_c" 2 X ;
+##MULTICYCLE FROM CLKNET "CLK_OSC_c" TO CLKNET "clk_100_i_c" 1 X ;
+
+MULTICYCLE FROM CLKNET "clk_100_i_c" TO CLKNET "CLK_EXT" 2 X ;
+#MULTICYCLE FROM CLKNET "CLK_EXT" TO CLKNET "clk_100_i_c" 1 X ;
+
+LOCATE COMP   "THE_MEDIA_UPLINK/gen_serdes_0_200_ctc.THE_SERDES/PCSD_INST" SITE "PCSA" ;
 
 #################################################################
 # Clock I/O

diff --git a/base/trb3_periph_32PinAddOn.lpf b/base/trb3_periph_32PinAddOn.lpf
index 9a94475c193d00107c382206cce30fd984c878cf..0432b4edd5e797f5d8230f9172099b6d3387d2fb 100644 (file)
--- a/base/trb3_periph_32PinAddOn.lpf
+++ b/base/trb3_periph_32PinAddOn.lpf
@@ -17,6 +17,8 @@ FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz;
 MULTICYCLE FROM CLKNET "clk_100_internal_c" TO CLKNET "CLK_PCLK_LEFT" 2 X ;
 MULTICYCLE FROM CLKNET "CLK_PCLK_LEFT" TO CLKNET "clk_100_internal_c" 2 X ;
 
+LOCATE COMP   "THE_MEDIA_UPLINK/gen_serdes_1_200_THE_SERDES/PCSD_INST" SITE "PCSA" ;
+
 #################################################################
 # Clock I/O
 #################################################################

diff --git a/base/trb3_periph_ADA.lpf b/base/trb3_periph_ADA.lpf
index caeaf6cd12ea5b9f87ba99b95c812bbd80218d1e..746468fb4fc124ca5df2c4babf24c42e26db1b3b 100644 (file)
--- a/base/trb3_periph_ADA.lpf
+++ b/base/trb3_periph_ADA.lpf
@@ -17,6 +17,8 @@ FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz;
 MULTICYCLE FROM CLKNET "clk_100_internal_c" TO CLKNET "CLK_PCLK_LEFT" 2 X ;
 MULTICYCLE FROM CLKNET "CLK_PCLK_LEFT" TO CLKNET "clk_100_internal_c" 2 X ;
 
+LOCATE COMP   "THE_MEDIA_UPLINK/gen_serdes_1_200_THE_SERDES/PCSD_INST" SITE "PCSA" ;
+
 #################################################################
 # Clock I/O
 #################################################################

diff --git a/base/trb3_periph_gpin.lpf b/base/trb3_periph_gpin.lpf
index 96e89d14525f4497c39a321535dd9be50f63fa3b..5dc1bebd8f62bc74dcb7fde8e962f2c62e92f55c 100644 (file)
--- a/base/trb3_periph_gpin.lpf
+++ b/base/trb3_periph_gpin.lpf
@@ -15,6 +15,8 @@ FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz;
 MULTICYCLE FROM CLKNET "clk_100_internal_c" TO CLKNET "CLK_PCLK_LEFT" 2 X ;
 MULTICYCLE FROM CLKNET "CLK_PCLK_LEFT" TO CLKNET "clk_100_internal_c" 2 X ;
 
+LOCATE COMP   "THE_MEDIA_UPLINK/gen_serdes_1_200_THE_SERDES/PCSD_INST" SITE "PCSA" ;
+
 #################################################################
 # Clock I/O
 #################################################################

diff --git a/base/trb3_periph_padiwa.lpf b/base/trb3_periph_padiwa.lpf
index d6144d405ee98350b82e39b23970e981088dcdc2..7979fabc78b3104e6db176efe0c4f474010ba1f1 100644 (file)
--- a/base/trb3_periph_padiwa.lpf
+++ b/base/trb3_periph_padiwa.lpf
@@ -15,6 +15,8 @@ FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz;
 MULTICYCLE FROM CLKNET "clk_100_internal_c" TO CLKNET "CLK_PCLK_LEFT" 2 X ;
 MULTICYCLE FROM CLKNET "CLK_PCLK_LEFT" TO CLKNET "clk_100_internal_c" 2 X ;
 
+LOCATE COMP   "THE_MEDIA_UPLINK/gen_serdes_1_200_THE_SERDES/PCSD_INST" SITE "PCSA" ;
+
 #################################################################
 # Clock I/O
 #################################################################