FREQUENCY PORT CLK_EXT 200 MHz;
#FREQUENCY PORT CLK_CM_* 125 MHz;
-MULTICYCLE FROM CLKNET "clk_100_i_c" TO CLKNET "CLK_OSC_c" 2 X ;
-#MULTICYCLE FROM CLKNET "CLK_OSC_c" TO CLKNET "clk_100_i_c" 1 X ;
+#MULTICYCLE FROM CLKNET "clk_100_i_c" TO CLKNET "CLK_OSC_c" 2 X ;
+##MULTICYCLE FROM CLKNET "CLK_OSC_c" TO CLKNET "clk_100_i_c" 1 X ;
+
+MULTICYCLE FROM CLKNET "clk_100_i_c" TO CLKNET "CLK_EXT" 2 X ;
+#MULTICYCLE FROM CLKNET "CLK_EXT" TO CLKNET "clk_100_i_c" 1 X ;
+
+LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_0_200_ctc.THE_SERDES/PCSD_INST" SITE "PCSA" ;
#################################################################
# Clock I/O
MULTICYCLE FROM CLKNET "clk_100_internal_c" TO CLKNET "CLK_PCLK_LEFT" 2 X ;
MULTICYCLE FROM CLKNET "CLK_PCLK_LEFT" TO CLKNET "clk_100_internal_c" 2 X ;
+LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200_THE_SERDES/PCSD_INST" SITE "PCSA" ;
+
#################################################################
# Clock I/O
#################################################################
MULTICYCLE FROM CLKNET "clk_100_internal_c" TO CLKNET "CLK_PCLK_LEFT" 2 X ;
MULTICYCLE FROM CLKNET "CLK_PCLK_LEFT" TO CLKNET "clk_100_internal_c" 2 X ;
+LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200_THE_SERDES/PCSD_INST" SITE "PCSA" ;
+
#################################################################
# Clock I/O
#################################################################
MULTICYCLE FROM CLKNET "clk_100_internal_c" TO CLKNET "CLK_PCLK_LEFT" 2 X ;
MULTICYCLE FROM CLKNET "CLK_PCLK_LEFT" TO CLKNET "clk_100_internal_c" 2 X ;
+LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200_THE_SERDES/PCSD_INST" SITE "PCSA" ;
+
#################################################################
# Clock I/O
#################################################################
MULTICYCLE FROM CLKNET "clk_100_internal_c" TO CLKNET "CLK_PCLK_LEFT" 2 X ;
MULTICYCLE FROM CLKNET "CLK_PCLK_LEFT" TO CLKNET "clk_100_internal_c" 2 X ;
+LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200_THE_SERDES/PCSD_INST" SITE "PCSA" ;
+
#################################################################
# Clock I/O
#################################################################