signal pll_adc_sample_clk_dphase_r : unsigned(3 downto 0);
signal pll_adc_sample_clk_finedelb_r : unsigned(3 downto 0);
signal nx_timestamp_delay_r : unsigned(2 downto 0);
+ signal nx_frame_word_delay_rr : unsigned(1 downto 0);
signal nx_frame_word_delay_r : unsigned(1 downto 0);
signal fifo_full_rr : std_logic;
signal fifo_full_r : std_logic;
attribute syn_keep of adc_debug_type_f : signal is true;
attribute syn_keep of adc_debug_type : signal is true;
-
+
+ attribute syn_keep of nx_frame_word_delay_rr : signal is true;
+ attribute syn_keep of nx_frame_word_delay_r : signal is true;
+
attribute syn_preserve : boolean;
attribute syn_preserve of reset_nx_timestamp_clk_in_ff : signal is true;
attribute syn_preserve of reset_nx_timestamp_clk_in_f : signal is true;
attribute syn_preserve of adc_debug_type_f : signal is true;
attribute syn_preserve of adc_debug_type : signal is true;
+
+ attribute syn_preserve of nx_frame_word_delay_rr : signal is true;
+ attribute syn_preserve of nx_frame_word_delay_r : signal is true;
begin
if (rising_edge(NX_TIMESTAMP_CLK_IN) ) then
nx_frame_word_delay <= nx_frame_word_delay_f;
adc_data_clk_last(0) <= adc_data_s_clk;
- -- Register Info
- nx_frame_word_delay_r <= nx_frame_word_delay;
if (RESET_NX_TIMESTAMP_CLK_IN = '1') then
nx_frame_word_delay_f <= "10";
debug_state <= x"5";
when R_RESET_TIMESTAMP =>
- -- must reset/resync Timestamp clock and data trnasmission clock
+ -- must reset/resync Timestamp clock and data transmission clock
-- of nxyter first, afterwards wait a bit to let settle down
reset_handler_counter <= reset_handler_counter + 1;
nx_timestamp_reset_o <= '1';
end process PROC_SLAVE_BUS_BUFFER;
-- Give status info to the TRB Slow Control Channel
+
+ -- Register Info
+ nx_frame_word_delay_rr <= nx_frame_word_delay_f when rising_edge(CLK_IN);
+ nx_frame_word_delay_r <= nx_frame_word_delay_rr when rising_edge(CLK_IN);
+
PROC_SLAVE_BUS: process(CLK_IN)
begin
if (rising_edge(CLK_IN) ) then
end entity;
architecture Behavioral of nx_fpga_timestamp is
+ type S_STATES is (S_IDLE,
+ S_RESET,
+ S_RESET_WAIT,
+ S_HOLD
+ );
+ signal S_STATE : S_STATES;
+
+ signal wait_timer_start : std_logic;
+ signal wait_timer_done : std_logic;
signal timestamp_reset_ff : std_logic;
signal timestamp_reset_f : std_logic;
signal timestamp_hold_o : std_logic_vector(11 downto 0);
signal timestamp_trigger_o : std_logic;
- signal timestamp_sync_o : std_logic;
+ signal timestamp_reset_o : std_logic;
-- Reset
signal reset_nx_main_clk_in_ff : std_logic;
attribute syn_keep of reset_nx_main_clk_in_ff : signal is true;
attribute syn_keep of reset_nx_main_clk_in_f : signal is true;
+ attribute syn_keep of timestamp_reset_ff : signal is true;
+ attribute syn_keep of timestamp_reset_f : signal is true;
+
attribute syn_preserve : boolean;
attribute syn_preserve of reset_nx_main_clk_in_ff : signal is true;
attribute syn_preserve of reset_nx_main_clk_in_f : signal is true;
+
+ attribute syn_preserve of timestamp_reset_ff : signal is true;
+ attribute syn_preserve of timestamp_reset_f : signal is true;
begin
DEBUG_OUT(0) <= NX_MAIN_CLK_IN;
- DEBUG_OUT(1) <= TIMESTAMP_RESET_IN;
- DEBUG_OUT(2) <= timestamp_reset;
- DEBUG_OUT(3) <= TIMESTAMP_RESET_OUT;
+ DEBUG_OUT(1) <= '0';
+ DEBUG_OUT(2) <= TIMESTAMP_RESET_IN;
+ DEBUG_OUT(3) <= '0';
DEBUG_OUT(4) <= TRIGGER_IN;
- DEBUG_OUT(15 downto 5) <= timestamp_hold_o(10 downto 0);
+ DEBUG_OUT(5) <= '0';
+ DEBUG_OUT(6) <= timestamp_reset_ff;
+ DEBUG_OUT(7) <= '0';
+ DEBUG_OUT(8) <= timestamp_reset_f;
+ DEBUG_OUT(9) <= '0';
+ DEBUG_OUT(10) <= timestamp_reset;
+ DEBUG_OUT(11) <= '0';
+ DEBUG_OUT(12) <= timestamp_reset_o;
+ DEBUG_OUT(13) <= '0';
+ DEBUG_OUT(14) <= timestamp_trigger_o;
+
+ DEBUG_OUT(15) <= '0';
+ --timestamp_hold_o(10 downto 0);
-----------------------------------------------------------------------------
-- Reset Domain Transfer
timestamp_reset <= timestamp_reset_f
when rising_edge(NX_MAIN_CLK_IN);
+ -- Timer
+ timer_static_TS_RESET: timer_static
+ generic map (
+ CTR_WIDTH => 3,
+ CTR_END => 7
+ )
+ port map (
+ CLK_IN => NX_MAIN_CLK_IN,
+ RESET_IN => RESET_NX_MAIN_CLK_IN,
+ TIMER_START_IN => wait_timer_start,
+ TIMER_DONE_OUT => wait_timer_done
+ );
+
PROC_TIMESTAMP_CTR: process (NX_MAIN_CLK_IN)
begin
if (rising_edge(NX_MAIN_CLK_IN)) then
if (RESET_NX_MAIN_CLK_IN = '1') then
+ wait_timer_start <= '0';
timestamp_ctr <= (others => '0');
timestamp_hold_o <= (others => '0');
- timestamp_sync_o <= '0';
+ timestamp_reset_o <= '0';
+ S_STATE <= S_RESET;
else
- timestamp_trigger_o <= '1';
- timestamp_sync_o <= '0';
+ wait_timer_start <= '0';
+ timestamp_trigger_o <= '0';
+ timestamp_reset_o <= '0';
+
+ case S_STATE is
+
+ when S_IDLE =>
+ timestamp_ctr <= timestamp_ctr + 1;
+ if (timestamp_reset = '0' and timestamp_reset_f = '1') then
+ S_STATE <= S_RESET;
+ elsif (TRIGGER_IN = '1') then
+ S_STATE <= S_HOLD;
+ else
+ S_STATE <= S_IDLE;
+ end if;
+
+ when S_RESET =>
+ timestamp_reset_o <= '1';
+ wait_timer_start <= '1';
+ S_STATE <= S_RESET_WAIT;
+
+ when S_RESET_WAIT =>
+ if (wait_timer_done = '0') then
+ timestamp_reset_o <= '1';
+ S_STATE <= S_RESET_WAIT;
+ else
+ timestamp_ctr <= (others => '0');
+ S_STATE <= S_IDLE;
+ end if;
+
+ when S_HOLD =>
+ timestamp_ctr <= timestamp_ctr + 1;
+ timestamp_hold_o <= timestamp_ctr;
+ timestamp_trigger_o <= '1';
+ S_STATE <= S_IDLE;
+
+ end case;
- if ((timestamp_reset = '0' and timestamp_reset_f = '1')) then
- timestamp_ctr <= (others => '0');
- timestamp_sync_o <= '1';
- else
- if (TRIGGER_IN = '1') then
- timestamp_hold_o <= std_logic_vector(timestamp_ctr);
- timestamp_trigger_o <= '1';
- end if;
- -- Increase TS Counter
- timestamp_ctr <= timestamp_ctr + 1;
- end if;
end if;
end if;
end process PROC_TIMESTAMP_CTR;
-- Output Signals
-----------------------------------------------------------------------------
- TIMESTAMP_RESET_OUT <= timestamp_sync_o;
+ TIMESTAMP_RESET_OUT <= timestamp_reset_o;
TIMESTAMP_HOLD_OUT <= timestamp_hold_o;
TIMESTAMP_TRIGGER_OUT <= timestamp_trigger_o;
signal channel_data_valid_o_f : std_logic_vector(2 downto 0);
signal channel_read_busy_o : std_logic;
+ signal debug_state_x : std_logic_vector(2 downto 0);
+ signal debug_state : std_logic_vector(2 downto 0);
+
begin
-----------------------------------------------------------------------------
DEBUG_OUT(6) <= read_enable;
DEBUG_OUT(7) <= channel_data_valid_o;
DEBUG_OUT(8) <= RESET_IN;
- DEBUG_OUT(15 downto 9) <= channel_data_o(6 downto 0);
+ DEBUG_OUT(11 downto 9) <= debug_state;
+ DEBUG_OUT(15 downto 12) <= channel_data_o(3 downto 0);
-----------------------------------------------------------------------------
data_hist_m <= (others => '0');
erase_counter <= (others => '0');
H_STATE <= H_ERASE;
+ debug_state <= (others => '0');
else
address_hist_m <= address_hist_m_x;
data_hist_m <= data_hist_m_x;
erase_counter <= erase_counter_x;
H_STATE <= H_NEXT_STATE;
+ debug_state <= debug_state_x;
end if;
end if;
end process PROC_HIST_HANDLER_TRANSFER;
erase_counter_x <= erase_counter;
case H_STATE is
+
when H_IDLE =>
write_address_hist <= (others => '0');
write_data_hist <= (others => '0');
data_hist_m_x <= (others => '0');
H_NEXT_STATE <= H_IDLE;
end if;
+ debug_state_x <= "001";
when H_WRITEADD_CHANNEL =>
if (AVERAGE_ENABLE_IN = '0') then
write_enable_hist <= '1';
channel_write_busy_o <= '1';
H_NEXT_STATE <= H_IDLE;
+ debug_state_x <= "010";
when H_WRITE_CHANNEL =>
new_data := unsigned(data_hist_m);
write_enable <= '1';
channel_write_busy_o <= '1';
H_NEXT_STATE <= H_IDLE;
+ debug_state_x <= "011";
when H_ERASE =>
write_address_hist <= (others => '0');
data_hist_m_x <= (others => '0');
channel_write_busy_o <= '1';
H_NEXT_STATE <= H_ERASE_CHANNEL;
+ debug_state_x <= "100";
when H_ERASE_CHANNEL =>
new_data := unsigned(data_hist_m);
else
H_NEXT_STATE <= H_IDLE;
end if;
-
+ debug_state_x <= "101";
+
end case;
end process PROC_HIST_HANDLER;
CHANNEL_FILL_IN : in std_logic;
CHANNEL_ID_IN : in std_logic_vector(6 downto 0);
CHANNEL_ADC_IN : in std_logic_vector(11 downto 0);
+ CHANNEL_TS_IN : in std_logic_vector(6 downto 0);
CHANNEL_PILEUP_IN : in std_logic;
CHANNEL_OVERFLOW_IN : in std_logic;
signal adc_read : std_logic;
signal adc_read_data : std_logic_vector(31 downto 0);
signal adc_read_data_valid : std_logic;
+
+ -- Timestamp Histogram
+ signal ts_num_averages : unsigned(2 downto 0);
+ signal ts_average_enable : std_logic;
+ signal ts_write_busy : std_logic;
+ signal ts_read_busy : std_logic;
+
+ signal ts_write_id : std_logic_vector(6 downto 0);
+ signal ts_write_data : std_logic_vector(31 downto 0);
+ signal ts_write : std_logic;
+ signal ts_add : std_logic;
+ signal ts_read_id : std_logic_vector(6 downto 0);
+ signal ts_read : std_logic;
+ signal ts_read_data : std_logic_vector(31 downto 0);
+ signal ts_read_data_valid : std_logic;
+
-- Reset Hists
signal RESET_HISTS : std_logic;
DEBUG_OUT => open
);
-
+
+ nx_histogram_ts: nx_histogram
+ port map (
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_HISTS,
+
+ NUM_AVERAGES_IN => ts_num_averages,
+ AVERAGE_ENABLE_IN => ts_average_enable,
+ CHANNEL_ID_IN => ts_write_id,
+ CHANNEL_DATA_IN => ts_write_data,
+ CHANNEL_ADD_IN => ts_add,
+ CHANNEL_WRITE_IN => ts_write,
+ CHANNEL_WRITE_BUSY_OUT => ts_write_busy,
+
+ CHANNEL_ID_READ_IN => ts_read_id,
+ CHANNEL_READ_IN => ts_read,
+ CHANNEL_DATA_OUT => ts_read_data,
+ CHANNEL_DATA_VALID_OUT => ts_read_data_valid,
+ CHANNEL_READ_BUSY_OUT => ts_read_busy,
+
+ DEBUG_OUT => open
+ );
+
-----------------------------------------------------------------------------
-- Fill Histograms
-----------------------------------------------------------------------------
ovfl_write_data <= (others => '0');
ovfl_write <= '0';
ovfl_add <= '0';
+
+ ts_write_id <= (others => '0');
+ ts_write_data <= (others => '0');
+ ts_write <= '0';
+ ts_add <= '0';
else
hit_write_id <= (others => '0');
hit_write_data <= (others => '0');
ovfl_write_data <= (others => '0');
ovfl_write <= '0';
ovfl_add <= '0';
+
+ ts_write_id <= (others => '0');
+ ts_write_data <= (others => '0');
+ ts_write <= '0';
+ ts_add <= '0';
if (CHANNEL_FILL_IN = '1' and hit_write_busy = '0') then
hit_write_id <= CHANNEL_ID_IN;
adc_write_data(11 downto 0) <= CHANNEL_ADC_IN;
adc_write_data(31 downto 12) <= (others => '0');
adc_add <= '1';
-
+
if (CHANNEL_PILEUP_IN = '1') then
pileup_write_id <= CHANNEL_ID_IN;
pileup_write_data <= x"0000_0001";
ovfl_add <= '1';
end if;
+ if (unsigned(CHANNEL_TS_IN) > 0) then
+ ts_write_id <= CHANNEL_TS_IN;
+ ts_write_data <= x"0000_0001";
+ ts_add <= '1';
+ end if;
+
end if;
end if;
end if;
ovfl_read <= '0';
ovfl_num_averages <= "000";
ovfl_average_enable <= '0';
+
+ ts_read_id <= (others => '0');
+ ts_read <= '0';
+ ts_num_averages <= "000";
+ ts_average_enable <= '0';
else
slv_data_out_o <= (others => '0');
slv_unknown_addr_o <= '0';
hit_read_id <= (others => '0');
hit_read <= '0';
+
adc_read_id <= (others => '0');
adc_read <= '0';
+
pileup_read_id <= (others => '0');
pileup_read <= '0';
+
ovfl_read_id <= (others => '0');
ovfl_read <= '0';
+
+ ts_read_id <= (others => '0');
+ ts_read <= '0';
if (hit_read_busy = '1' or
adc_read_busy = '1' or
pileup_read_busy = '1' or
- ovfl_read_busy = '1' ) then
+ ovfl_read_busy = '1' or
+ ts_read_busy = '1') then
if (hit_read_data_valid = '1') then
slv_data_out_o <= hit_read_data;
slv_ack_o <= '1';
elsif (ovfl_read_data_valid = '1') then
slv_data_out_o <= ovfl_read_data;
slv_ack_o <= '1';
+ elsif (ts_read_data_valid = '1') then
+ slv_data_out_o <= ts_read_data;
+ slv_ack_o <= '1';
else
slv_ack_o <= '0';
end if;
adc_read_id <= SLV_ADDR_IN(6 downto 0);
adc_read <= '1';
slv_ack_o <= '0';
+ elsif (unsigned(SLV_ADDR_IN) >= x"0400" and
+ unsigned(SLV_ADDR_IN) <= x"047f") then
+ ts_read_id <= SLV_ADDR_IN(6 downto 0);
+ ts_read <= '1';
+ slv_ack_o <= '0';
else
case SLV_ADDR_IN is
when x"0080" =>
slv_data_out_o(0) <= adc_average_enable;
slv_data_out_o(31 downto 1) <= (others => '0');
slv_ack_o <= '1';
-
+
+ when x"0481" =>
+ slv_data_out_o(0) <= ts_average_enable;
+ slv_data_out_o(31 downto 1) <= (others => '0');
+ slv_ack_o <= '1';
+
when others =>
slv_unknown_addr_o <= '1';
slv_ack_o <= '0';
slv_ack_o <= '1';
when x"0281" =>
- ovfl_average_enable <= SLV_DATA_IN(0);
+ ovfl_average_enable <= SLV_DATA_IN(0);
slv_ack_o <= '1';
when x"0380" =>
adc_average_enable <= SLV_DATA_IN(0);
slv_ack_o <= '1';
+ when x"0481" =>
+ ts_average_enable <= SLV_DATA_IN(0);
+ slv_ack_o <= '1';
+
when others =>
slv_unknown_addr_o <= '1';
slv_ack_o <= '0';
signal fee_data_finished_o : std_logic;
signal fee_trg_release_o : std_logic;
signal fee_trg_statusbits_o : std_logic_vector(31 downto 0);
- signal send_testpulse : std_logic;
+ signal testpulse_trigger : std_logic;
signal testpulse_enable : std_logic;
);
signal T_STATE : T_STATES;
-
+
+ signal start_testpulse : std_logic;
signal testpulse_delay : unsigned(11 downto 0);
signal testpulse_length : unsigned(11 downto 0);
signal testpulse_o : std_logic;
signal wait_timer_start : std_logic;
signal wait_timer_done : std_logic;
signal wait_timer_end : unsigned(11 downto 0);
-
+ signal internal_trigger_f : std_logic;
+ signal internal_trigger : std_logic;
+
-- Rate Calculation
- signal send_testpulse_ff : std_logic;
- signal send_testpulse_f : std_logic;
+ signal start_testpulse_ff : std_logic;
+ signal start_testpulse_f : std_logic;
signal accepted_trigger_rate_t : unsigned(27 downto 0);
- signal testpulse_o_clk100 : std_logic;
+ signal start_testpulse_clk100 : std_logic;
signal testpulse_rate_t : unsigned(27 downto 0);
signal rate_timer : unsigned(27 downto 0);
attribute syn_keep of fast_clear_ff : signal is true;
attribute syn_keep of fast_clear_f : signal is true;
+
+ attribute syn_keep of internal_trigger_f : signal is true;
+ attribute syn_keep of internal_trigger : signal is true;
+
+ attribute syn_keep of start_testpulse_ff : signal is true;
+ attribute syn_keep of start_testpulse_f : signal is true;
attribute syn_preserve : boolean;
attribute syn_preserve of reset_nx_main_clk_in_ff : signal is true;
attribute syn_preserve of fast_clear_ff : signal is true;
attribute syn_preserve of fast_clear_f : signal is true;
+ attribute syn_preserve of internal_trigger_f : signal is true;
+ attribute syn_preserve of internal_trigger : signal is true;
+
+ attribute syn_preserve of start_testpulse_ff : signal is true;
+ attribute syn_preserve of start_testpulse_f : signal is true;
+
begin
-- Debug Line
DEBUG_OUT(11) <= fee_trg_release_o;
DEBUG_OUT(12) <= trigger_busy_o;
DEBUG_OUT(13) <= timestamp_trigger_o;
- DEBUG_OUT(14) <= send_testpulse;
+ DEBUG_OUT(14) <= testpulse_trigger;
DEBUG_OUT(15) <= testpulse_o;
-----------------------------------------------------------------------------
invalid_timing_trigger_n <= '1';
ts_wait_timer_start <= '0';
ts_wait_timer_reset <= '1';
- send_testpulse <= '0';
+ testpulse_trigger <= '0';
timestamp_trigger_o <= '0';
TS_STATE <= TS_IDLE;
else
invalid_timing_trigger_n <= '0';
ts_wait_timer_start <= '0';
ts_wait_timer_reset <= '0';
- send_testpulse <= '0';
+ testpulse_trigger <= '0';
timestamp_trigger_o <= '0';
if (fast_clear = '1') then
TS_STATE <= TS_INVALID_TRIGGER;
else
if (reg_testpulse_enable = '1') then
- send_testpulse <= '1';
+ testpulse_trigger <= '1';
end if;
timestamp_trigger_o <= '1';
ts_wait_timer_start <= '1';
TIMER_DONE_OUT => wait_timer_done
);
- testpulse_delay <= reg_testpulse_delay when rising_edge(NX_MAIN_CLK_IN);
- testpulse_length <= reg_testpulse_length when rising_edge(NX_MAIN_CLK_IN);
+ testpulse_delay <= reg_testpulse_delay when rising_edge(NX_MAIN_CLK_IN);
+ testpulse_length <= reg_testpulse_length when rising_edge(NX_MAIN_CLK_IN);
+
+ internal_trigger_f <= INTERNAL_TRIGGER_IN when rising_edge(NX_MAIN_CLK_IN);
+ internal_trigger <= internal_trigger_f when rising_edge(NX_MAIN_CLK_IN);
+ start_testpulse <= testpulse_trigger or internal_trigger;
+
PROC_TESTPULSE_HANDLER: process (NX_MAIN_CLK_IN)
begin
if( rising_edge(NX_MAIN_CLK_IN) ) then
case T_STATE is
when T_IDLE =>
- if (send_testpulse = '1') then
+ if (start_testpulse = '1') then
if (reg_testpulse_delay > 0) then
wait_timer_end <= testpulse_delay;
wait_timer_start <= '1';
end process PROC_TESTPULSE_HANDLER;
-- Relax Timing
- send_testpulse_ff <= send_testpulse when rising_edge(NX_MAIN_CLK_IN);
- send_testpulse_f <= send_testpulse_ff when rising_edge(NX_MAIN_CLK_IN);
+ start_testpulse_ff <= start_testpulse when rising_edge(NX_MAIN_CLK_IN);
+ start_testpulse_f <= start_testpulse_ff when rising_edge(NX_MAIN_CLK_IN);
+
pulse_dtrans_TESTPULSE_RATE: pulse_dtrans
generic map (
- CLK_RATIO => 2
+ CLK_RATIO => 4
)
port map (
CLK_A_IN => NX_MAIN_CLK_IN,
RESET_A_IN => RESET_NX_MAIN_CLK_IN,
- PULSE_A_IN => send_testpulse_f,
+ PULSE_A_IN => start_testpulse_f,
CLK_B_IN => CLK_IN,
RESET_B_IN => RESET_IN,
- PULSE_B_OUT => testpulse_o_clk100
+ PULSE_B_OUT => start_testpulse_clk100
);
PROC_CAL_RATES: process (CLK_IN)
accepted_trigger_rate_t <= accepted_trigger_rate_t + 1;
end if;
- if (testpulse_o_clk100 = '1') then
+ if (start_testpulse_clk100 = '1') then
testpulse_rate_t <= testpulse_rate_t + 1;
end if;
rate_timer <= rate_timer + 1;
FEE_TRG_RELEASE_OUT <= fee_trg_release_o;
FEE_TRG_STATUSBITS_OUT <= fee_trg_statusbits_o;
- NX_TESTPULSE_OUT <= testpulse_o or INTERNAL_TRIGGER_IN;
+ NX_TESTPULSE_OUT <= testpulse_o;
-- Slave Bus
SLV_DATA_OUT <= slv_data_out_o;
HISTOGRAM_FILL_OUT : out std_logic;
HISTOGRAM_BIN_OUT : out std_logic_vector(6 downto 0);
HISTOGRAM_ADC_OUT : out std_logic_vector(11 downto 0);
+ HISTOGRAM_TS_OUT : out std_logic_vector(6 downto 0);
HISTOGRAM_PILEUP_OUT : out std_logic;
HISTOGRAM_OVERFLOW_OUT : out std_logic;
signal window_hit_ctr_r : unsigned(15 downto 0);
signal out_of_window_h_ctr_r : unsigned(15 downto 0);
signal validation_busy : std_logic_vector(1 downto 0);
- signal histogram_trigger_filter : std_logic;
-- Rate Calculations
signal data_rate_ctr_nr : unsigned(31 downto 0);
signal out_of_window_error_ctr : unsigned(15 downto 0);
signal readout_mode : std_logic_vector(3 downto 0);
- signal timestamp_fpga_i : unsigned(11 downto 0);
+ signal timestamp_fpga_ff : unsigned(11 downto 0);
+ signal timestamp_fpga_f : unsigned(11 downto 0);
signal timestamp_fpga : unsigned(11 downto 0);
signal timestamp_ref : unsigned(11 downto 0);
signal busy_time_ctr_last : unsigned(11 downto 0);
signal wait_timer_done_ns : std_logic;
-- Histogram
-
- signal histogram_trigger_all : std_logic;
signal histogram_fill_o : std_logic;
signal histogram_bin_o : std_logic_vector(6 downto 0);
signal histogram_adc_o : std_logic_vector(11 downto 0);
+ signal histogram_ts_o : std_logic_vector(6 downto 0);
signal histogram_pileup_o : std_logic;
signal histogram_ovfl_o : std_logic;
signal slv_unknown_addr_o : std_logic;
signal slv_ack_o : std_logic;
- signal readout_mode_r : std_logic_vector(3 downto 0);
- signal histogram_trigger_filter_r : std_logic;
+ signal readout_mode_r : std_logic_vector(3 downto 0);
+
signal out_of_window_error_ctr_clear : std_logic;
+ signal histogram_trig_filter : std_logic;
signal histogram_limits : std_logic;
signal histogram_lower_limit : unsigned(13 downto 0);
signal histogram_upper_limit : unsigned(13 downto 0);
- signal reset_hists_r : std_logic;
+ signal reset_hists : std_logic;
signal reset_hists_o : std_logic;
-- Timestamp Trigger Window Settings
signal state_d : std_logic_vector(1 downto 0);
+ attribute syn_keep : boolean;
+ attribute syn_keep of timestamp_fpga_ff : signal is true;
+ attribute syn_keep of timestamp_fpga_f : signal is true;
+
+ attribute syn_preserve : boolean;
+ attribute syn_preserve of timestamp_fpga_ff : signal is true;
+ attribute syn_preserve of timestamp_fpga_f : signal is true;
+
begin
-- Debug Line
DEBUG_OUT(8) <= channel_all_done;
DEBUG_OUT(9) <= store_to_fifo;
DEBUG_OUT(10) <= data_clk_o;
- DEBUG_OUT(11) <= out_of_window_error or EVT_BUFFER_FULL_IN;
+ DEBUG_OUT(11) <= out_of_window_error; -- or EVT_BUFFER_FULL_IN;
DEBUG_OUT(12) <= TIMESTAMP_STATUS_IN(S_PARITY);
DEBUG_OUT(13) <= min_val_time_expired;
DEBUG_OUT(14) <= token_update;
DEBUG_OUT(15) <= nomore_data_o;
-
+
-- Timer
timer_1: timer
generic map(
out_of_window_error <= '0';
fifo_delay_time <= (others => '0');
out_of_window_error_ctr <= (others => '0');
- histogram_trigger_filter <= '0';
+
+ histogram_fill_o <= '0';
+ histogram_bin_o <= (others => '0');
+ histogram_adc_o <= (others => '0');
+ histogram_ts_o <= (others => '0');
+ histogram_pileup_o <= '0';
+ histogram_ovfl_o <= '0';
else
d_data_o <= (others => '0');
d_data_clk_o <= '0';
histogram_fill_o <= '0';
histogram_bin_o <= (others => '0');
histogram_adc_o <= (others => '0');
+ histogram_ts_o <= (others => '0');
histogram_pileup_o <= '0';
histogram_ovfl_o <= '0';
- histogram_trigger_filter <= histogram_trigger_filter_r;
-----------------------------------------------------------------------
-- Calculate Thresholds and values for FIFO Delay
end case;
-- Fill Histogram
- if (histogram_trigger_all = '0') then
+ if (histogram_trig_filter = '1') then
if (histogram_limits = '1') then
if (deltaTStore >= histogram_lower_limit and
deltaTStore <= histogram_upper_limit) then
histogram_fill_o <= '1';
histogram_bin_o <= CHANNEL_IN;
histogram_adc_o <= ADC_DATA_IN;
+ histogram_ts_o <= deltaTStore(10 downto 4);
histogram_pileup_o <= TIMESTAMP_STATUS_IN(S_PILEUP);
histogram_ovfl_o <= TIMESTAMP_STATUS_IN(S_OVFL);
end if;
histogram_fill_o <= '1';
histogram_bin_o <= CHANNEL_IN;
histogram_adc_o <= ADC_DATA_IN;
+ histogram_ts_o <= deltaTStore(10 downto 4);
histogram_pileup_o <= TIMESTAMP_STATUS_IN(S_PILEUP);
histogram_ovfl_o <= TIMESTAMP_STATUS_IN(S_OVFL);
end if;
end if;
-- Fill Histogram
- if (histogram_trigger_all = '1') then
+ if (histogram_trig_filter = '0') then
histogram_fill_o <= '1';
histogram_bin_o <= CHANNEL_IN;
histogram_adc_o <= ADC_DATA_IN;
+ histogram_ts_o <= (others => '0');
histogram_pileup_o <= TIMESTAMP_STATUS_IN(S_PILEUP);
histogram_ovfl_o <= TIMESTAMP_STATUS_IN(S_OVFL);
end if;
when "00"=> -- No validation
out_of_window_l_ctr <= (others => '0');
window_hit_ctr <= (others => '0');
- out_of_window_l_ctr <= (others => '0');
+ out_of_window_h_ctr <= (others => '0');
when "01"=> -- Start validation
out_of_window_l_ctr <= (others => '0');
window_hit_ctr <= (others => '0');
- out_of_window_l_ctr <= (others => '0');
+ out_of_window_h_ctr <= (others => '0');
when "10"=> -- End validation
out_of_window_l_ctr_r <= out_of_window_l_ctr;
window_hit_ctr_r <= window_hit_ctr;
- out_of_window_l_ctr_r <= out_of_window_l_ctr;
+ out_of_window_h_ctr_r <= out_of_window_h_ctr;
when "11" => -- Validation
if (out_of_window_l = '1') then
window_hit_ctr <= window_hit_ctr + 1;
end if;
- if (out_of_window_l = '1') then
- out_of_window_h_ctr <= out_of_window_h_ctr + 1;
+ if (out_of_window_h = '1') then
+ out_of_window_h_ctr <= out_of_window_h_ctr + 1;
end if;
end case;
end if;
end if;
end process PROC_SELF_TRIGGER;
+
+ timestamp_fpga_ff <= TIMESTAMP_FPGA_IN when rising_edge(CLK_IN);
+ timestamp_fpga_f <= timestamp_fpga_ff when rising_edge(CLK_IN);
PROC_TRIGGER_HANDLER: process(CLK_IN)
variable wait_for_data_time : unsigned(19 downto 0);
variable min_validation_time : unsigned(19 downto 0);
begin
if( rising_edge(CLK_IN) ) then
- timestamp_fpga_i <= TIMESTAMP_FPGA_IN;
if (RESET_IN = '1' or FAST_CLEAR_IN = '1') then
store_to_fifo <= '0';
trigger_busy_o <= '0';
wait_for_data_time :=
resize(nxyter_cv_time, 20) + data_fifo_delay_o * 32 + 280; --320;
+ -- ?????????????????????????
if (skip_wait_for_data = '1') then
min_validation_time :=
min_validation_time + wait_for_data_time;
timestamp_fpga <= (others => '0');
else
timestamp_fpga <=
- timestamp_fpga_i + fpga_timestamp_offset;
- timestamp_ref <= timestamp_fpga;
+ timestamp_fpga_f + fpga_timestamp_offset;
end if;
STATE <= S_WRITE_HEADER;
end if;
when S_WRITE_HEADER =>
state_d <= "10";
+ timestamp_ref <= timestamp_fpga;
- t_data_o(11 downto 0) <= timestamp_ref;
+ t_data_o(11 downto 0) <= timestamp_fpga;
t_data_o(21 downto 12) <= event_counter;
-- Readout Mode Mapping
-- Bit #3: self Triger mode
end process PROC_CHANNEL_STATUS;
PROC_DATA_FIFO_DELAY: process(CLK_IN)
- variable nx_cvt : unsigned(11 downto 0);
+ variable nx_cvt : unsigned(11 downto 0); -- convertion time in 4n steps
variable fifo_delay : unsigned(11 downto 0);
begin
if( rising_edge(CLK_IN) ) then
slv_no_more_data_o <= '0';
ts_window_offset <= (others => '0');
- ts_window_width <= "0000110010"; -- 50
- cts_trigger_delay <= x"0c8";
+ ts_window_width <= "0001100100"; -- 100 = 400ns
+ cts_trigger_delay <= x"019"; -- 25 = 100ns
readout_mode_r <= "0000";
- readout_time_max <= x"3e8";
- histogram_trigger_filter_r <= '1';
+ readout_time_max <= x"3e8"; -- 1000 = 10mus
+ histogram_trig_filter <= '1';
fpga_timestamp_offset <= (others => '0');
out_of_window_error_ctr_clear <= '0';
skip_wait_for_data <= '0';
- nxyter_cv_time <= x"190"; -- 400ns
- reset_hists_r <= '0';
+ nxyter_cv_time <= x"190"; -- 400ns
+
+ histogram_lower_limit <= (others => '0');
+ histogram_upper_limit <= (others => '1');
+ reset_hists <= '0';
+ histogram_limits <= '0';
+ histogram_trig_filter <= '0';
else
slv_data_out_o <= (others => '0');
slv_unknown_addr_o <= '0';
cts_trigger_delay(11 downto 10) <= (others => '0');
readout_time_max(11 downto 10) <= (others => '0');
out_of_window_error_ctr_clear <= '0';
- reset_hists_r <= '0';
+ reset_hists <= '0';
if (SLV_READ_IN = '1') then
case SLV_ADDR_IN is
slv_data_out_o(31 downto 16) <= (others => '0');
slv_ack_o <= '1';
+ --when x"001d" =>
+ -- slv_data_out_o(15 downto 0) <=
+ -- std_logic_vector(window_hit_ctr_r);
+ -- slv_data_out_o(31 downto 16) <= (others => '0');
+ -- slv_ack_o <= '1';
+
when x"001d" =>
slv_data_out_o(15 downto 0) <=
- std_logic_vector(window_hit_ctr_r);
+ std_logic_vector(out_of_window_h_ctr_r);
slv_data_out_o(31 downto 16) <= (others => '0');
slv_ack_o <= '1';
- --when x"001e" =>
- -- slv_data_out_o(15 downto 0) <=
- -- std_logic_vector(out_of_window_h_ctr_r);
- -- slv_data_out_o(31 downto 16) <= (others => '0');
- -- slv_ack_o <= '1';
-
when x"001e" =>
slv_data_out_o(27 downto 0) <= std_logic_vector(data_rate);
slv_data_out_o(31 downto 28) <= (others => '0');
std_logic_vector(histogram_upper_limit);
slv_data_out_o(29) <= '0';
slv_data_out_o(30) <= histogram_limits;
- slv_data_out_o(31) <= histogram_trigger_filter_r;
+ slv_data_out_o(31) <= histogram_trig_filter;
slv_ack_o <= '1';
when others =>
when x"001f" =>
histogram_lower_limit <= SLV_DATA_IN(13 downto 0);
histogram_upper_limit <= SLV_DATA_IN(28 downto 15);
- reset_hists_r <= SLV_DATA_IN(29);
+ reset_hists <= SLV_DATA_IN(29);
histogram_limits <= SLV_DATA_IN(30);
- histogram_trigger_filter_r <= SLV_DATA_IN(31);
+ histogram_trig_filter <= SLV_DATA_IN(31);
slv_ack_o <= '1';
when others =>
port map (
CLK_IN => CLK_IN,
RESET_IN => RESET_IN,
- PULSE_IN => reset_hists_r,
+ PULSE_IN => reset_hists,
LEVEL_OUT => reset_hists_o
);
HISTOGRAM_FILL_OUT <= histogram_fill_o;
HISTOGRAM_BIN_OUT <= histogram_bin_o;
HISTOGRAM_ADC_OUT <= histogram_adc_o;
+ HISTOGRAM_TS_OUT <= histogram_ts_o;
HISTOGRAM_PILEUP_OUT <= histogram_pileup_o;
HISTOGRAM_OVERFLOW_OUT <= histogram_ovfl_o;
HISTOGRAM_FILL_OUT : out std_logic;
HISTOGRAM_BIN_OUT : out std_logic_vector(6 downto 0);
HISTOGRAM_ADC_OUT : out std_logic_vector(11 downto 0);
+ HISTOGRAM_TS_OUT : out std_logic_vector(6 downto 0);
HISTOGRAM_PILEUP_OUT : out std_logic;
HISTOGRAM_OVERFLOW_OUT : out std_logic;
SLV_READ_IN : in std_logic;
CHANNEL_FILL_IN : in std_logic;
CHANNEL_ID_IN : in std_logic_vector(6 downto 0);
CHANNEL_ADC_IN : in std_logic_vector(11 downto 0);
+ CHANNEL_TS_IN : in std_logic_vector(6 downto 0);
CHANNEL_PILEUP_IN : in std_logic;
CHANNEL_OVERFLOW_IN : in std_logic;
SLV_READ_IN : in std_logic;
signal trigger_validate_fill : std_logic;
signal trigger_validate_bin : std_logic_vector(6 downto 0);
signal trigger_validate_adc : std_logic_vector(11 downto 0);
+ signal trigger_validate_ts : std_logic_vector(6 downto 0);
signal trigger_validate_pileup : std_logic;
signal trigger_validate_ovfl : std_logic;
signal reset_hists : std_logic;
HISTOGRAM_FILL_OUT => trigger_validate_fill,
HISTOGRAM_BIN_OUT => trigger_validate_bin,
HISTOGRAM_ADC_OUT => trigger_validate_adc,
+ HISTOGRAM_TS_OUT => trigger_validate_ts,
HISTOGRAM_PILEUP_OUT => trigger_validate_pileup,
HISTOGRAM_OVERFLOW_OUT => trigger_validate_ovfl,
CHANNEL_FILL_IN => trigger_validate_fill,
CHANNEL_ID_IN => trigger_validate_bin,
CHANNEL_ADC_IN => trigger_validate_adc,
+ CHANNEL_TS_IN => trigger_validate_ts,
CHANNEL_PILEUP_IN => trigger_validate_pileup,
CHANNEL_OVERFLOW_IN => trigger_validate_ovfl,
MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_fpga_timestamp_*/reset_nx_main_clk_in_ff*" 30 ns;
MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_fpga_timestamp_*/timestamp_reset_ff*" 10 ns;
-MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_fpga_timestamp_*/timestamp_sync_o*" 10 ns;
MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_fpga_timestamp_*/timestamp_hold_o_*" 30 ns;
MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/reset_nx_timestamp_clk_in_ff*" 30 ns;
MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/reset_handler_start_r*" 100 ns;
MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/johnson_counter_sync_r*" 100 ns;
MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/nx_timestamp_delay_r*" 100 ns;
-MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/nx_frame_word_delay_r*" 100 ns;
+MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/nx_frame_word_delay_rr*" 100 ns;
MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/fifo_full_r*" 100 ns;
MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/fifo_empty_r*" 100 ns;
MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/pll_adc_sample_clk_finedelb_r*" 100 ns;
-i 2
-l 5
-n 28
--t 28
+-t 50
-s 1
-c 1
-e 2
jspc29 / trb3.git / commitdiff