CLK_REF_FULL : in std_logic; -- TRBnet reference clock
SYSCLK : in std_logic; -- FPGA fabric clock
RESET : in std_logic; -- synchronous reset
- CLEAR : in std_logic; -- asynchronous reset
-- Media Interface TX/RX
MEDIA_MED2INT : out med2int_array_t(0 to 3);
MEDIA_INT2MED : in int2med_array_t(0 to 3);
global_reset_i(1) when ((quad_mode >= 8) and (IS_MODE(1) = c_IS_SLAVE)) else
global_reset_i(2) when ((quad_mode >= 8) and (IS_MODE(2) = c_IS_SLAVE)) else
global_reset_i(3) when ((quad_mode >= 8) and (IS_MODE(3) = c_IS_SLAVE)) else -- HEREWEARE
- GLOBAL_RESET_IN;
+ '0';
-------------------------------------------------
-- stable RX recovered clock available
CLK_TXI => clk_tx_full(i),
CLK_REF => CLK_REF_FULL,
RESET => RESET,
- CLEAR => CLEAR,
-- Media Interface
MEDIA_MED2INT => MEDIA_MED2INT(i),
MEDIA_INT2MED => MEDIA_INT2MED(i),
-- ports for synchronous operation
WORD_SYNC_IN => WORD_SYNC_IN,
WORD_SYNC_OUT => word_sync_i(i),
- GLOBAL_RESET_IN => GLOBAL_RESET_IN,
GLOBAL_RESET_OUT => global_reset_i(i),
LINK_TX_READY_IN => LINK_TX_READY_IN,
LINK_RX_READY_OUT => link_rx_ready_i(i),
CLK_TXI : in std_logic; -- TX clock, from SerDes TX channel
CLK_REF : in std_logic; -- SerDes reference clock
RESET : in std_logic;
- CLEAR : in std_logic;
-- Media Interface
MEDIA_MED2INT : out MED2INT; -- Media Interface OUT
MEDIA_INT2MED : in INT2MED; -- Media Interface IN
-- ports for synchronous operation
WORD_SYNC_IN : in std_logic; -- sync signal for Byte/Word Alignment
WORD_SYNC_OUT : out std_logic;
- GLOBAL_RESET_IN : in std_logic; -- global reset to master ports
GLOBAL_RESET_OUT : out std_logic; -- global reset from slave port
LINK_TX_READY_IN : in std_logic; --
LINK_RX_READY_OUT : out std_logic; --
signal link_tx_ready_qsys : std_logic;
signal link_status : std_logic_vector(3 downto 0);
signal link_status_qsys : std_logic_vector(3 downto 0);
-
+
-- attribute syn_keep : boolean;
-- attribute syn_preserve : boolean;
-- attribute syn_keep of rx_lsm_state : signal is true;
GLOBAL_RESET_OUT <= sd_los_q;
-- TX_CONTROL and RX_CONTROL reset
- reset_i <= (RESET or sd_los_q) when (IS_MODE = c_IS_SLAVE)
- else (RESET);
+-- reset_i <= (RESET or sd_los_q) when (IS_MODE = c_IS_SLAVE)
+-- else (RESET);
+ reset_i <= RESET;
+ -- We provide GLOBAL_RESET_OUT (in case of SLAVE port) to clock_reset_handler,
+ -- which turns it into global RESET signal.
+
-- for syncing later
link_tx_ready_i <= LINK_TX_READY_IN;
led_rx <= (media_med2int_i.dataready or led_rx) and not timer(20) when rising_edge(CLK_SYS);
led_tx <= (MEDIA_INT2MED.dataready or led_tx or sd_los_q) and not timer(20) when rising_edge(CLK_SYS);
+ -- REMARK: RESET or reset_i?
ROC_TIMER_PROC: process( CLK_SYS, RESET )
begin
if ( RESET = '1' ) then
media_med2int_i.stat_op(15) <= '0';
media_med2int_i.stat_op(14) <= '0'; --reset MUX
- media_med2int_i.stat_op(13) <= '0'; --make trbnet reset
+ media_med2int_i.stat_op(13) <= '0'; --not link_full_done_qsys; --make trbnet reset
media_med2int_i.stat_op(12) <= '0';
media_med2int_i.stat_op(11) <= led_tx;
media_med2int_i.stat_op(10) <= led_rx or last_led_rx;
media_med2int_i.stat_op(9) <= led_ok;
media_med2int_i.stat_op(8 downto 6) <= (others => '0');
- media_med2int_i.stat_op(5) <= link_tx_ready_qsys; -- tx_allow
- media_med2int_i.stat_op(4) <= link_rx_ready_qsys; -- rx_allow
+ media_med2int_i.stat_op(5) <= link_full_done_qsys; -- tx_allow
+ media_med2int_i.stat_op(4) <= link_full_done_qsys; -- rx_allow
media_med2int_i.stat_op(3 downto 0) <= link_status_qsys;
link_status <= x"0" when ((link_half_done_i = '1') and (link_full_done_i = '1'))
generic(\r
RESET_DELAY : std_logic_vector(15 downto 0) := x"1fff"\r
);\r
-port(\r
- CLEAR_IN : in std_logic; -- reset input (high active, async)\r
- CLEAR_N_IN : in std_logic; -- reset input (low active, async)\r
- CLK_IN : in std_logic; -- raw master clock, NOT from PLL/DLL!\r
- SYSCLK_IN : in std_logic; -- PLL/DLL remastered clock\r
- PLL_LOCKED_IN : in std_logic; -- master PLL lock signal (async)\r
- RESET_IN : in std_logic; -- general reset signal (SYSCLK)\r
- TRB_RESET_IN : in std_logic; -- TRBnet reset signal (SYSCLK)\r
- CLEAR_OUT : out std_logic; -- async reset out, USE WITH CARE!\r
- RESET_OUT : out std_logic; -- synchronous reset out (SYSCLK)\r
- DEBUG_OUT : out std_logic_vector(15 downto 0)\r
-);\r
-end;\r
+ port(\r
+ CLEAR_IN : in std_logic; -- reset input (high active, async)\r
+ CLEAR_N_IN : in std_logic; -- reset input (low active, async)\r
+ CLK_IN : in std_logic; -- raw master clock, NOT from PLL/DLL!\r
+ SYSCLK_IN : in std_logic; -- PLL/DLL remastered clock\r
+ PLL_LOCKED_IN : in std_logic; -- master PLL lock signal (async)\r
+ RESET_IN : in std_logic; -- general reset signal (SYSCLK)\r
+ TRB_RESET_IN : in std_logic; -- TRBnet reset signal (SYSCLK)\r
+ CLEAR_OUT : out std_logic; -- async reset out, USE WITH CARE!\r
+ RESET_OUT : out std_logic; -- synchronous reset out (SYSCLK)\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+ );\r
+end entity;\r
\r
-- This reset handler tries to generate a stable synchronous reset\r
-- for FPGA fabric. It waits for the system clock PLL to lock, reacts\r
jspc29 / trbnet.git / commitdiff