more details

diff --git a/electronics/electronics2013.tex b/electronics/electronics2013.tex
index 995a30dd015eefa0819fbc973929de6c45487441..1bb436763947785a32f36d8f1618901c5cf0df74 100644 (file)
--- a/electronics/electronics2013.tex
+++ b/electronics/electronics2013.tex
@@ -62,7 +62,8 @@ Voltage and JTAG switch (Bus) & 0 & 6 / 0+6 \\
 \hline
 Total & 13 & 15 / 7+8\\
 \end{tabularx}
-\caption{Inputs/Outputs from the FPGA, first value differential, second single ended}
+\caption{Inputs/Outputs from the FPGA for a converter board with 2 sensors. First value
+differential, second single ended}
 \end{table}
 
 
@@ -96,11 +97,22 @@ Such a TRB3-AddOn is currently in preparation at GSI (52 channels, 12 Bit, 40 MS
 Current sensing can be implemented with dedicated current monitors, e.g. TSC101 to reduce count of
 components.
 
+For latch-up protection, fast discriminators with settable threshold (via DAC) provide a logical
+signal to the FPGA about the current status of the current levels. Necessary action is taken by the
+logic in the FPGA and the corresponding voltages are switched.
+
+
 \subsection{Board Control}
 All voltages are switchable from FPGA. The JTAG chain needs the option to disable individual
 sensors. Both features can make use of a 74HC259 IC to reduce number of lines. This chip also
 provides the CE signals for ADCs if needed.
 
+For clamping voltages and current monitoring thresholds 4 configurable voltages are necessary per
+sensor. The clamping can be provided by the previous method where it can be changed with a
+potentiometer only. The threshold voltages for current monitoring must be configurable at run-time
+with a slow but precise DAC.
+
+
 
 \subsection{Connectivity}
 All communication to the TRB3 should be differential, maybe despite on some static signals. Test