--- /dev/null
+[Device]
+Family=latticescm
+PartType=LFSCM3GA25EP1
+PartName=LFSCM3GA25EP1-6FF1020C
+SpeedGrade=-6
+Package=FFBGA1020
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=PLL
+CoreRevision=4.0
+ModuleName=lattice_scm_clock_300
+SourceFormat=Schematic/VHDL
+ParameterFileVersion=1.0
+Date=07/23/2008
+Time=11:49:32
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+Clki_freq=100
+U_OFrq=300
+OP_Tol=1.0
+ClkOP_Freq= 300.000000
+U_SFrq=100
+OS_Tol=1.0
+ClkOS_Freq= 100.000000
+Phase=0
+FineDelay=0
+FeedbackClk=Internal
+Frequency=100
+enSpectrum=0
+smiport=0
+enRSTN=0
+Clki_boosting=DEL0
+Clkfb_boosting=DEL0
+Clki_fine=0
+Clkfb_fine=0
+enSpread=0
+modulation=1
+Desired=30
+Actual=30
+lock=Frequency
+enGSR=0
+VcoRate= 600.000000
+Bandwidth= 5.262395
+enHighBand=0
+enBypassP=0
+enBypassS=0
--- /dev/null
+clk i
+clkop o
+clkos o
+lock o
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v71_PROD_Build (58)
+-- Module Version: 4.0
+--/local/lattice/ispLever7.1/isptools/ispfpga/bin/lin/scuba -w -n lattice_scm_clock_300 -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type pll -fin 100 -mfreq 300 -nfreq 100 -clkos_fdel 0 -fb 0 -clki_del 0 -clki_fdel 0 -clkfb_del 0 -clkfb_fdel 0 -mtol 1.0 -ntol 1.0 -bw LOW -e
+
+-- Wed Jul 23 11:49:32 2008
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library SCM;
+use SCM.COMPONENTS.all;
+-- synopsys translate_on
+
+entity lattice_scm_clock_300 is
+ generic (
+ SMI_OFFSET : in String := "0x410"
+ );
+ port (
+ clk: in std_logic;
+ clkop: out std_logic;
+ clkos: out std_logic;
+ lock: out std_logic);
+ attribute dont_touch : string;
+ attribute dont_touch of lattice_scm_clock_300 : entity is "true";
+end lattice_scm_clock_300;
+
+architecture Structure of lattice_scm_clock_300 is
+
+ -- internal signal declarations
+ signal scuba_vlo: std_logic;
+ signal scuba_vhi: std_logic;
+ signal clkos_t: std_logic;
+ signal fb: std_logic;
+ signal clkop_t: std_logic;
+ signal clk_t: std_logic;
+
+ attribute module_type : string;
+ -- local component declarations
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component EHXPLLA
+ generic (SMI_OFFSET : in String
+ -- synopsys translate_off
+ ; GSR : in String; CLKOS_DIV : in Integer;
+ CLKOP_DIV : in Integer; CLKFB_DIV : in Integer;
+ CLKI_DIV : in Integer; CLKOS_FDEL : in Integer;
+ CLKFB_FDEL : in Integer; CLKI_FDEL : in Integer;
+ CLKOS_MODE : in String; CLKOP_MODE : in String;
+ PHASEADJ : in Integer; CLKOS_VCODEL : in Integer
+ -- synopsys translate_on
+ );
+ port (SMIADDR9: in std_logic; SMIADDR8: in std_logic;
+ SMIADDR7: in std_logic; SMIADDR6: in std_logic;
+ SMIADDR5: in std_logic; SMIADDR4: in std_logic;
+ SMIADDR3: in std_logic; SMIADDR2: in std_logic;
+ SMIADDR1: in std_logic; SMIADDR0: in std_logic;
+ SMIRD: in std_logic; SMIWR: in std_logic;
+ SMICLK: in std_logic; SMIWDATA: in std_logic;
+ SMIRSTN: in std_logic; CLKI: in std_logic;
+ CLKFB: in std_logic; RSTN: in std_logic;
+ CLKOS: out std_logic; CLKOP: out std_logic;
+ LOCK: out std_logic; CLKINTFB: out std_logic;
+ SMIRDATA: out std_logic);
+ end component;
+ attribute module_type of EHXPLLA : component is "EHXPLLA";
+ attribute ip_type : string;
+ attribute FREQUENCY_PIN_CLKOS : string;
+ attribute FREQUENCY_PIN_CLKOP : string;
+ attribute FREQUENCY_PIN_CLKI : string;
+ attribute VCO_LOWERFREQ : string;
+ attribute GMCFREQSEL : string;
+ attribute GSR : string;
+ attribute SPREAD_DIV2 : string;
+ attribute SPREAD_DIV1 : string;
+ attribute SPREAD_DRIFT : string;
+ attribute SPREAD : string;
+ attribute CLKFB_FDEL : string;
+ attribute CLKI_FDEL : string;
+ attribute CLKFB_PDEL : string;
+ attribute CLKI_PDEL : string;
+ attribute LF_RESISTOR : string;
+ attribute LF_IX5UA : string;
+ attribute CLKOS_FDEL : string;
+ attribute CLKOS_VCODEL : string;
+ attribute PHASEADJ : string;
+ attribute CLKOS_MODE : string;
+ attribute CLKOP_MODE : string;
+ attribute CLKOS_DIV : string;
+ attribute CLKOP_DIV : string;
+ attribute CLKFB_DIV : string;
+ attribute CLKI_DIV : string;
+ attribute ip_type of lattice_scm_clock_300_0_0 : label is "EHXPLLA";
+ attribute FREQUENCY_PIN_CLKOS of lattice_scm_clock_300_0_0 : label is "100.000000";
+ attribute FREQUENCY_PIN_CLKOP of lattice_scm_clock_300_0_0 : label is "300.000000";
+ attribute FREQUENCY_PIN_CLKI of lattice_scm_clock_300_0_0 : label is "100.000000";
+ attribute VCO_LOWERFREQ of lattice_scm_clock_300_0_0 : label is "DISABLED";
+ attribute GMCFREQSEL of lattice_scm_clock_300_0_0 : label is "HIGH";
+ attribute GSR of lattice_scm_clock_300_0_0 : label is "DISABLED";
+ attribute SPREAD_DIV2 of lattice_scm_clock_300_0_0 : label is "2";
+ attribute SPREAD_DIV1 of lattice_scm_clock_300_0_0 : label is "2";
+ attribute SPREAD_DRIFT of lattice_scm_clock_300_0_0 : label is "1";
+ attribute SPREAD of lattice_scm_clock_300_0_0 : label is "DISABLED";
+ attribute CLKFB_FDEL of lattice_scm_clock_300_0_0 : label is "0";
+ attribute CLKI_FDEL of lattice_scm_clock_300_0_0 : label is "0";
+ attribute CLKFB_PDEL of lattice_scm_clock_300_0_0 : label is "DEL0";
+ attribute CLKI_PDEL of lattice_scm_clock_300_0_0 : label is "DEL0";
+ attribute LF_RESISTOR of lattice_scm_clock_300_0_0 : label is "0b111010";
+ attribute LF_IX5UA of lattice_scm_clock_300_0_0 : label is "31";
+ attribute CLKOS_FDEL of lattice_scm_clock_300_0_0 : label is "0";
+ attribute CLKOS_VCODEL of lattice_scm_clock_300_0_0 : label is "0";
+ attribute PHASEADJ of lattice_scm_clock_300_0_0 : label is "0";
+ attribute CLKOS_MODE of lattice_scm_clock_300_0_0 : label is "DIV";
+ attribute CLKOP_MODE of lattice_scm_clock_300_0_0 : label is "DIV";
+ attribute CLKOS_DIV of lattice_scm_clock_300_0_0 : label is "6";
+ attribute CLKOP_DIV of lattice_scm_clock_300_0_0 : label is "2";
+ attribute CLKFB_DIV of lattice_scm_clock_300_0_0 : label is "6";
+ attribute CLKI_DIV of lattice_scm_clock_300_0_0 : label is "1";
+ attribute syn_keep : boolean;
+ attribute syn_noprune : boolean;
+ attribute syn_noprune of Structure : architecture is true;
+
+begin
+ -- component instantiation statements
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ lattice_scm_clock_300_0_0: EHXPLLA
+ generic map (SMI_OFFSET=> SMI_OFFSET
+ -- synopsys translate_off
+ , GSR=> "DISABLED", CLKFB_FDEL=> 0, CLKI_FDEL=> 0,
+ CLKOS_FDEL=> 0, CLKOS_VCODEL=> 0, PHASEADJ=> 0, CLKOS_MODE=> "DIV",
+ CLKOP_MODE=> "DIV", CLKOS_DIV=> 6, CLKOP_DIV=> 2, CLKFB_DIV=> 6,
+ CLKI_DIV=> 1
+ -- synopsys translate_on
+ )
+ port map (SMIADDR9=>scuba_vlo, SMIADDR8=>scuba_vlo,
+ SMIADDR7=>scuba_vlo, SMIADDR6=>scuba_vlo,
+ SMIADDR5=>scuba_vlo, SMIADDR4=>scuba_vlo,
+ SMIADDR3=>scuba_vlo, SMIADDR2=>scuba_vlo,
+ SMIADDR1=>scuba_vlo, SMIADDR0=>scuba_vlo, SMIRD=>scuba_vlo,
+ SMIWR=>scuba_vlo, SMICLK=>scuba_vlo, SMIWDATA=>scuba_vlo,
+ SMIRSTN=>scuba_vlo, CLKI=>clk_t, CLKFB=>fb, RSTN=>scuba_vhi,
+ CLKOS=>clkos_t, CLKOP=>clkop_t, LOCK=>lock, CLKINTFB=>fb,
+ SMIRDATA=>open);
+
+ clkos <= clkos_t;
+ clkop <= clkop_t;
+ clk_t <= clk;
+end Structure;
+
+-- synopsys translate_off
+library SCM;
+configuration Structure_CON of lattice_scm_clock_300 is
+ for Structure
+ for all:VHI use entity SCM.VHI(V); end for;
+ for all:VLO use entity SCM.VLO(V); end for;
+ for all:EHXPLLA use entity SCM.EHXPLLA(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+-- VHDL module instantiation generated by SCUBA ispLever_v71_PROD_Build (58)
+-- Module Version: 4.0
+-- Wed Jul 23 11:49:33 2008
+
+-- parameterized module component declaration
+component lattice_scm_clock_300
+ generic (SMI_OFFSET : in String := "0x410"
+ );
+ port (clk: in std_logic; clkop: out std_logic;
+ clkos: out std_logic; lock: out std_logic);
+end component;
+
+-- parameterized module component instance
+__ : lattice_scm_clock_300
+ generic map ( SMI_OFFSET=>____)
+ port map (clk=>__, clkop=>__, clkos=>__, lock=>__);
--- /dev/null
+[Device]
+Family=latticescm
+PartType=LFSCM3GA15EP1
+PartName=LFSCM3GA15EP1-5F256C
+SpeedGrade=-5
+Package=FPBGA256
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=FIFO_DC
+CoreRevision=4.4
+ModuleName=lattice_scm_fifo_16bit_dualport
+SourceFormat=Schematic/VHDL
+ParameterFileVersion=1.0
+Date=07/23/2008
+Time=14:50:38
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+FIFOImp=EBR Only
+RDepth=1024
+RWidth=18
+WDepth=1024
+WWidth=18
+regout=1
+CtrlByRdEn=0
+EmpFlg=1
+PeMode=Static - Single Threshold
+PeAssert=10
+PeDeassert=12
+FullFlg=1
+PfMode=Static - Single Threshold
+PfAssert=1008
+PfDeassert=506
+Reset=Sync
+RDataCount=0
+WDataCount=0
+EnECC=0
--- /dev/null
+Data[17] i
+Data[16] i
+Data[15] i
+Data[14] i
+Data[13] i
+Data[12] i
+Data[11] i
+Data[10] i
+Data[9] i
+Data[8] i
+Data[7] i
+Data[6] i
+Data[5] i
+Data[4] i
+Data[3] i
+Data[2] i
+Data[1] i
+Data[0] i
+WrClock i
+RdClock i
+WrEn i
+RdEn i
+Reset i
+RPReset i
+Q[17] o
+Q[16] o
+Q[15] o
+Q[14] o
+Q[13] o
+Q[12] o
+Q[11] o
+Q[10] o
+Q[9] o
+Q[8] o
+Q[7] o
+Q[6] o
+Q[5] o
+Q[4] o
+Q[3] o
+Q[2] o
+Q[1] o
+Q[0] o
+Empty o
+Full o
+AlmostEmpty o
+AlmostFull o
--- /dev/null
+SCUBA, Version ispLever_v71_PROD_Build (58)
+Wed Jul 23 14:50:39 2008
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp. All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
+Copyright (c) 2001 Agere Systems All rights reserved.
+Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.
+
+ Issued command : /local/lattice/ispLever7.1/isptools/ispfpga/bin/lin/scuba -w -n lattice_scm_fifo_16bit_dualport -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -depth 1024 -width 18 -rwidth 18 -regout -no_enable -pe 10 -pf 1008 -sync_reset -e
+ Circuit name : lattice_scm_fifo_16bit_dualport
+ Module type : ebfifo
+ Module Version : 4.4
+ Ports :
+ Inputs : Data[17:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset
+ Outputs : Q[17:0], Empty, Full, AlmostEmpty, AlmostFull
+ I/O buffer : not inserted
+ EDIF output : suppressed
+ VHDL output : lattice_scm_fifo_16bit_dualport.vhd
+ VHDL template : lattice_scm_fifo_16bit_dualport_tmpl.vhd
+ VHDL testbench : tb_lattice_scm_fifo_16bit_dualport_tmpl.vhd
+ VHDL purpose : for synthesis and simulation
+ Bus notation : big endian
+ Report output : lattice_scm_fifo_16bit_dualport.srp
+ Element Usage :
+ FIFO16KA : 1
+ Estimated Resource Usage:
+ EBR : 1
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v71_PROD_Build (58)
+-- Module Version: 4.4
+--/local/lattice/ispLever7.1/isptools/ispfpga/bin/lin/scuba -w -n lattice_scm_fifo_16bit_dualport -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -depth 1024 -width 18 -rwidth 18 -regout -no_enable -pe 10 -pf 1008 -sync_reset -e
+
+-- Wed Jul 23 14:50:39 2008
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library SCM;
+use SCM.COMPONENTS.all;
+-- synopsys translate_on
+
+entity lattice_scm_fifo_16bit_dualport is
+ port (
+ Data: in std_logic_vector(17 downto 0);
+ WrClock: in std_logic;
+ RdClock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ RPReset: in std_logic;
+ Q: out std_logic_vector(17 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic;
+ AlmostEmpty: out std_logic;
+ AlmostFull: out std_logic);
+end lattice_scm_fifo_16bit_dualport;
+
+architecture Structure of lattice_scm_fifo_16bit_dualport is
+
+ -- internal signal declarations
+ signal Empty_int: std_logic;
+ signal Full_int: std_logic;
+ signal scuba_vhi: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component FIFO16KA
+ -- synopsys translate_off
+ generic (FULLPOINTER1 : in std_logic_vector(14 downto 0);
+ FULLPOINTER : in std_logic_vector(14 downto 0);
+ AFPOINTER1 : in std_logic_vector(14 downto 0);
+ AEPOINTER1 : in std_logic_vector(14 downto 0);
+ AFPOINTER : in std_logic_vector(14 downto 0);
+ AEPOINTER : in std_logic_vector(14 downto 0);
+ CSDECODE_R : in std_logic_vector(1 downto 0);
+ CSDECODE_W : in std_logic_vector(1 downto 0);
+ RESETMODE : in String; REGMODE : in String;
+ DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
+ -- synopsys translate_on
+ port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
+ DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
+ DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
+ DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
+ DI12: in std_logic; DI13: in std_logic;
+ DI14: in std_logic; DI15: in std_logic;
+ DI16: in std_logic; DI17: in std_logic;
+ DI18: in std_logic; DI19: in std_logic;
+ DI20: in std_logic; DI21: in std_logic;
+ DI22: in std_logic; DI23: in std_logic;
+ DI24: in std_logic; DI25: in std_logic;
+ DI26: in std_logic; DI27: in std_logic;
+ DI28: in std_logic; DI29: in std_logic;
+ DI30: in std_logic; DI31: in std_logic;
+ DI32: in std_logic; DI33: in std_logic;
+ DI34: in std_logic; DI35: in std_logic;
+ FULLI: in std_logic; CSW0: in std_logic;
+ CSW1: in std_logic; EMPTYI: in std_logic;
+ CSR0: in std_logic; CSR1: in std_logic; WE: in std_logic;
+ RE: in std_logic; CLKW: in std_logic; CLKR: in std_logic;
+ RST: in std_logic; RPRST: in std_logic;
+ DO0: out std_logic; DO1: out std_logic;
+ DO2: out std_logic; DO3: out std_logic;
+ DO4: out std_logic; DO5: out std_logic;
+ DO6: out std_logic; DO7: out std_logic;
+ DO8: out std_logic; DO9: out std_logic;
+ DO10: out std_logic; DO11: out std_logic;
+ DO12: out std_logic; DO13: out std_logic;
+ DO14: out std_logic; DO15: out std_logic;
+ DO16: out std_logic; DO17: out std_logic;
+ DO18: out std_logic; DO19: out std_logic;
+ DO20: out std_logic; DO21: out std_logic;
+ DO22: out std_logic; DO23: out std_logic;
+ DO24: out std_logic; DO25: out std_logic;
+ DO26: out std_logic; DO27: out std_logic;
+ DO28: out std_logic; DO29: out std_logic;
+ DO30: out std_logic; DO31: out std_logic;
+ DO32: out std_logic; DO33: out std_logic;
+ DO34: out std_logic; DO35: out std_logic;
+ EF: out std_logic; AEF: out std_logic; AFF: out std_logic;
+ FF: out std_logic);
+ end component;
+ attribute FULLPOINTER1 : string;
+ attribute FULLPOINTER : string;
+ attribute AFPOINTER1 : string;
+ attribute AFPOINTER : string;
+ attribute AEPOINTER1 : string;
+ attribute AEPOINTER : string;
+ attribute RESETMODE : string;
+ attribute REGMODE : string;
+ attribute CSDECODE_R : string;
+ attribute CSDECODE_W : string;
+ attribute DATA_WIDTH_R : string;
+ attribute DATA_WIDTH_W : string;
+ attribute FULLPOINTER1 of lattice_scm_fifo_16bit_dualport_0_0 : label is "0b011111111100001";
+ attribute FULLPOINTER of lattice_scm_fifo_16bit_dualport_0_0 : label is "0b011111111110001";
+ attribute AFPOINTER1 of lattice_scm_fifo_16bit_dualport_0_0 : label is "0b011111011100001";
+ attribute AFPOINTER of lattice_scm_fifo_16bit_dualport_0_0 : label is "0b011111011110001";
+ attribute AEPOINTER1 of lattice_scm_fifo_16bit_dualport_0_0 : label is "0b000000010111111";
+ attribute AEPOINTER of lattice_scm_fifo_16bit_dualport_0_0 : label is "0b000000010101111";
+ attribute RESETMODE of lattice_scm_fifo_16bit_dualport_0_0 : label is "SYNC";
+ attribute REGMODE of lattice_scm_fifo_16bit_dualport_0_0 : label is "OUTREG";
+ attribute CSDECODE_R of lattice_scm_fifo_16bit_dualport_0_0 : label is "0b11";
+ attribute CSDECODE_W of lattice_scm_fifo_16bit_dualport_0_0 : label is "0b11";
+ attribute DATA_WIDTH_R of lattice_scm_fifo_16bit_dualport_0_0 : label is "18";
+ attribute DATA_WIDTH_W of lattice_scm_fifo_16bit_dualport_0_0 : label is "18";
+ attribute syn_keep : boolean;
+
+begin
+ -- component instantiation statements
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ lattice_scm_fifo_16bit_dualport_0_0: FIFO16KA
+ -- synopsys translate_off
+ generic map (FULLPOINTER1=> "011111111100001", FULLPOINTER=> "011111111110001",
+ AFPOINTER1=> "011111011100001", AFPOINTER=> "011111011110001",
+ AEPOINTER1=> "000000010111111", AEPOINTER=> "000000010101111",
+ RESETMODE=> "SYNC", REGMODE=> "OUTREG", CSDECODE_R=> "11",
+ CSDECODE_W=> "11", DATA_WIDTH_R=> 18, DATA_WIDTH_W=> 18)
+ -- synopsys translate_on
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
+ DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11),
+ DI12=>Data(12), DI13=>Data(13), DI14=>Data(14),
+ DI15=>Data(15), DI16=>Data(16), DI17=>Data(17),
+ DI18=>scuba_vlo, DI19=>scuba_vlo, DI20=>scuba_vlo,
+ DI21=>scuba_vlo, DI22=>scuba_vlo, DI23=>scuba_vlo,
+ DI24=>scuba_vlo, DI25=>scuba_vlo, DI26=>scuba_vlo,
+ DI27=>scuba_vlo, DI28=>scuba_vlo, DI29=>scuba_vlo,
+ DI30=>scuba_vlo, DI31=>scuba_vlo, DI32=>scuba_vlo,
+ DI33=>scuba_vlo, DI34=>scuba_vlo, DI35=>scuba_vlo,
+ FULLI=>Full_int, CSW0=>scuba_vhi, CSW1=>scuba_vhi,
+ EMPTYI=>Empty_int, CSR0=>RdEn, CSR1=>scuba_vhi, WE=>WrEn,
+ RE=>scuba_vhi, CLKW=>WrClock, CLKR=>RdClock, RST=>Reset,
+ RPRST=>RPReset, DO0=>Q(0), DO1=>Q(1), DO2=>Q(2), DO3=>Q(3),
+ DO4=>Q(4), DO5=>Q(5), DO6=>Q(6), DO7=>Q(7), DO8=>Q(8),
+ DO9=>Q(9), DO10=>Q(10), DO11=>Q(11), DO12=>Q(12),
+ DO13=>Q(13), DO14=>Q(14), DO15=>Q(15), DO16=>Q(16),
+ DO17=>Q(17), DO18=>open, DO19=>open, DO20=>open, DO21=>open,
+ DO22=>open, DO23=>open, DO24=>open, DO25=>open, DO26=>open,
+ DO27=>open, DO28=>open, DO29=>open, DO30=>open, DO31=>open,
+ DO32=>open, DO33=>open, DO34=>open, DO35=>open,
+ EF=>Empty_int, AEF=>AlmostEmpty, AFF=>AlmostFull,
+ FF=>Full_int);
+
+ Empty <= Empty_int;
+ Full <= Full_int;
+end Structure;
+
+-- synopsys translate_off
+library SCM;
+configuration Structure_CON of lattice_scm_fifo_16bit_dualport is
+ for Structure
+ for all:VHI use entity SCM.VHI(V); end for;
+ for all:VLO use entity SCM.VLO(V); end for;
+ for all:FIFO16KA use entity SCM.FIFO16KA(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+-- VHDL module instantiation generated by SCUBA ispLever_v71_PROD_Build (58)
+-- Module Version: 4.4
+-- Wed Jul 23 14:50:39 2008
+
+-- parameterized module component declaration
+component lattice_scm_fifo_16bit_dualport
+ port (Data: in std_logic_vector(17 downto 0);
+ WrClock: in std_logic; RdClock: in std_logic;
+ WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic;
+ RPReset: in std_logic; Q: out std_logic_vector(17 downto 0);
+ Empty: out std_logic; Full: out std_logic;
+ AlmostEmpty: out std_logic; AlmostFull: out std_logic);
+end component;
+
+-- parameterized module component instance
+__ : lattice_scm_fifo_16bit_dualport
+ port map (Data(17 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__,
+ RdEn=>__, Reset=>__, RPReset=>__, Q(17 downto 0)=>__, Empty=>__,
+ Full=>__, AlmostEmpty=>__, AlmostFull=>__);
--- /dev/null
+[Device]
+Family=latticescm
+PartType=LFSCM3GA25EP1
+PartName=LFSCM3GA25EP1-5FF1020CES
+SpeedGrade=-5
+Package=FFBGA1020
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=FIFO_DC
+CoreRevision=4.2
+ModuleName=lattice_scm_fifo_18x16
+SourceFormat=Schematic/VHDL
+ParameterFileVersion=1.0
+Date=02/08/2008
+Time=13:39:45
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+FIFOImp=LUT Based
+RDepth=16
+RWidth=18
+WDepth=16
+WWidth=18
+regout=0
+CtrlByRdEn=0
+EmpFlg=0
+PeMode=Static - Single Threshold
+PeAssert=10
+PeDeassert=12
+FullFlg=0
+PfMode=Static - Single Threshold
+PfAssert=508
+PfDeassert=506
+Reset=Sync
+RDataCount=0
+WDataCount=0
+EnECC=0
--- /dev/null
+Data[17] i
+Data[16] i
+Data[15] i
+Data[14] i
+Data[13] i
+Data[12] i
+Data[11] i
+Data[10] i
+Data[9] i
+Data[8] i
+Data[7] i
+Data[6] i
+Data[5] i
+Data[4] i
+Data[3] i
+Data[2] i
+Data[1] i
+Data[0] i
+WrClock i
+RdClock i
+WrEn i
+RdEn i
+Reset i
+RPReset i
+Q[17] o
+Q[16] o
+Q[15] o
+Q[14] o
+Q[13] o
+Q[12] o
+Q[11] o
+Q[10] o
+Q[9] o
+Q[8] o
+Q[7] o
+Q[6] o
+Q[5] o
+Q[4] o
+Q[3] o
+Q[2] o
+Q[1] o
+Q[0] o
+Empty o
+Full o
--- /dev/null
+SCUBA, Version ispLever_v70_Prod_Build (55)
+Fri Feb 8 13:39:45 2008
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp. All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
+Copyright (c) 2001 Agere Systems All rights reserved.
+Copyright (c) 2002-2007 Lattice Semiconductor Corporation, All rights reserved.
+
+ Issued command : /opt/lattice/isplever7.0/isptools/ispfpga/bin/lin/scuba -w -n lattice_scm_fifo_18x16 -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -depth 16 -width 18 -rwidth 18 -pfu_fifo -no_enable -pe -1 -pf -1 -sync_reset -e
+ Circuit name : lattice_scm_fifo_18x16
+ Module type : ebfifo
+ Module Version : 4.2
+ Ports :
+ Inputs : Data[17:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset
+ Outputs : Q[17:0], Empty, Full
+ I/O buffer : not inserted
+ EDIF output : suppressed
+ VHDL output : lattice_scm_fifo_18x16.vhd
+ VHDL template : lattice_scm_fifo_18x16_tmpl.vhd
+ VHDL testbench : tb_lattice_scm_fifo_18x16_tmpl.vhd
+ VHDL purpose : for synthesis and simulation
+ Bus notation : big endian
+ Report output : lattice_scm_fifo_18x16.srp
+ Element Usage :
+ DPR16X2 : 9
+ ROM16X1 : 12
+ AND2 : 2
+ OR2 : 1
+ XOR2 : 8
+ INV : 2
+ FADD2 : 2
+ CU2 : 6
+ AGEB2 : 6
+ FD1P3BX : 2
+ FD1P3DX : 46
+ FD1S3BX : 1
+ FD1S3DX : 21
+ Estimated Resource Usage:
+ LUT : 51
+ DRAM : 18
+ Reg : 70
--- /dev/null
+[Device]
+Family=latticescm
+PartType=LFSCM3GA25EP1
+PartName=LFSCM3GA25EP1-5FF1020CES
+SpeedGrade=-5
+Package=FFBGA1020
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=FIFO_DC
+CoreRevision=4.2
+ModuleName=lattice_scm_fifo_18x1k
+SourceFormat=Schematic/VHDL
+ParameterFileVersion=1.0
+Date=02/08/2008
+Time=13:39:06
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+FIFOImp=EBR Only
+RDepth=1024
+RWidth=18
+WDepth=1024
+WWidth=18
+regout=0
+CtrlByRdEn=0
+EmpFlg=1
+PeMode=Static - Single Threshold
+PeAssert=10
+PeDeassert=12
+FullFlg=1
+PfMode=Static - Single Threshold
+PfAssert=508
+PfDeassert=506
+Reset=Sync
+RDataCount=0
+WDataCount=0
+EnECC=0
--- /dev/null
+Data[17] i
+Data[16] i
+Data[15] i
+Data[14] i
+Data[13] i
+Data[12] i
+Data[11] i
+Data[10] i
+Data[9] i
+Data[8] i
+Data[7] i
+Data[6] i
+Data[5] i
+Data[4] i
+Data[3] i
+Data[2] i
+Data[1] i
+Data[0] i
+WrClock i
+RdClock i
+WrEn i
+RdEn i
+Reset i
+RPReset i
+Q[17] o
+Q[16] o
+Q[15] o
+Q[14] o
+Q[13] o
+Q[12] o
+Q[11] o
+Q[10] o
+Q[9] o
+Q[8] o
+Q[7] o
+Q[6] o
+Q[5] o
+Q[4] o
+Q[3] o
+Q[2] o
+Q[1] o
+Q[0] o
+Empty o
+Full o
+AlmostEmpty o
+AlmostFull o
--- /dev/null
+SCUBA, Version ispLever_v70_Prod_Build (55)
+Fri Feb 8 13:39:06 2008
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp. All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
+Copyright (c) 2001 Agere Systems All rights reserved.
+Copyright (c) 2002-2007 Lattice Semiconductor Corporation, All rights reserved.
+
+ Issued command : /opt/lattice/isplever7.0/isptools/ispfpga/bin/lin/scuba -w -n lattice_scm_fifo_18x1k -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -depth 1024 -width 18 -rwidth 18 -no_enable -pe 10 -pf 508 -sync_reset -e
+ Circuit name : lattice_scm_fifo_18x1k
+ Module type : ebfifo
+ Module Version : 4.2
+ Ports :
+ Inputs : Data[17:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset
+ Outputs : Q[17:0], Empty, Full, AlmostEmpty, AlmostFull
+ I/O buffer : not inserted
+ EDIF output : suppressed
+ VHDL output : lattice_scm_fifo_18x1k.vhd
+ VHDL template : lattice_scm_fifo_18x1k_tmpl.vhd
+ VHDL testbench : tb_lattice_scm_fifo_18x1k_tmpl.vhd
+ VHDL purpose : for synthesis and simulation
+ Bus notation : big endian
+ Report output : lattice_scm_fifo_18x1k.srp
+ Element Usage :
+ FIFO16KA : 1
+ Estimated Resource Usage:
+ EBR : 1
--- /dev/null
+[Device]
+Family=latticescm
+PartType=LFSCM3GA25EP1
+PartName=LFSCM3GA25EP1-5FF1020CES
+SpeedGrade=-5
+Package=FFBGA1020
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=FIFO_DC
+CoreRevision=4.2
+ModuleName=lattice_scm_fifo_18x32
+SourceFormat=Schematic/VHDL
+ParameterFileVersion=1.0
+Date=02/08/2008
+Time=13:40:10
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+FIFOImp=LUT Based
+RDepth=32
+RWidth=18
+WDepth=32
+WWidth=18
+regout=0
+CtrlByRdEn=0
+EmpFlg=0
+PeMode=Static - Single Threshold
+PeAssert=10
+PeDeassert=12
+FullFlg=0
+PfMode=Static - Single Threshold
+PfAssert=508
+PfDeassert=506
+Reset=Sync
+RDataCount=0
+WDataCount=0
+EnECC=0
--- /dev/null
+Data[17] i
+Data[16] i
+Data[15] i
+Data[14] i
+Data[13] i
+Data[12] i
+Data[11] i
+Data[10] i
+Data[9] i
+Data[8] i
+Data[7] i
+Data[6] i
+Data[5] i
+Data[4] i
+Data[3] i
+Data[2] i
+Data[1] i
+Data[0] i
+WrClock i
+RdClock i
+WrEn i
+RdEn i
+Reset i
+RPReset i
+Q[17] o
+Q[16] o
+Q[15] o
+Q[14] o
+Q[13] o
+Q[12] o
+Q[11] o
+Q[10] o
+Q[9] o
+Q[8] o
+Q[7] o
+Q[6] o
+Q[5] o
+Q[4] o
+Q[3] o
+Q[2] o
+Q[1] o
+Q[0] o
+Empty o
+Full o
--- /dev/null
+SCUBA, Version ispLever_v70_Prod_Build (55)
+Fri Feb 8 13:40:11 2008
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp. All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
+Copyright (c) 2001 Agere Systems All rights reserved.
+Copyright (c) 2002-2007 Lattice Semiconductor Corporation, All rights reserved.
+
+ Issued command : /opt/lattice/isplever7.0/isptools/ispfpga/bin/lin/scuba -w -n lattice_scm_fifo_18x32 -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -depth 32 -width 18 -rwidth 18 -pfu_fifo -no_enable -pe -1 -pf -1 -sync_reset -e
+ Circuit name : lattice_scm_fifo_18x32
+ Module type : ebfifo
+ Module Version : 4.2
+ Ports :
+ Inputs : Data[17:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset
+ Outputs : Q[17:0], Empty, Full
+ I/O buffer : not inserted
+ EDIF output : suppressed
+ VHDL output : lattice_scm_fifo_18x32.vhd
+ VHDL template : lattice_scm_fifo_18x32_tmpl.vhd
+ VHDL testbench : tb_lattice_scm_fifo_18x32_tmpl.vhd
+ VHDL purpose : for synthesis and simulation
+ Bus notation : big endian
+ Report output : lattice_scm_fifo_18x32.srp
+ Element Usage :
+ DPR16X2 : 18
+ ROM16X1 : 16
+ MUX21 : 18
+ AND2 : 2
+ OR2 : 1
+ XOR2 : 10
+ INV : 3
+ FADD2 : 2
+ CU2 : 6
+ AGEB2 : 6
+ FD1P3BX : 2
+ FD1P3DX : 52
+ FD1S3BX : 1
+ FD1S3DX : 25
+ Estimated Resource Usage:
+ LUT : 75
+ DRAM : 36
+ Reg : 80
--- /dev/null
+[Device]
+Family=latticescm
+PartType=LFSCM3GA25EP1
+PartName=LFSCM3GA25EP1-5FF1020CES
+SpeedGrade=-5
+Package=FFBGA1020
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=FIFO_DC
+CoreRevision=4.2
+ModuleName=lattice_scm_fifo_18x64
+SourceFormat=Schematic/VHDL
+ParameterFileVersion=1.0
+Date=02/08/2008
+Time=13:40:40
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+FIFOImp=LUT Based
+RDepth=64
+RWidth=18
+WDepth=64
+WWidth=18
+regout=0
+CtrlByRdEn=0
+EmpFlg=0
+PeMode=Static - Single Threshold
+PeAssert=10
+PeDeassert=12
+FullFlg=0
+PfMode=Static - Single Threshold
+PfAssert=508
+PfDeassert=506
+Reset=Sync
+RDataCount=0
+WDataCount=0
+EnECC=0
--- /dev/null
+Data[17] i
+Data[16] i
+Data[15] i
+Data[14] i
+Data[13] i
+Data[12] i
+Data[11] i
+Data[10] i
+Data[9] i
+Data[8] i
+Data[7] i
+Data[6] i
+Data[5] i
+Data[4] i
+Data[3] i
+Data[2] i
+Data[1] i
+Data[0] i
+WrClock i
+RdClock i
+WrEn i
+RdEn i
+Reset i
+RPReset i
+Q[17] o
+Q[16] o
+Q[15] o
+Q[14] o
+Q[13] o
+Q[12] o
+Q[11] o
+Q[10] o
+Q[9] o
+Q[8] o
+Q[7] o
+Q[6] o
+Q[5] o
+Q[4] o
+Q[3] o
+Q[2] o
+Q[1] o
+Q[0] o
+Empty o
+Full o
--- /dev/null
+SCUBA, Version ispLever_v70_Prod_Build (55)
+Fri Feb 8 13:40:40 2008
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp. All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
+Copyright (c) 2001 Agere Systems All rights reserved.
+Copyright (c) 2002-2007 Lattice Semiconductor Corporation, All rights reserved.
+
+ Issued command : /opt/lattice/isplever7.0/isptools/ispfpga/bin/lin/scuba -w -n lattice_scm_fifo_18x64 -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -depth 64 -width 18 -rwidth 18 -pfu_fifo -no_enable -pe -1 -pf -1 -sync_reset -e
+ Circuit name : lattice_scm_fifo_18x64
+ Module type : ebfifo
+ Module Version : 4.2
+ Ports :
+ Inputs : Data[17:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset
+ Outputs : Q[17:0], Empty, Full
+ I/O buffer : not inserted
+ EDIF output : suppressed
+ VHDL output : lattice_scm_fifo_18x64.vhd
+ VHDL template : lattice_scm_fifo_18x64_tmpl.vhd
+ VHDL testbench : tb_lattice_scm_fifo_18x64_tmpl.vhd
+ VHDL purpose : for synthesis and simulation
+ Bus notation : big endian
+ Report output : lattice_scm_fifo_18x64.srp
+ Element Usage :
+ DPR16X2 : 36
+ ROM16X1 : 20
+ MUX41 : 18
+ AND2 : 2
+ OR2 : 1
+ XOR2 : 12
+ INV : 4
+ FADD2 : 2
+ CU2 : 8
+ AGEB2 : 8
+ FD1P3BX : 2
+ FD1P3DX : 58
+ FD1S3BX : 1
+ FD1S3DX : 29
+ Estimated Resource Usage:
+ LUT : 89
+ DRAM : 72
+ Reg : 90
--- /dev/null
+-- VHDL testbench template generated by SCUBA ispLever_v70_Prod_Build (55)
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+entity tb is
+end entity tb;
+
+
+architecture test of tb is
+
+ component lattice_scm_fifo_18x16
+ port (Data : in std_logic_vector(17 downto 0);
+ WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic;
+ RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic;
+ Q : out std_logic_vector(17 downto 0); Empty: out std_logic;
+ Full: out std_logic
+ );
+ end component;
+
+ signal Data : std_logic_vector(17 downto 0) := (others => '0');
+ signal WrClock: std_logic := '0';
+ signal RdClock: std_logic := '0';
+ signal WrEn: std_logic := '0';
+ signal RdEn: std_logic := '0';
+ signal Reset: std_logic := '0';
+ signal RPReset: std_logic := '0';
+ signal Q : std_logic_vector(17 downto 0);
+ signal Empty: std_logic;
+ signal Full: std_logic;
+begin
+ u1 : lattice_scm_fifo_18x16
+ port map (Data => Data, WrClock => WrClock, RdClock => RdClock,
+ WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset,
+ Q => Q, Empty => Empty, Full => Full
+ );
+
+ process
+
+ begin
+ Data <= (others => '0') ;
+ wait for 100 ns;
+ wait until Reset = '0';
+ for i in 0 to 19 loop
+ wait until WrClock'event and WrClock = '1';
+ Data <= Data + '1' after 1 ns;
+ end loop;
+ wait;
+ end process;
+
+ WrClock <= not WrClock after 5.00 ns;
+
+ RdClock <= not RdClock after 5.00 ns;
+
+ process
+
+ begin
+ WrEn <= '0' ;
+ wait for 100 ns;
+ wait until Reset = '0';
+ for i in 0 to 19 loop
+ wait until WrClock'event and WrClock = '1';
+ WrEn <= '1' after 1 ns;
+ end loop;
+ WrEn <= '0' ;
+ wait;
+ end process;
+
+ process
+
+ begin
+ RdEn <= '0' ;
+ wait until Reset = '0';
+ wait until WrEn = '1';
+ wait until WrEn = '0';
+ for i in 0 to 19 loop
+ wait until RdClock'event and RdClock = '1';
+ RdEn <= '1' after 1 ns;
+ end loop;
+ RdEn <= '0' ;
+ wait;
+ end process;
+
+ process
+
+ begin
+ Reset <= '1' ;
+ wait for 100 ns;
+ Reset <= '0' ;
+ wait;
+ end process;
+
+ process
+
+ begin
+ RPReset <= '1' ;
+ wait for 100 ns;
+ RPReset <= '0' ;
+ wait;
+ end process;
+
+end architecture test;
--- /dev/null
+-- VHDL testbench template generated by SCUBA ispLever_v70_Prod_Build (55)
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+entity tb is
+end entity tb;
+
+
+architecture test of tb is
+
+ component lattice_scm_fifo_18x1k
+ port (Data : in std_logic_vector(17 downto 0);
+ WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic;
+ RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic;
+ Q : out std_logic_vector(17 downto 0); Empty: out std_logic;
+ Full: out std_logic; AlmostEmpty: out std_logic;
+ AlmostFull: out std_logic
+ );
+ end component;
+
+ signal Data : std_logic_vector(17 downto 0) := (others => '0');
+ signal WrClock: std_logic := '0';
+ signal RdClock: std_logic := '0';
+ signal WrEn: std_logic := '0';
+ signal RdEn: std_logic := '0';
+ signal Reset: std_logic := '0';
+ signal RPReset: std_logic := '0';
+ signal Q : std_logic_vector(17 downto 0);
+ signal Empty: std_logic;
+ signal Full: std_logic;
+ signal AlmostEmpty: std_logic;
+ signal AlmostFull: std_logic;
+begin
+ u1 : lattice_scm_fifo_18x1k
+ port map (Data => Data, WrClock => WrClock, RdClock => RdClock,
+ WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset,
+ Q => Q, Empty => Empty, Full => Full, AlmostEmpty => AlmostEmpty,
+ AlmostFull => AlmostFull
+ );
+
+ process
+
+ begin
+ Data <= (others => '0') ;
+ wait for 100 ns;
+ wait until Reset = '0';
+ for i in 0 to 1027 loop
+ wait until WrClock'event and WrClock = '1';
+ Data <= Data + '1' after 1 ns;
+ end loop;
+ wait;
+ end process;
+
+ WrClock <= not WrClock after 5.00 ns;
+
+ RdClock <= not RdClock after 5.00 ns;
+
+ process
+
+ begin
+ WrEn <= '0' ;
+ wait for 100 ns;
+ wait until Reset = '0';
+ for i in 0 to 1027 loop
+ wait until WrClock'event and WrClock = '1';
+ WrEn <= '1' after 1 ns;
+ end loop;
+ WrEn <= '0' ;
+ wait;
+ end process;
+
+ process
+
+ begin
+ RdEn <= '0' ;
+ wait until Reset = '0';
+ wait until WrEn = '1';
+ wait until WrEn = '0';
+ for i in 0 to 1027 loop
+ wait until RdClock'event and RdClock = '1';
+ RdEn <= '1' after 1 ns;
+ end loop;
+ RdEn <= '0' ;
+ wait;
+ end process;
+
+ process
+
+ begin
+ Reset <= '1' ;
+ wait for 100 ns;
+ Reset <= '0' ;
+ wait;
+ end process;
+
+ process
+
+ begin
+ RPReset <= '1' ;
+ wait for 100 ns;
+ RPReset <= '0' ;
+ wait;
+ end process;
+
+end architecture test;
--- /dev/null
+-- VHDL testbench template generated by SCUBA ispLever_v70_Prod_Build (55)
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+entity tb is
+end entity tb;
+
+
+architecture test of tb is
+
+ component lattice_scm_fifo_18x32
+ port (Data : in std_logic_vector(17 downto 0);
+ WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic;
+ RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic;
+ Q : out std_logic_vector(17 downto 0); Empty: out std_logic;
+ Full: out std_logic
+ );
+ end component;
+
+ signal Data : std_logic_vector(17 downto 0) := (others => '0');
+ signal WrClock: std_logic := '0';
+ signal RdClock: std_logic := '0';
+ signal WrEn: std_logic := '0';
+ signal RdEn: std_logic := '0';
+ signal Reset: std_logic := '0';
+ signal RPReset: std_logic := '0';
+ signal Q : std_logic_vector(17 downto 0);
+ signal Empty: std_logic;
+ signal Full: std_logic;
+begin
+ u1 : lattice_scm_fifo_18x32
+ port map (Data => Data, WrClock => WrClock, RdClock => RdClock,
+ WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset,
+ Q => Q, Empty => Empty, Full => Full
+ );
+
+ process
+
+ begin
+ Data <= (others => '0') ;
+ wait for 100 ns;
+ wait until Reset = '0';
+ for i in 0 to 35 loop
+ wait until WrClock'event and WrClock = '1';
+ Data <= Data + '1' after 1 ns;
+ end loop;
+ wait;
+ end process;
+
+ WrClock <= not WrClock after 5.00 ns;
+
+ RdClock <= not RdClock after 5.00 ns;
+
+ process
+
+ begin
+ WrEn <= '0' ;
+ wait for 100 ns;
+ wait until Reset = '0';
+ for i in 0 to 35 loop
+ wait until WrClock'event and WrClock = '1';
+ WrEn <= '1' after 1 ns;
+ end loop;
+ WrEn <= '0' ;
+ wait;
+ end process;
+
+ process
+
+ begin
+ RdEn <= '0' ;
+ wait until Reset = '0';
+ wait until WrEn = '1';
+ wait until WrEn = '0';
+ for i in 0 to 35 loop
+ wait until RdClock'event and RdClock = '1';
+ RdEn <= '1' after 1 ns;
+ end loop;
+ RdEn <= '0' ;
+ wait;
+ end process;
+
+ process
+
+ begin
+ Reset <= '1' ;
+ wait for 100 ns;
+ Reset <= '0' ;
+ wait;
+ end process;
+
+ process
+
+ begin
+ RPReset <= '1' ;
+ wait for 100 ns;
+ RPReset <= '0' ;
+ wait;
+ end process;
+
+end architecture test;
--- /dev/null
+-- VHDL testbench template generated by SCUBA ispLever_v70_Prod_Build (55)
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+entity tb is
+end entity tb;
+
+
+architecture test of tb is
+
+ component lattice_scm_fifo_18x64
+ port (Data : in std_logic_vector(17 downto 0);
+ WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic;
+ RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic;
+ Q : out std_logic_vector(17 downto 0); Empty: out std_logic;
+ Full: out std_logic
+ );
+ end component;
+
+ signal Data : std_logic_vector(17 downto 0) := (others => '0');
+ signal WrClock: std_logic := '0';
+ signal RdClock: std_logic := '0';
+ signal WrEn: std_logic := '0';
+ signal RdEn: std_logic := '0';
+ signal Reset: std_logic := '0';
+ signal RPReset: std_logic := '0';
+ signal Q : std_logic_vector(17 downto 0);
+ signal Empty: std_logic;
+ signal Full: std_logic;
+begin
+ u1 : lattice_scm_fifo_18x64
+ port map (Data => Data, WrClock => WrClock, RdClock => RdClock,
+ WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset,
+ Q => Q, Empty => Empty, Full => Full
+ );
+
+ process
+
+ begin
+ Data <= (others => '0') ;
+ wait for 100 ns;
+ wait until Reset = '0';
+ for i in 0 to 67 loop
+ wait until WrClock'event and WrClock = '1';
+ Data <= Data + '1' after 1 ns;
+ end loop;
+ wait;
+ end process;
+
+ WrClock <= not WrClock after 5.00 ns;
+
+ RdClock <= not RdClock after 5.00 ns;
+
+ process
+
+ begin
+ WrEn <= '0' ;
+ wait for 100 ns;
+ wait until Reset = '0';
+ for i in 0 to 67 loop
+ wait until WrClock'event and WrClock = '1';
+ WrEn <= '1' after 1 ns;
+ end loop;
+ WrEn <= '0' ;
+ wait;
+ end process;
+
+ process
+
+ begin
+ RdEn <= '0' ;
+ wait until Reset = '0';
+ wait until WrEn = '1';
+ wait until WrEn = '0';
+ for i in 0 to 67 loop
+ wait until RdClock'event and RdClock = '1';
+ RdEn <= '1' after 1 ns;
+ end loop;
+ RdEn <= '0' ;
+ wait;
+ end process;
+
+ process
+
+ begin
+ Reset <= '1' ;
+ wait for 100 ns;
+ Reset <= '0' ;
+ wait;
+ end process;
+
+ process
+
+ begin
+ RPReset <= '1' ;
+ wait for 100 ns;
+ RPReset <= '0' ;
+ wait;
+ end process;
+
+end architecture test;
--- /dev/null
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.std_logic_ARITH.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+
+library work;
+use work.trb_net_std.all;
+
+entity trb_net_clock_generator is
+ generic(
+ FREQUENCY_IN : real := 100.0;
+ CLOCK_MULT : integer range 1 to 32 := 3;
+ CLOCK_DIV : integer range 1 to 32 := 1;
+ );
+ port(
+ RESET : in std_logic;
+ CLK_IN : in std_logic;
+ CLK_OUT : out std_logic;
+ LOCKED : out std_logic
+ );
+
+end entity;
+
+
+architecture trb_net_clock_generator_arch of trb_net_clock_generator is
+ component lattice_scm_clock_300
+ generic (SMI_OFFSET : in String := "0x410");
+ port (clk: in std_logic; clkop: out std_logic;
+ clkos: out std_logic; lock: out std_logic);
+ end component;
+
+
+begin
+
+ gen_3x : if CLOCK_MULT = 3 and CLOCK_DIV = 1 and FREQUENCY_IN = 100.0 generate
+
+-- parameterized module component instance
+ CLK_GEN : lattice_scm_clock_300
+ port map (
+ clk =>CLK_IN,
+ clkop=>CLK_OUT,
+ clkos=>open,
+ lock =>lock
+ );
+ end generate;
+
+ gen_none : if CLOCK_MULT /= 3 or CLOCK_DIV /= 1 or FREQUENCY_IN /= 100.0 generate
+ CLK_OUT <= CLK_IN;
+ LOCKED <= '0';
+ end generate;
+
+
+end architecture;
\ No newline at end of file
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+library work;
+use work.trb_net_std.all;
+
+entity trb_net_fifo_16bit_bram_dualport is
+ generic(
+ USE_STATUS_FLAGS : integer := c_YES
+ );
+ port (
+ read_clock_in: IN std_logic;
+ write_clock_in: IN std_logic;
+ read_enable_in: IN std_logic;
+ write_enable_in: IN std_logic;
+ fifo_gsr_in: IN std_logic;
+ write_data_in: IN std_logic_vector(17 downto 0);
+ read_data_out: OUT std_logic_vector(17 downto 0);
+ full_out: OUT std_logic;
+ empty_out: OUT std_logic;
+ fifostatus_out: OUT std_logic_vector(3 downto 0); --counter for 1/16th of fifo
+ valid_read_out: OUT std_logic;
+ almost_empty_out:OUT std_logic;
+ almost_full_out :OUT std_logic
+ );
+end entity trb_net_fifo_16bit_bram_dualport;
+
+architecture trb_net_fifo_16bit_bram_dualport_arch of trb_net_fifo_16bit_bram_dualport is
+
+ component lattice_scm_fifo_16bit_dualport
+ port (Data: in std_logic_vector(17 downto 0);
+ WrClock: in std_logic; RdClock: in std_logic;
+ WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic;
+ RPReset: in std_logic; Q: out std_logic_vector(17 downto 0);
+ Empty: out std_logic; Full: out std_logic;
+ AlmostEmpty: out std_logic; AlmostFull: out std_logic);
+ end component;
+
+BEGIN
+ FIFO_DP_BRAM : lattice_scm_fifo_16bit_dualport
+ port map (
+ Data => write_data_in,
+ WrClock => write_clock_in,
+ RdClock => read_clock_in,
+ WrEn => write_enable_in,
+ RdEn => read_enable_in,
+ Reset => fifo_gsr_in,
+ RPReset => '0',
+ Q => read_data_out,
+ Empty => empty_out,
+ Full => full_out,
+ AlmostEmpty => almost_empty_out,
+ AlmostFull => almost_full_out
+ );
+
+end architecture trb_net_fifo_16bit_bram_dualport_arch;
+
jspc29 / trbnet.git / commitdiff