added tb_dsp_interface.vhd, Attilio

diff --git a/dsp_interface.vhd b/dsp_interface.vhd
index 9a734c7007aee125c6975f2d36e3def547f5477a..a8c04e5e66d9a370ff36eeaefe265a9809f50a51 100644 (file)
--- a/dsp_interface.vhd
+++ b/dsp_interface.vhd
@@ -135,33 +135,32 @@ begin  -- behavioural
         next_state  <= READ_DSP_WAIT1;
         
       when READ_DSP_WAIT1 =>
-        debug_register  <= "011";
-        ADDRESS_DSP <= reg_address_dsp;
-
+         debug_register  <= "011";
+         next_state <= READ_DSP_WAIT2;
          RD_OUT      <= '1';
---         WRL         <= '1';
+         WRL         <= '1';
          WRL         <= '1';
          HBR_OUT     <= '0';
-                 next_state <= READ_DSP_WAIT2;
 
       when READ_DSP_WAIT2 =>
-
+         debug_register  <= "100";
+                       next_state <= READ_DSP_WAIT3;
          RD_OUT      <= '1';
          WRL         <= '1';
          WRL         <= '1';
          HBR_OUT     <= '0';
-         next_state <= READ_DSP_WAIT3;
+
          
       when READ_DSP_WAIT3 =>
-        debug_register  <= "100";
-
+        debug_register  <= "101";
+         next_state <= READ_DSP_MEMORY;
          RD_OUT      <= '1';
          WRL         <= '1';
          WRL         <= '1';
          HBR_OUT     <= '0';
-         next_state <= READ_DSP_MEMORY;
+
       when READ_DSP_MEMORY  =>
-        debug_register  <= "101";
+        debug_register  <= "110";
          RD_OUT      <= '1';
          WRL         <= '1';
          WRL         <= '1';
@@ -169,14 +168,13 @@ begin  -- behavioural
         if ACK = '0' then
           next_state    <= READ_DSP_MEMORY;
         else
-
-          next_read_dsp_data <= DSP_DATA;
           next_state    <= SENT_DATA_TO_INTERNAL_ENTITY;
+          next_read_dsp_data <= DSP_DATA;
         end if;
 
          
       when SENT_DATA_TO_INTERNAL_ENTITY =>
-        debug_register  <= "110";
+        debug_register  <= "111";
         VALID_DATA_SENT <= '1';
         INTERNAL_DATA   <= reg_read_dsp_data;
         next_state      <= IDLE;

diff --git a/tb_dsp_interface.vhd b/tb_dsp_interface.vhd
new file mode 100644 (file)
index 0000000..6eef751
--- /dev/null
+++ b/tb_dsp_interface.vhd
@@ -0,0 +1,177 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all;
+USE ieee.numeric_std.ALL;
+
+ENTITY dsp_inteface_vhd IS
+END dsp_inteface_vhd;
+
+ARCHITECTURE behavior OF dsp_inteface_vhd IS 
+
+       -- Component Declaration for the Unit Under Test (UUT)
+       COMPONENT dsp_interface
+       PORT(
+               HBG_IN : IN std_logic;
+               BM_IN : IN std_logic;
+               ACK : IN std_logic;
+               CLK : IN std_logic;
+               RESET : IN std_logic;
+               R_W_ENABLE : IN std_logic;
+               TRIGGER : IN std_logic;
+               INTERNAL_ADDRESS : IN std_logic_vector(31 downto 0);
+               ACKNOWLEDGE : IN std_logic;    
+               DSP_DATA : INOUT std_logic_vector(31 downto 0);
+               WRL : INOUT std_logic;
+               WRH : INOUT std_logic;
+               BRST : INOUT std_logic;
+               INTERNAL_DATA : INOUT std_logic_vector(31 downto 0);      
+               HBR_OUT : OUT std_logic;
+               RD_OUT : OUT std_logic;
+               ADDRESS_DSP : OUT std_logic_vector(31 downto 0);
+               DSP_RESET : OUT std_logic;
+               VALID_DATA_SENT : OUT std_logic;
+               DEBUGSTATE_MACHINE : OUT std_logic_vector(31 downto 0)
+               );
+       END COMPONENT;
+
+       --Inputs
+       SIGNAL HBG_IN_i :  std_logic := '0';
+       SIGNAL BM_IN_i :  std_logic := '0';
+       SIGNAL ACK_i :  std_logic := '0';
+       SIGNAL CLK_i:  std_logic := '0';
+       SIGNAL RESET_i :  std_logic := '0';
+       SIGNAL R_W_ENABLE_i :  std_logic := '0';
+       SIGNAL TRIGGER_i :  std_logic := '0';
+       SIGNAL ACKNOWLEDGE_i :  std_logic := '0';
+       SIGNAL INTERNAL_ADDRESS_i :  std_logic_vector(31 downto 0) := (others=>'0');
+
+       --BiDirs
+       SIGNAL DSP_DATA_i :  std_logic_vector(31 downto 0);
+       SIGNAL WRL_i :  std_logic;
+       SIGNAL WRH_i :  std_logic;
+       SIGNAL BRST_i :  std_logic;
+       SIGNAL INTERNAL_DATA_i :  std_logic_vector(31 downto 0);
+
+       --Outputs
+       SIGNAL HBR_OUT_i :  std_logic;
+       SIGNAL RD_OUT_i :  std_logic;
+       SIGNAL ADDRESS_DSP_i :  std_logic_vector(31 downto 0);
+       SIGNAL DSP_RESET_i :  std_logic;
+       SIGNAL VALID_DATA_SENT_i :  std_logic;
+       SIGNAL DEBUGSTATE_MACHINE_i :  std_logic_vector(31 downto 0);
+
+BEGIN
+
+       -- Instantiate the Unit Under Test (UUT)
+       uut: dsp_interface PORT MAP(
+               HBR_OUT => HBR_OUT_i,
+               HBG_IN => HBG_IN_i,
+               RD_OUT => RD_OUT_i,
+               DSP_DATA => DSP_DATA_i,
+               ADDRESS_DSP => ADDRESS_DSP_i,
+               WRL => WRL_i,
+               WRH => WRH_i,
+               BM_IN => BM_IN_i,
+               DSP_RESET => DSP_RESET_i,
+               BRST => BRST_i,
+               ACK => ACK_i,
+               CLK => CLK_i,
+               RESET => RESET_i,
+               R_W_ENABLE => R_W_ENABLE_i,
+               TRIGGER => TRIGGER_i,
+               INTERNAL_DATA => INTERNAL_DATA_i,
+               INTERNAL_ADDRESS => INTERNAL_ADDRESS_i,
+               VALID_DATA_SENT => VALID_DATA_SENT_i,
+               ACKNOWLEDGE => ACKNOWLEDGE_i,
+               DEBUGSTATE_MACHINE => DEBUGSTATE_MACHINE_i
+       );
+
+       tb : PROCESS
+       BEGIN
+------------------------
+--read data from dsp
+------------------------
+ wait for 10 ns;
+  RESET_i <= '0';
+  wait for 10 ns;
+  RESET_i <= '1';
+  wait for 20 ns;
+  RESET_i <= '0';
+  wait for 20 ns;
+  HBG_IN_i <= '1';
+  wait for 20 ns;
+  RESET_i <= '0';
+  TRIGGER_i <= '0';
+  wait for 20 ns;
+  TRIGGER_i <= '1';
+  R_W_ENABLE_i <= '1';
+  INTERNAL_DATA_i <= (others => 'Z');
+  DSP_DATA_i <= x"dadadada";
+  INTERNAL_ADDRESS_i <= x"11111111";
+  wait for 10 ns;
+  R_W_ENABLE_i <= '1';            --read dsp data
+  wait for 50 ns;
+  TRIGGER_i <= '0';
+  HBG_IN_i <= '0';
+  ACK_i <= '0';
+  wait for 50 ns;
+  ACK_i <='1';
+  wait for 300 ns;
+  ACK_i <='0';
+  wait for 50 ns;
+  ACKNOWLEDGE_i <= '1';
+  HBG_IN_i <= '1';
+  R_W_ENABLE_i <= '0';
+  --wait for 200 ns;
+  --ACK_i <='0';
+  wait for 30 ns;
+  ACKNOWLEDGE_i <= '0';
+  wait for 300 ns;
+---------------
+--write into dsp
+----------------
+    RESET_i <= '1';
+    wait for 20 ns;
+    RESET_i <= '0';
+    wait for 10 ns;
+    DSP_DATA_i <=  (others => 'Z');
+    --INTERNAL_DATA_i <= (others => 'Z');
+    INTERNAL_DATA_i <= x"deadface";
+    INTERNAL_ADDRESS_i <= x"01010101";
+    R_W_ENABLE_i <= '0';
+    wait for 200 ns;
+    HBG_IN_i <= '0';
+    wait for 10 ns;
+    TRIGGER_i <= '1';
+    wait for 20 ns;
+    R_W_ENABLE_i <= '0';
+    wait for 5 ns;
+    TRIGGER_i <= '0';
+    R_W_ENABLE_i <= '1';
+    HBG_IN_i <= '0';
+    wait for 50 ns;
+    ACK_i <='1';
+        wait for 100 ns;
+        ACK_i <='0';
+        wait for 100 ns;
+    ACKNOWLEDGE_i <= '1';
+    wait for 100 ns;
+    HBG_IN_i <= '1';
+    wait for 100 ns;
+  -- Wait 100 ns for global reset to finish
+  wait for 100 ns;
+  
+  
+  
+  
+
+               wait; -- will wait forever
+       END PROCESS;
+       
+       clk_gen : process
+begin  -- process clk_gen
+  CLK_i <= not CLK_i;
+  wait for 10 ns;
+end process clk_gen;
+
+END;