In order to increase the hardware independence of the design, the CTS consists of two major
building blocks: The \emph{Network Logic} handles the network interfaces (which are not part of the CTS design itself)
- and propagates event information gathered by the \emph{Trigger Logic} (see figure~\ref{fig:cts_structural_overview}).
+ and propagates event information gathered by the \emph{Trigger
+ Logic} (see figure~\ref{fig:cts_structural_overview}).
\subsection{CTS Network Logic}
The CTS uses two dedicated network endpoints for communications: The \emph{CTS Endpoint} is obviously needed due to
0x2a & \texttt{0x35c3e3e1} & Timestamp \\\hline
\multicolumn{3}{c}{End of CTS Data. Remaining words are from External Trigger Logic}\\\hline
- 0x2b & \texttt{0x10000000} & CBM-MBS word (see table \ref{tab:cts_cbm_data_word}) \\\hline
+ 0x2b & \texttt{0x10000000} & External trigger module word %(see table \ref{tab:cts_cbm_data_word})
+ \\\hline
\end{tabular}
\caption{Example of CTS Package. The data in the subsubevent appears in the same order as the
generate pseudo random numbers (PRN). If multiple instance of the pulser are synthesised with different constants. As
simulations suggest, the values generated are nearly uniform deviates.
Furthermore, the distance between two successive numbers is also distributed almost uniformly and
- seems to be uncorrelated to their magnitude (see figure~\ref{fig:cts_bb_trigger_logic_pseudorand}).
+ seems to be uncorrelated to their magnitude. % (see figure~\ref{fig:cts_bb_trigger_logic_pseudorand}).
In each clock cycle a random number is compared with a configurable threshold. If it is smaller, an event
is produced. Since the numbers are uniform deviates, the average duty cycle of the pulser is given
- by the threshold divided by the maximum value possible (see figure~\ref{fig:cts_bb_trigger_logic_pseudorand}a).
+ by the threshold divided by the maximum value possible. % (see figure~\ref{fig:cts_bb_trigger_logic_pseudorand}a).
In addition, the uniformly distributed distances prevent the clustering of events that can be observed with
other pseudorandom number generators, such as linear feedback shift registers.
dependency between the average trigger rate $F$ and the threshold $T$ given by
$F(T) = \frac{ 100\text{~MHz} } {2^{32} - 1} \cdot T$.
- \item \textbf{\addr{0x60} External logic- CBM/MBS}. This module indicates the presence of the CBM adapter
+ \item \textbf{\addr{0x60} External logic - CBM/MBS}. This module indicates the presence of the CBM adapter
module. If set, the lowest bit of the control registers prevents the module from sending data to the
event builder. The lower 24~bit of the status register contains the timestamp of the last event seen. The
MSB holds the error flag.
year = "2009",
url = "http://www.latticesemi.com/documents/HB1003.pdf"
}
+
+@Misc{penschuck12,
+ author = {Penschuck, Manuel},
+ title = {Development and Implementation of
+a Central Trigger System for TrbNet-based systems},
+ howpublished = {Bachelor Thesis, Uni Frankfurt},
+ year = 2012,
+}
+
+
\section[CTS]{CTS\footnote{If not explicitly stated otherwise, in this chapter, CTS refers to the trigger system embeddable into the central
FPGA of a TRB3.}}
\subsection{Features}
- \input{CtsFeatures}
- %\subsection{Software}
- % \input{CtsGettingStarted}
- %\subsection{Building Blocks}
+ \input{CtsFeatures}
+ \subsection{Getting Started}
+ \input{CtsGettingStarted}
+ \subsection{Building Blocks}
\input{CtsBuildingBlocks}
\subsection{Slow Control Registers}
\input{CtsSlowControl}