design information update for TDC table

diff --git a/trb3/IncludedFeaturesTable.tex b/trb3/IncludedFeaturesTable.tex
index 8276394a96cd426b633c83c730e4038b024a3632..eb2b9c2ce5656c08a30b7ff600cad7f004dea8bd 100644 (file)
--- a/trb3/IncludedFeaturesTable.tex
+++ b/trb3/IncludedFeaturesTable.tex
@@ -1,4 +1,4 @@
-\begin{longtable}{|p{0.05\textwidth}|p{0.08\textwidth}|p{0.13\textwidth}|X|}
+\begin{longtable}{|p{0.05\textwidth}|p{0.08\textwidth}|p{0.16\textwidth}|X|}
 \hline
 \textbf{Table} & \textbf{Bit} & \textbf{Name} & \textbf{Description} \\
 \hline\hline
@@ -33,7 +33,10 @@ CTS registers. \\
 1-to-1, 2: every second input (e.g. Padiwa Amps fast-only), 3: every fourth input (HPTDC very high speed mode)\\
  & 11 -- 8  & DoubleEdge  & Double edge setup: 0: single edge only, 1: same channel, 2: alternating channels, 3: same 
 channel with stretcher \\
+ & 14 -- 12 & RingBuffer  & Ring Buffer size: 0:12 words, 1:44 words, 2:76 
+words, 3:108 words \\
  & 15       & TDC         & Contains a TDC \\
+ & 17 -- 16 & ReadoutModule & Number of readout modules \\
  & 42       & Spi         & Contains SPI on all relevant I/Os depending on AddOn board design\\
  & 43       & Uart        & Contains an Uart\\
  & 47 -- 44 & InpMonitor  & See table 1. Pinout should match the one of the TDC\\